mirror of
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Updating prebuilts and/or headers
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nvdisplay/src/nvidia-modeset/include/nvkms-hal.h d4889d903bf4de06d85e55b005206ed57f28af69 - nvdisplay/src/nvidia-modeset/include/nvkms-lut.h 9dd131355ed1e25a7cee7bfef00501cf6427ae92 - nvdisplay/src/nvidia-modeset/include/nvkms-private.h 8a6f26ccf2e563b78f6e189c999ba470ed35271d - nvdisplay/src/nvidia-modeset/include/nvkms-evo.h 75e8a8747795fad89b4d2b662477e5454863dcc7 - nvdisplay/src/nvidia-modeset/include/nvkms-flip.h d3f5bc85b538a3a1d4c2389c81001be91205ec9f - nvdisplay/src/nvidia-modeset/include/nvkms-modeset-types.h 260b6ef87c755e55a803adad4ce49f2d57315f9a - nvdisplay/src/nvidia-modeset/include/nvkms-event.h 867e3091a945d3d43b2f28393b40edeb9d27597b - nvdisplay/src/nvidia-modeset/include/nvkms-rmapi.h 118d0ea84ff81de16fbdc2c7daf249ee5c82ed6e - nvdisplay/src/nvidia-modeset/include/nvkms-modepool.h c8f714e80dd4bb60ceab0c0c7e6a5b3304940946 - nvdisplay/src/nvidia-modeset/include/nvkms-types.h 71e8c5d3c4dfec6f2261654c3fc91210bff78da9 - nvdisplay/src/nvidia-modeset/include/nvkms-surface.h 52b6c19cce320677bd3a4dfcf1698b236f29e59e - nvdisplay/src/nvidia-modeset/include/dp/nvdp-device.h 4625828efd425e1b29835ab91fcc3d2d85e92389 - nvdisplay/src/nvidia-modeset/include/dp/nvdp-connector-event-sink.h a8fbb7a071c0e7b326f384fed7547e7b6ec81c3e - nvdisplay/src/nvidia-modeset/include/dp/nvdp-timer.h 17f6fbbd5e0a75faec21347b691f44dcb65c01aa - nvdisplay/src/nvidia-modeset/include/dp/nvdp-connector.h 727bd77cfbc9ac4989c2ab7eec171ceb516510aa - nvdisplay/src/nvidia-modeset/kapi/include/nvkms-kapi-notifiers.h e48c2ec8145a6f2099dddb24d2900e3ae94ec02e - nvdisplay/src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h f6875ef0da055900ef6ef1da5dc94cba2837e4d0 - nvdisplay/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c 394ea31caa5957cfb2c8bb8c3cc0e4703213fe7f - nvdisplay/src/nvidia-modeset/kapi/src/nvkms-kapi.c 01d943d6edb0c647c2b8dbc44460948665b03e7a - nvdisplay/src/nvidia-modeset/kapi/src/nvkms-kapi-notifiers.c fb242aa7a53983118ee019415076033e596374af - nvdisplay/src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h 009cd8e2b7ee8c0aeb05dac44cc84fc8f6f37c06 - nvdisplay/src/nvidia-modeset/kapi/interface/nvkms-kapi.h f8bdd07a27296ef6aab86cc9dbccf8df811fff24 - nvdisplay/src/nvidia-modeset/src/nvkms-modeset.c 21c8184de2c9150c21ac5d6fba24e79e513a0a69 - nvdisplay/src/nvidia-modeset/src/nvkms-evo.c 1918ca3aa611cd9dfc79d46d038ab22706f0b1ed - nvdisplay/src/nvidia-modeset/src/nvkms-cursor3.c fc8182cc1f3af77125dbfa328996bcfe0387cc41 - nvdisplay/src/nvidia-modeset/src/nvkms-rm.c 45230e56d29c98ea0f10f87c1b16ba70c96f24d5 - nvdisplay/src/nvidia-modeset/src/nvkms-evo3.c 05548338a73ade1b3c2ad1cebf1ab5eb16ef6c9b - nvdisplay/src/nvidia-modeset/src/nvkms-flip.c 673ad86616f9863766bfec0e118c918297d32010 - nvdisplay/src/nvidia-modeset/src/g_nvkms-evo-states.c 85ddb19f89833ca57fd2deff2e2b4566e162a56c - nvdisplay/src/nvidia-modeset/src/nvkms-hal.c 5acf19920d56793d96c80e8461b0d0213c871b34 - nvdisplay/src/nvidia-modeset/src/nvkms-surface.c 8f22c278a5839d36f74f85469b2d927d9265cb80 - nvdisplay/src/nvidia-modeset/src/nvkms-utils.c 94f4736acf7981cebfd74302a21f19cdbafa8d71 - nvdisplay/src/nvidia-modeset/src/nvkms-hdmi.c 24156462f25922c8de5b5d2558db36b2e68b28ed - nvdisplay/src/nvidia-modeset/src/nvkms-dpy.c eb09642e8b5d9333699f817caaf20483c840b376 - nvdisplay/src/nvidia-modeset/src/nvkms.c ab17e5b4cafa92aa03691a0c187ef8c9ae53fa59 - nvdisplay/src/nvidia-modeset/src/nvkms-cursor.c b55665d7bceaad04bbf29a68f44536518302c3d6 - nvdisplay/src/nvidia-modeset/src/nvkms-evo2.c 8415bcd6ab34e356374659e965790a0715ed7971 - nvdisplay/src/nvidia-modeset/src/nvkms-prealloc.c 07c2f10473e2fbe921b2781cc107b5e56e6373e3 - nvdisplay/src/nvidia-modeset/src/nvkms-attributes.c f27f52dc428a6adeb936c8cf99e1fc2d8b0ad667 - nvdisplay/src/nvidia-modeset/src/nvkms-dma.c da726d20eea99a96af4c10aace88f419e8ee2a34 - nvdisplay/src/nvidia-modeset/src/nvkms-event.c c98f76bcfc7c654a619762ebc3a2599f9aa89f8d - nvdisplay/src/nvidia-modeset/src/nvkms-3dvision.c c2870190ca4c4d5b3a439386583d0a7c193d6263 - nvdisplay/src/nvidia-modeset/src/nvkms-hw-states.c c799d52bdc792efc377fb5cd307b0eb445c44d6a - nvdisplay/src/nvidia-modeset/src/nvkms-cursor2.c c2d0e6bef0c4929a3ca4adfd74bd6168fa4aa000 - nvdisplay/src/nvidia-modeset/src/nvkms-framelock.c e9626eee225e58ec2d5be756c5015775ca5e54b9 - nvdisplay/src/nvidia-modeset/src/nvkms-vrr.c 5c79c271609ebcc739f8d73d7d47f0b376298438 - nvdisplay/src/nvidia-modeset/src/nvkms-rmapi-dgpu.c 86da3c7c09354d2c49d95562aba15cbedb543d9b - nvdisplay/src/nvidia-modeset/src/nvkms-evo1.c 574b1268ff83e4e5ed4da15609247a5c0ec8f51b - nvdisplay/src/nvidia-modeset/src/nvkms-console-restore.c ec97ab37cdf2cec0283657c2c04a139a1a168337 - nvdisplay/src/nvidia-modeset/src/nvkms-modepool.c 5fb73f35841c41e7376531732cb12303224e61ad - nvdisplay/src/nvidia-modeset/src/nvkms-lut.c f96cd982b4c05351faa31d04ac30d6fa7c866bcb - nvdisplay/src/nvidia-modeset/src/dp/nvdp-timer.cpp 6b985fc50b5040ce1a81418bed73a60edb5d3289 - nvdisplay/src/nvidia-modeset/src/dp/nvdp-timer.hpp 8af6062034d464f778969e26d3bf5a9b4cdaccf0 - nvdisplay/src/nvidia-modeset/src/dp/nvdp-connector.cpp f6c3e8bd4ee13970737e96f9d9a3e4d8afdf9695 - nvdisplay/src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp f2a05c29383bfc8631ad31909f31a8351501eb27 - nvdisplay/src/nvidia-modeset/src/dp/nvdp-device.cpp 31767fd551f3c89e5b00f54147b6a8e8fa3320e3 - nvdisplay/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp 51af3c1ee6b74ee0c9add3fb7d50cbc502980789 - nvdisplay/src/nvidia-modeset/src/dp/nvdp-evo-interface.hpp 110ac212ee8832c3fa3c4f45d6d33eed0301e992 - nvdisplay/src/nvidia-modeset/src/dp/nvdp-host.cpp 69fed95ab3954dd5cb26590d02cd8ba09cdff1ac - nvdisplay/src/nvidia-modeset/src/dp/nvdp-connector-event-sink.hpp 7d108165b4a7b6a44ac21460ea3bf4381fb48c5b - nvdisplay/src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h 17855f638fd09abfec7d188e49b396793a9f6106 - nvdisplay/src/nvidia-modeset/os-interface/include/nvkms.h 445a409950ab8f36cfa24d1dc73e59718d335263 - nvdisplay/src/nvidia-modeset/interface/nvkms-api.h 5c4c05e5a638888babb5a8af2f0a61c94ecd150b - nvdisplay/src/nvidia-modeset/interface/nvkms-format.h 2ea1436104463c5e3d177e8574c3b4298976d37e - nvdisplay/src/nvidia-modeset/interface/nvkms-ioctl.h 910255a4d92e002463175a28e38c3f24716fb654 - nvdisplay/src/nvidia-modeset/interface/nvkms-api-types.h 281fdc23f82d8bdb94b26d0093b444eb0c056f51 - nvdisplay/src/nvidia-modeset/interface/nvkms-sync.h Change-Id: I7bb776aa8b86d8401aba1cbe9e6c56713750eba2
This commit is contained in:
svcmobrel-release
34
nvdisplay/kernel-open/common/inc/conftest.h
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34
nvdisplay/kernel-open/common/inc/conftest.h
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@@ -0,0 +1,34 @@
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||||
/*
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* SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
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* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
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||||
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||||
#ifndef _CONFTEST_H
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#define _CONFTEST_H
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#include "conftest/headers.h"
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#include "conftest/functions.h"
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#include "conftest/generic.h"
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#include "conftest/macros.h"
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#include "conftest/symbols.h"
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#include "conftest/types.h"
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||||
#endif
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453
nvdisplay/kernel-open/common/inc/cpuopsys.h
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453
nvdisplay/kernel-open/common/inc/cpuopsys.h
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@@ -0,0 +1,453 @@
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/*
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||||
* SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
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||||
|
||||
/*! \brief
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||||
* Define compile time symbols for CPU type and operating system type.
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* This file should only contain preprocessor commands so that
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* there are no dependencies on other files.
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*
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* cpuopsys.h
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*
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* Copyright (c) 2001, Nvidia Corporation. All rights reserved.
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*/
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/*!
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||||
* Uniform names are defined for compile time options to distinguish
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* CPU types and Operating systems.
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||||
* Distinctions between CPU and OpSys should be orthogonal.
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*
|
||||
* These uniform names have initially been defined by keying off the
|
||||
* makefile/build names defined for builds in the OpenGL group.
|
||||
* Getting the uniform names defined for other builds may require
|
||||
* different qualifications.
|
||||
*
|
||||
* The file is placed here to allow for the possibility of all driver
|
||||
* components using the same naming convention for conditional compilation.
|
||||
*/
|
||||
|
||||
#ifndef CPUOPSYS_H
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||||
#define CPUOPSYS_H
|
||||
|
||||
/*****************************************************************************/
|
||||
/* Define all OS/CPU-Chip related symbols */
|
||||
|
||||
/* ***** WINDOWS variations */
|
||||
#if defined(_WIN32) || defined(_WIN16)
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||||
# define NV_WINDOWS
|
||||
|
||||
# if defined(_WIN32_WINNT)
|
||||
# define NV_WINDOWS_NT
|
||||
# elif defined(_WIN32_WCE)
|
||||
# define NV_WINDOWS_CE
|
||||
# elif !defined(NV_MODS)
|
||||
# define NV_WINDOWS_9X
|
||||
# endif
|
||||
#endif /* _WIN32 || defined(_WIN16) */
|
||||
|
||||
/* ***** Unix variations */
|
||||
#if defined(__linux__) && !defined(NV_LINUX) && !defined(NV_VMWARE)
|
||||
# define NV_LINUX
|
||||
#endif /* defined(__linux__) */
|
||||
|
||||
#if defined(__VMWARE__) && !defined(NV_VMWARE)
|
||||
# define NV_VMWARE
|
||||
#endif /* defined(__VMWARE__) */
|
||||
|
||||
/* SunOS + gcc */
|
||||
#if defined(__sun__) && defined(__svr4__) && !defined(NV_SUNOS)
|
||||
# define NV_SUNOS
|
||||
#endif /* defined(__sun__) && defined(__svr4__) */
|
||||
|
||||
/* SunOS + Sun Compiler (named SunPro, Studio or Forte) */
|
||||
#if defined(__SUNPRO_C) || defined(__SUNPRO_CC)
|
||||
# define NV_SUNPRO_C
|
||||
# define NV_SUNOS
|
||||
#endif /* defined(_SUNPRO_C) || defined(__SUNPRO_CC) */
|
||||
|
||||
#if defined(__FreeBSD__) && !defined(NV_BSD)
|
||||
# define NV_BSD
|
||||
#endif /* defined(__FreeBSD__) */
|
||||
|
||||
/* XXXar don't define NV_UNIX on MacOSX or vxworks or QNX */
|
||||
#if (defined(__unix__) || defined(__unix) || defined(__INTEGRITY) ) && !defined(nvmacosx) && !defined(vxworks) && !defined(NV_UNIX) && !defined(__QNX__) && !defined(__QNXNTO__)/* XXX until removed from Makefiles */
|
||||
# define NV_UNIX
|
||||
#endif /* defined(__unix__) */
|
||||
|
||||
#if (defined(__QNX__) || defined(__QNXNTO__)) && !defined(NV_QNX)
|
||||
# define NV_QNX
|
||||
#endif
|
||||
|
||||
#if (defined(__ANDROID__) || defined(ANDROID)) && !defined(NV_ANDROID)
|
||||
# define NV_ANDROID
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(DceCore) && !defined(NV_DCECORE)
|
||||
# define NV_DCECORE
|
||||
#endif
|
||||
|
||||
/* ***** Apple variations */
|
||||
#if defined(macintosh) || defined(__APPLE__)
|
||||
# define NV_MACINTOSH
|
||||
# if defined(__MACH__)
|
||||
# define NV_MACINTOSH_OSX
|
||||
# else
|
||||
# define NV_MACINTOSH_OS9
|
||||
# endif
|
||||
# if defined(__LP64__)
|
||||
# define NV_MACINTOSH_64
|
||||
# endif
|
||||
#endif /* defined(macintosh) */
|
||||
|
||||
/* ***** VxWorks */
|
||||
/* Tornado 2.21 is gcc 2.96 and #defines __vxworks. */
|
||||
/* Tornado 2.02 is gcc 2.7.2 and doesn't define any OS symbol, so we rely on */
|
||||
/* the build system #defining vxworks. */
|
||||
#if defined(__vxworks) || defined(vxworks)
|
||||
# define NV_VXWORKS
|
||||
#endif
|
||||
|
||||
/* ***** Integrity OS */
|
||||
#if defined(__INTEGRITY)
|
||||
# if !defined(NV_INTEGRITY)
|
||||
# define NV_INTEGRITY
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* ***** Processor type variations */
|
||||
/* Note: The prefix NV_CPU_* is taken by Nvcm.h */
|
||||
|
||||
#if ((defined(_M_IX86) || defined(__i386__) || defined(__i386)) && !defined(NVCPU_X86)) /* XXX until removed from Makefiles */
|
||||
/* _M_IX86 for windows, __i386__ for Linux (or any x86 using gcc) */
|
||||
/* __i386 for Studio compiler on Solaris x86 */
|
||||
# define NVCPU_X86 /* any IA32 machine (not x86-64) */
|
||||
# define NVCPU_MIN_PAGE_SHIFT 12
|
||||
#endif
|
||||
|
||||
#if defined(_WIN32) && defined(_M_IA64)
|
||||
# define NVCPU_IA64_WINDOWS /* any IA64 for Windows opsys */
|
||||
#endif
|
||||
#if defined(NV_LINUX) && defined(__ia64__)
|
||||
# define NVCPU_IA64_LINUX /* any IA64 for Linux opsys */
|
||||
#endif
|
||||
#if defined(NVCPU_IA64_WINDOWS) || defined(NVCPU_IA64_LINUX) || defined(IA64)
|
||||
# define NVCPU_IA64 /* any IA64 for any opsys */
|
||||
#endif
|
||||
|
||||
#if (defined(NV_MACINTOSH) && !(defined(__i386__) || defined(__x86_64__))) || defined(__PPC__) || defined(__ppc)
|
||||
# if defined(__powerpc64__) && defined(__LITTLE_ENDIAN__)
|
||||
# ifndef NVCPU_PPC64LE
|
||||
# define NVCPU_PPC64LE /* PPC 64-bit little endian */
|
||||
# endif
|
||||
# else
|
||||
# ifndef NVCPU_PPC
|
||||
# define NVCPU_PPC /* any non-PPC64LE PowerPC architecture */
|
||||
# endif
|
||||
# ifndef NV_BIG_ENDIAN
|
||||
# define NV_BIG_ENDIAN
|
||||
# endif
|
||||
# endif
|
||||
# define NVCPU_FAMILY_PPC
|
||||
#endif
|
||||
|
||||
#if defined(__x86_64) || defined(AMD64) || defined(_M_AMD64)
|
||||
# define NVCPU_X86_64 /* any x86-64 for any opsys */
|
||||
#endif
|
||||
|
||||
#if defined(NVCPU_X86) || defined(NVCPU_X86_64)
|
||||
# define NVCPU_FAMILY_X86
|
||||
#endif
|
||||
|
||||
#if defined(__riscv) && (__riscv_xlen==64)
|
||||
# define NVCPU_RISCV64
|
||||
# if defined(__nvriscv)
|
||||
# define NVCPU_NVRISCV64
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(__arm__) || defined(_M_ARM)
|
||||
/*
|
||||
* 32-bit instruction set on, e.g., ARMv7 or AArch32 execution state
|
||||
* on ARMv8
|
||||
*/
|
||||
# define NVCPU_ARM
|
||||
# define NVCPU_MIN_PAGE_SHIFT 12
|
||||
#endif
|
||||
|
||||
#if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64)
|
||||
# define NVCPU_AARCH64 /* 64-bit A64 instruction set on ARMv8 */
|
||||
# define NVCPU_MIN_PAGE_SHIFT 12
|
||||
#endif
|
||||
|
||||
#if defined(NVCPU_ARM) || defined(NVCPU_AARCH64)
|
||||
# define NVCPU_FAMILY_ARM
|
||||
#endif
|
||||
|
||||
#if defined(__SH4__)
|
||||
# ifndef NVCPU_SH4
|
||||
# define NVCPU_SH4 /* Renesas (formerly Hitachi) SH4 */
|
||||
# endif
|
||||
# if defined NV_WINDOWS_CE
|
||||
# define NVCPU_MIN_PAGE_SHIFT 12
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* For Xtensa processors */
|
||||
#if defined(__XTENSA__)
|
||||
# define NVCPU_XTENSA
|
||||
# if defined(__XTENSA_EB__)
|
||||
# define NV_BIG_ENDIAN
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Other flavors of CPU type should be determined at run-time.
|
||||
* For example, an x86 architecture with/without SSE.
|
||||
* If it can compile, then there's no need for a compile time option.
|
||||
* For some current GCC limitations, these may be fixed by using the Intel
|
||||
* compiler for certain files in a Linux build.
|
||||
*/
|
||||
|
||||
/* The minimum page size can be determined from the minimum page shift */
|
||||
#if defined(NVCPU_MIN_PAGE_SHIFT)
|
||||
#define NVCPU_MIN_PAGE_SIZE (1 << NVCPU_MIN_PAGE_SHIFT)
|
||||
#endif
|
||||
|
||||
#if defined(NVCPU_IA64) || defined(NVCPU_X86_64) || \
|
||||
defined(NV_MACINTOSH_64) || defined(NVCPU_AARCH64) || \
|
||||
defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64)
|
||||
# define NV_64_BITS /* all architectures where pointers are 64 bits */
|
||||
#else
|
||||
/* we assume 32 bits. I don't see a need for NV_16_BITS. */
|
||||
#endif
|
||||
|
||||
/* For verification-only features not intended to be included in normal drivers */
|
||||
#if defined(NV_MODS) && defined(DEBUG) && !defined(DISABLE_VERIF_FEATURES)
|
||||
#define NV_VERIF_FEATURES
|
||||
#endif
|
||||
|
||||
/*
|
||||
* New, safer family of #define's -- these ones use 0 vs. 1 rather than
|
||||
* defined/!defined. This is advantageous because if you make a typo,
|
||||
* say misspelled ENDIAN:
|
||||
*
|
||||
* #if NVCPU_IS_BIG_ENDAIN
|
||||
*
|
||||
* ...some compilers can give you a warning telling you that you screwed up.
|
||||
* The compiler can also give you a warning if you forget to #include
|
||||
* "cpuopsys.h" in your code before the point where you try to use these
|
||||
* conditionals.
|
||||
*
|
||||
* Also, the names have been prefixed in more cases with "CPU" or "OS" for
|
||||
* increased clarity. You can tell the names apart from the old ones because
|
||||
* they all use "_IS_" in the name.
|
||||
*
|
||||
* Finally, these can be used in "if" statements and not just in #if's. For
|
||||
* example:
|
||||
*
|
||||
* if (NVCPU_IS_BIG_ENDIAN) x = Swap32(x);
|
||||
*
|
||||
* Maybe some day in the far-off future these can replace the old #define's.
|
||||
*/
|
||||
|
||||
#if defined(NV_MODS)
|
||||
#define NV_IS_MODS 1
|
||||
#else
|
||||
#define NV_IS_MODS 0
|
||||
#endif
|
||||
|
||||
#if defined(NV_WINDOWS)
|
||||
#define NVOS_IS_WINDOWS 1
|
||||
#else
|
||||
#define NVOS_IS_WINDOWS 0
|
||||
#endif
|
||||
#if defined(NV_WINDOWS_CE)
|
||||
#define NVOS_IS_WINDOWS_CE 1
|
||||
#else
|
||||
#define NVOS_IS_WINDOWS_CE 0
|
||||
#endif
|
||||
#if defined(NV_LINUX)
|
||||
#define NVOS_IS_LINUX 1
|
||||
#else
|
||||
#define NVOS_IS_LINUX 0
|
||||
#endif
|
||||
#if defined(NV_UNIX)
|
||||
#define NVOS_IS_UNIX 1
|
||||
#else
|
||||
#define NVOS_IS_UNIX 0
|
||||
#endif
|
||||
#if defined(NV_BSD)
|
||||
#define NVOS_IS_FREEBSD 1
|
||||
#else
|
||||
#define NVOS_IS_FREEBSD 0
|
||||
#endif
|
||||
#if defined(NV_SUNOS)
|
||||
#define NVOS_IS_SOLARIS 1
|
||||
#else
|
||||
#define NVOS_IS_SOLARIS 0
|
||||
#endif
|
||||
#if defined(NV_VMWARE)
|
||||
#define NVOS_IS_VMWARE 1
|
||||
#else
|
||||
#define NVOS_IS_VMWARE 0
|
||||
#endif
|
||||
#if defined(NV_QNX)
|
||||
#define NVOS_IS_QNX 1
|
||||
#else
|
||||
#define NVOS_IS_QNX 0
|
||||
#endif
|
||||
#if defined(NV_ANDROID)
|
||||
#define NVOS_IS_ANDROID 1
|
||||
#else
|
||||
#define NVOS_IS_ANDROID 0
|
||||
#endif
|
||||
#if defined(NV_MACINTOSH)
|
||||
#define NVOS_IS_MACINTOSH 1
|
||||
#else
|
||||
#define NVOS_IS_MACINTOSH 0
|
||||
#endif
|
||||
#if defined(NV_VXWORKS)
|
||||
#define NVOS_IS_VXWORKS 1
|
||||
#else
|
||||
#define NVOS_IS_VXWORKS 0
|
||||
#endif
|
||||
#if defined(NV_LIBOS)
|
||||
#define NVOS_IS_LIBOS 1
|
||||
#else
|
||||
#define NVOS_IS_LIBOS 0
|
||||
#endif
|
||||
#if defined(NV_INTEGRITY)
|
||||
#define NVOS_IS_INTEGRITY 1
|
||||
#else
|
||||
#define NVOS_IS_INTEGRITY 0
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(NVCPU_X86)
|
||||
#define NVCPU_IS_X86 1
|
||||
#else
|
||||
#define NVCPU_IS_X86 0
|
||||
#endif
|
||||
#if defined(NVCPU_RISCV64)
|
||||
#define NVCPU_IS_RISCV64 1
|
||||
#else
|
||||
#define NVCPU_IS_RISCV64 0
|
||||
#endif
|
||||
#if defined(NVCPU_NVRISCV64)
|
||||
#define NVCPU_IS_NVRISCV64 1
|
||||
#else
|
||||
#define NVCPU_IS_NVRISCV64 0
|
||||
#endif
|
||||
#if defined(NVCPU_IA64)
|
||||
#define NVCPU_IS_IA64 1
|
||||
#else
|
||||
#define NVCPU_IS_IA64 0
|
||||
#endif
|
||||
#if defined(NVCPU_X86_64)
|
||||
#define NVCPU_IS_X86_64 1
|
||||
#else
|
||||
#define NVCPU_IS_X86_64 0
|
||||
#endif
|
||||
#if defined(NVCPU_FAMILY_X86)
|
||||
#define NVCPU_IS_FAMILY_X86 1
|
||||
#else
|
||||
#define NVCPU_IS_FAMILY_X86 0
|
||||
#endif
|
||||
#if defined(NVCPU_PPC)
|
||||
#define NVCPU_IS_PPC 1
|
||||
#else
|
||||
#define NVCPU_IS_PPC 0
|
||||
#endif
|
||||
#if defined(NVCPU_PPC64LE)
|
||||
#define NVCPU_IS_PPC64LE 1
|
||||
#else
|
||||
#define NVCPU_IS_PPC64LE 0
|
||||
#endif
|
||||
#if defined(NVCPU_FAMILY_PPC)
|
||||
#define NVCPU_IS_FAMILY_PPC 1
|
||||
#else
|
||||
#define NVCPU_IS_FAMILY_PPC 0
|
||||
#endif
|
||||
#if defined(NVCPU_ARM)
|
||||
#define NVCPU_IS_ARM 1
|
||||
#else
|
||||
#define NVCPU_IS_ARM 0
|
||||
#endif
|
||||
#if defined(NVCPU_AARCH64)
|
||||
#define NVCPU_IS_AARCH64 1
|
||||
#else
|
||||
#define NVCPU_IS_AARCH64 0
|
||||
#endif
|
||||
#if defined(NVCPU_FAMILY_ARM)
|
||||
#define NVCPU_IS_FAMILY_ARM 1
|
||||
#else
|
||||
#define NVCPU_IS_FAMILY_ARM 0
|
||||
#endif
|
||||
#if defined(NVCPU_SH4)
|
||||
#define NVCPU_IS_SH4 1
|
||||
#else
|
||||
#define NVCPU_IS_SH4 0
|
||||
#endif
|
||||
#if defined(NVCPU_XTENSA)
|
||||
#define NVCPU_IS_XTENSA 1
|
||||
#else
|
||||
#define NVCPU_IS_XTENSA 0
|
||||
#endif
|
||||
#if defined(NV_BIG_ENDIAN)
|
||||
#define NVCPU_IS_BIG_ENDIAN 1
|
||||
#else
|
||||
#define NVCPU_IS_BIG_ENDIAN 0
|
||||
#endif
|
||||
#if defined(NV_64_BITS)
|
||||
#define NVCPU_IS_64_BITS 1
|
||||
#else
|
||||
#define NVCPU_IS_64_BITS 0
|
||||
#endif
|
||||
#if defined(NVCPU_FAMILY_ARM)
|
||||
#define NVCPU_IS_PCIE_CACHE_COHERENT 0
|
||||
#else
|
||||
#define NVCPU_IS_PCIE_CACHE_COHERENT 1
|
||||
#endif
|
||||
#if defined(NV_DCECORE)
|
||||
#define NVOS_IS_DCECORE 1
|
||||
#else
|
||||
#define NVOS_IS_DCECORE 0
|
||||
#endif
|
||||
/*****************************************************************************/
|
||||
|
||||
#endif /* CPUOPSYS_H */
|
||||
35
nvdisplay/kernel-open/common/inc/dce_rm_client_ipc.h
Normal file
35
nvdisplay/kernel-open/common/inc/dce_rm_client_ipc.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _OS_DCE_CLIENT_IPC_H_
|
||||
#define _OS_DCE_CLIENT_IPC_H_
|
||||
|
||||
// RM IPC Client Types
|
||||
|
||||
#define DCE_CLIENT_RM_IPC_TYPE_SYNC 0x0
|
||||
#define DCE_CLIENT_RM_IPC_TYPE_EVENT 0x1
|
||||
#define DCE_CLIENT_RM_IPC_TYPE_MAX 0x2
|
||||
|
||||
void dceclientHandleAsyncRpcCallback(NvU32 handle, NvU32 interfaceType,
|
||||
NvU32 msgLength, void *data,
|
||||
void *usrCtx);
|
||||
#endif
|
||||
94
nvdisplay/kernel-open/common/inc/nv-caps.h
Normal file
94
nvdisplay/kernel-open/common/inc/nv-caps.h
Normal file
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_CAPS_H_
|
||||
#define _NV_CAPS_H_
|
||||
|
||||
#include <nv-kernel-interface-api.h>
|
||||
|
||||
/*
|
||||
* Opaque OS-specific struct; on Linux, this has member
|
||||
* 'struct proc_dir_entry'.
|
||||
*/
|
||||
typedef struct nv_cap nv_cap_t;
|
||||
|
||||
/*
|
||||
* Creates directory named "capabilities" under the provided path.
|
||||
*
|
||||
* @param[in] path Absolute path
|
||||
*
|
||||
* Returns a valid nv_cap_t upon success. Otherwise, returns NULL.
|
||||
*/
|
||||
nv_cap_t* NV_API_CALL nv_cap_init(const char *path);
|
||||
|
||||
/*
|
||||
* Creates capability directory entry
|
||||
*
|
||||
* @param[in] parent_cap Parent capability directory
|
||||
* @param[in] name Capability directory's name
|
||||
* @param[in] mode Capability directory's access mode
|
||||
*
|
||||
* Returns a valid nv_cap_t upon success. Otherwise, returns NULL.
|
||||
*/
|
||||
nv_cap_t* NV_API_CALL nv_cap_create_dir_entry(nv_cap_t *parent_cap, const char *name, int mode);
|
||||
|
||||
/*
|
||||
* Creates capability file entry
|
||||
*
|
||||
* @param[in] parent_cap Parent capability directory
|
||||
* @param[in] name Capability file's name
|
||||
* @param[in] mode Capability file's access mode
|
||||
*
|
||||
* Returns a valid nv_cap_t upon success. Otherwise, returns NULL.
|
||||
*/
|
||||
nv_cap_t* NV_API_CALL nv_cap_create_file_entry(nv_cap_t *parent_cap, const char *name, int mode);
|
||||
|
||||
/*
|
||||
* Destroys capability entry
|
||||
*
|
||||
* @param[in] cap Capability entry
|
||||
*/
|
||||
void NV_API_CALL nv_cap_destroy_entry(nv_cap_t *cap);
|
||||
|
||||
/*
|
||||
* Validates and duplicates the provided file descriptor
|
||||
*
|
||||
* @param[in] cap Capability entry
|
||||
* @param[in] fd File descriptor to be validated
|
||||
*
|
||||
* Returns duplicate fd upon success. Otherwise, returns -1.
|
||||
*/
|
||||
int NV_API_CALL nv_cap_validate_and_dup_fd(const nv_cap_t *cap, int fd);
|
||||
|
||||
/*
|
||||
* Closes file descriptor
|
||||
*
|
||||
* This function should be used to close duplicate file descriptors
|
||||
* returned by nv_cap_validate_and_dup_fd.
|
||||
*
|
||||
* @param[in] fd File descriptor to be validated
|
||||
*
|
||||
*/
|
||||
void NV_API_CALL nv_cap_close_fd(int fd);
|
||||
|
||||
#endif /* _NV_CAPS_H_ */
|
||||
31
nvdisplay/kernel-open/common/inc/nv-dmabuf.h
Normal file
31
nvdisplay/kernel-open/common/inc/nv-dmabuf.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_DMABUF_H_
|
||||
#define _NV_DMABUF_H_
|
||||
|
||||
#include "nv-linux.h"
|
||||
|
||||
NV_STATUS nv_dma_buf_export(nv_state_t *, nv_ioctl_export_to_dma_buf_fd_t *);
|
||||
|
||||
#endif // _NV_DMABUF_H_
|
||||
44
nvdisplay/kernel-open/common/inc/nv-gpu-info.h
Normal file
44
nvdisplay/kernel-open/common/inc/nv-gpu-info.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_GPU_INFO_H_
|
||||
#define _NV_GPU_INFO_H_
|
||||
|
||||
typedef struct {
|
||||
NvU32 gpu_id;
|
||||
|
||||
struct {
|
||||
NvU32 domain;
|
||||
NvU8 bus, slot, function;
|
||||
} pci_info;
|
||||
|
||||
/*
|
||||
* opaque OS-specific pointer; on Linux, this is a pointer to the
|
||||
* 'struct device' for the GPU.
|
||||
*/
|
||||
void *os_device_ptr;
|
||||
} nv_gpu_info_t;
|
||||
|
||||
#define NV_MAX_GPUS 32
|
||||
|
||||
#endif /* _NV_GPU_INFO_H_ */
|
||||
96
nvdisplay/kernel-open/common/inc/nv-hash.h
Normal file
96
nvdisplay/kernel-open/common/inc/nv-hash.h
Normal file
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef __NV_HASH_H__
|
||||
#define __NV_HASH_H__
|
||||
|
||||
#include "conftest.h"
|
||||
#include "nv-list-helpers.h"
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/hash.h>
|
||||
|
||||
#if defined(NV_LINUX_STRINGHASH_H_PRESENT)
|
||||
#include <linux/stringhash.h> /* full_name_hash() */
|
||||
#else
|
||||
#include <linux/dcache.h>
|
||||
#endif
|
||||
|
||||
#if (NV_FULL_NAME_HASH_ARGUMENT_COUNT == 3)
|
||||
#define nv_string_hash(_str) full_name_hash(NULL, _str, strlen(_str))
|
||||
#else
|
||||
#define nv_string_hash(_str) full_name_hash(_str, strlen(_str))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* This naive hashtable was introduced by commit d9b482c8ba19 (v3.7, 2012-10-31).
|
||||
* To support older kernels import necessary functionality from
|
||||
* <linux/hashtable.h>.
|
||||
*/
|
||||
|
||||
#define NV_HASH_SIZE(name) (ARRAY_SIZE(name))
|
||||
#define NV_HASH_BITS(name) ilog2(NV_HASH_SIZE(name))
|
||||
|
||||
/* Use hash_32 when possible to allow for fast 32bit hashing in 64bit kernels. */
|
||||
#define NV_HASH_MIN(val, bits) \
|
||||
(sizeof(val) <= 4 ? hash_32(val, bits) : hash_long(val, bits))
|
||||
|
||||
#define NV_DECLARE_HASHTABLE(name, bits) \
|
||||
struct hlist_head name[1 << (bits)]
|
||||
|
||||
static inline void _nv_hash_init(struct hlist_head *ht, unsigned int sz)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < sz; i++)
|
||||
{
|
||||
INIT_HLIST_HEAD(&ht[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* nv_hash_init - initialize a hash table
|
||||
* @hashtable: hashtable to be initialized
|
||||
*/
|
||||
#define nv_hash_init(hashtable) _nv_hash_init(hashtable, NV_HASH_SIZE(hashtable))
|
||||
|
||||
/**
|
||||
* nv_hash_add - add an object to a hashtable
|
||||
* @hashtable: hashtable to add to
|
||||
* @node: the &struct hlist_node of the object to be added
|
||||
* @key: the key of the object to be added
|
||||
*/
|
||||
#define nv_hash_add(hashtable, node, key) \
|
||||
hlist_add_head(node, &hashtable[NV_HASH_MIN(key, NV_HASH_BITS(hashtable))])
|
||||
|
||||
/**
|
||||
* nv_hash_for_each_possible - iterate over all possible objects hashing to the
|
||||
* same bucket
|
||||
* @name: hashtable to iterate
|
||||
* @obj: the type * to use as a loop cursor for each entry
|
||||
* @member: the name of the hlist_node within the struct
|
||||
* @key: the key of the objects to iterate over
|
||||
*/
|
||||
#define nv_hash_for_each_possible(name, obj, member, key) \
|
||||
nv_hlist_for_each_entry(obj, &name[NV_HASH_MIN(key, NV_HASH_BITS(name))], member)
|
||||
|
||||
#endif // __NV_HASH_H__
|
||||
125
nvdisplay/kernel-open/common/inc/nv-hypervisor.h
Normal file
125
nvdisplay/kernel-open/common/inc/nv-hypervisor.h
Normal file
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_HYPERVISOR_H_
|
||||
#define _NV_HYPERVISOR_H_
|
||||
|
||||
#include <nv-kernel-interface-api.h>
|
||||
|
||||
// Enums for supported hypervisor types.
|
||||
// New hypervisor type should be added before OS_HYPERVISOR_CUSTOM_FORCED
|
||||
typedef enum _HYPERVISOR_TYPE
|
||||
{
|
||||
OS_HYPERVISOR_XEN = 0,
|
||||
OS_HYPERVISOR_VMWARE,
|
||||
OS_HYPERVISOR_HYPERV,
|
||||
OS_HYPERVISOR_KVM,
|
||||
OS_HYPERVISOR_PARALLELS,
|
||||
OS_HYPERVISOR_CUSTOM_FORCED,
|
||||
OS_HYPERVISOR_UNKNOWN
|
||||
} HYPERVISOR_TYPE;
|
||||
|
||||
#define CMD_VGPU_VFIO_WAKE_WAIT_QUEUE 0
|
||||
#define CMD_VGPU_VFIO_INJECT_INTERRUPT 1
|
||||
#define CMD_VGPU_VFIO_REGISTER_MDEV 2
|
||||
#define CMD_VGPU_VFIO_PRESENT 3
|
||||
|
||||
#define MAX_VF_COUNT_PER_GPU 64
|
||||
|
||||
typedef enum _VGPU_TYPE_INFO
|
||||
{
|
||||
VGPU_TYPE_NAME = 0,
|
||||
VGPU_TYPE_DESCRIPTION,
|
||||
VGPU_TYPE_INSTANCES,
|
||||
} VGPU_TYPE_INFO;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
void *vgpuVfioRef;
|
||||
void *waitQueue;
|
||||
void *nv;
|
||||
NvU32 *vgpuTypeIds;
|
||||
NvU32 numVgpuTypes;
|
||||
NvU32 domain;
|
||||
NvU8 bus;
|
||||
NvU8 slot;
|
||||
NvU8 function;
|
||||
NvBool is_virtfn;
|
||||
} vgpu_vfio_info;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 domain;
|
||||
NvU8 bus;
|
||||
NvU8 slot;
|
||||
NvU8 function;
|
||||
NvBool isNvidiaAttached;
|
||||
NvBool isMdevAttached;
|
||||
} vgpu_vf_pci_info;
|
||||
|
||||
typedef enum VGPU_CMD_PROCESS_VF_INFO_E
|
||||
{
|
||||
NV_VGPU_SAVE_VF_INFO = 0,
|
||||
NV_VGPU_REMOVE_VF_PCI_INFO = 1,
|
||||
NV_VGPU_REMOVE_VF_MDEV_INFO = 2,
|
||||
NV_VGPU_GET_VF_INFO = 3
|
||||
} VGPU_CMD_PROCESS_VF_INFO;
|
||||
|
||||
typedef enum VGPU_DEVICE_STATE_E
|
||||
{
|
||||
NV_VGPU_DEV_UNUSED = 0,
|
||||
NV_VGPU_DEV_OPENED = 1,
|
||||
NV_VGPU_DEV_IN_USE = 2
|
||||
} VGPU_DEVICE_STATE;
|
||||
|
||||
typedef enum _VMBUS_CMD_TYPE
|
||||
{
|
||||
VMBUS_CMD_TYPE_INVALID = 0,
|
||||
VMBUS_CMD_TYPE_SETUP = 1,
|
||||
VMBUS_CMD_TYPE_SENDPACKET = 2,
|
||||
VMBUS_CMD_TYPE_CLEANUP = 3,
|
||||
} VMBUS_CMD_TYPE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 request_id;
|
||||
NvU32 page_count;
|
||||
NvU64 *pPfns;
|
||||
void *buffer;
|
||||
NvU32 bufferlen;
|
||||
} vmbus_send_packet_cmd_params;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 override_sint;
|
||||
NvU8 *nv_guid;
|
||||
} vmbus_setup_cmd_params;
|
||||
|
||||
/*
|
||||
* Function prototypes
|
||||
*/
|
||||
|
||||
HYPERVISOR_TYPE NV_API_CALL nv_get_hypervisor_type(void);
|
||||
|
||||
#endif // _NV_HYPERVISOR_H_
|
||||
84
nvdisplay/kernel-open/common/inc/nv-ioctl-numa.h
Normal file
84
nvdisplay/kernel-open/common/inc/nv-ioctl-numa.h
Normal file
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NV_IOCTL_NUMA_H
|
||||
#define NV_IOCTL_NUMA_H
|
||||
|
||||
#if defined(NV_LINUX)
|
||||
|
||||
#include <nv-ioctl-numbers.h>
|
||||
|
||||
#if defined(NV_KERNEL_INTERFACE_LAYER)
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#else
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#if !defined(__aligned)
|
||||
#define __aligned(n) __attribute__((aligned(n)))
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#define NV_ESC_NUMA_INFO (NV_IOCTL_BASE + 15)
|
||||
#define NV_ESC_SET_NUMA_STATUS (NV_IOCTL_BASE + 16)
|
||||
|
||||
#define NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES 64
|
||||
typedef struct offline_addresses
|
||||
{
|
||||
uint64_t addresses[NV_IOCTL_NUMA_INFO_MAX_OFFLINE_ADDRESSES] __aligned(8);
|
||||
uint32_t numEntries;
|
||||
} nv_offline_addresses_t;
|
||||
|
||||
|
||||
/* per-device NUMA memory info as assigned by the system */
|
||||
typedef struct nv_ioctl_numa_info
|
||||
{
|
||||
int32_t nid;
|
||||
int32_t status;
|
||||
uint64_t memblock_size __aligned(8);
|
||||
uint64_t numa_mem_addr __aligned(8);
|
||||
uint64_t numa_mem_size __aligned(8);
|
||||
nv_offline_addresses_t offline_addresses __aligned(8);
|
||||
} nv_ioctl_numa_info_t;
|
||||
|
||||
/* set the status of the device NUMA memory */
|
||||
typedef struct nv_ioctl_set_numa_status
|
||||
{
|
||||
int32_t status;
|
||||
} nv_ioctl_set_numa_status_t;
|
||||
|
||||
#define NV_IOCTL_NUMA_STATUS_DISABLED 0
|
||||
#define NV_IOCTL_NUMA_STATUS_OFFLINE 1
|
||||
#define NV_IOCTL_NUMA_STATUS_ONLINE_IN_PROGRESS 2
|
||||
#define NV_IOCTL_NUMA_STATUS_ONLINE 3
|
||||
#define NV_IOCTL_NUMA_STATUS_ONLINE_FAILED 4
|
||||
#define NV_IOCTL_NUMA_STATUS_OFFLINE_IN_PROGRESS 5
|
||||
#define NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED 6
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
43
nvdisplay/kernel-open/common/inc/nv-ioctl-numbers.h
Normal file
43
nvdisplay/kernel-open/common/inc/nv-ioctl-numbers.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NV_IOCTL_NUMBERS_H
|
||||
#define NV_IOCTL_NUMBERS_H
|
||||
|
||||
/* NOTE: using an ioctl() number > 55 will overflow! */
|
||||
#define NV_IOCTL_MAGIC 'F'
|
||||
#define NV_IOCTL_BASE 200
|
||||
#define NV_ESC_CARD_INFO (NV_IOCTL_BASE + 0)
|
||||
#define NV_ESC_REGISTER_FD (NV_IOCTL_BASE + 1)
|
||||
#define NV_ESC_ALLOC_OS_EVENT (NV_IOCTL_BASE + 6)
|
||||
#define NV_ESC_FREE_OS_EVENT (NV_IOCTL_BASE + 7)
|
||||
#define NV_ESC_STATUS_CODE (NV_IOCTL_BASE + 9)
|
||||
#define NV_ESC_CHECK_VERSION_STR (NV_IOCTL_BASE + 10)
|
||||
#define NV_ESC_IOCTL_XFER_CMD (NV_IOCTL_BASE + 11)
|
||||
#define NV_ESC_ATTACH_GPUS_TO_FD (NV_IOCTL_BASE + 12)
|
||||
#define NV_ESC_QUERY_DEVICE_INTR (NV_IOCTL_BASE + 13)
|
||||
#define NV_ESC_SYS_PARAMS (NV_IOCTL_BASE + 14)
|
||||
#define NV_ESC_EXPORT_TO_DMABUF_FD (NV_IOCTL_BASE + 17)
|
||||
|
||||
#endif
|
||||
145
nvdisplay/kernel-open/common/inc/nv-ioctl.h
Normal file
145
nvdisplay/kernel-open/common/inc/nv-ioctl.h
Normal file
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef NV_IOCTL_H
|
||||
#define NV_IOCTL_H
|
||||
|
||||
#include <nv-ioctl-numbers.h>
|
||||
#include <nvtypes.h>
|
||||
|
||||
typedef struct {
|
||||
NvU32 domain; /* PCI domain number */
|
||||
NvU8 bus; /* PCI bus number */
|
||||
NvU8 slot; /* PCI slot number */
|
||||
NvU8 function; /* PCI function number */
|
||||
NvU16 vendor_id; /* PCI vendor ID */
|
||||
NvU16 device_id; /* PCI device ID */
|
||||
} nv_pci_info_t;
|
||||
|
||||
/*
|
||||
* ioctl()'s with parameter structures too large for the
|
||||
* _IOC cmd layout use the nv_ioctl_xfer_t structure
|
||||
* and the NV_ESC_IOCTL_XFER_CMD ioctl() to pass the actual
|
||||
* size and user argument pointer into the RM, which
|
||||
* will then copy it to/from kernel space in separate steps.
|
||||
*/
|
||||
typedef struct nv_ioctl_xfer
|
||||
{
|
||||
NvU32 cmd;
|
||||
NvU32 size;
|
||||
NvP64 ptr NV_ALIGN_BYTES(8);
|
||||
} nv_ioctl_xfer_t;
|
||||
|
||||
typedef struct nv_ioctl_card_info
|
||||
{
|
||||
NvBool valid;
|
||||
nv_pci_info_t pci_info; /* PCI config information */
|
||||
NvU32 gpu_id;
|
||||
NvU16 interrupt_line;
|
||||
NvU64 reg_address NV_ALIGN_BYTES(8);
|
||||
NvU64 reg_size NV_ALIGN_BYTES(8);
|
||||
NvU64 fb_address NV_ALIGN_BYTES(8);
|
||||
NvU64 fb_size NV_ALIGN_BYTES(8);
|
||||
NvU32 minor_number;
|
||||
NvU8 dev_name[10]; /* device names such as vmgfx[0-32] for vmkernel */
|
||||
} nv_ioctl_card_info_t;
|
||||
|
||||
/* alloc event */
|
||||
typedef struct nv_ioctl_alloc_os_event
|
||||
{
|
||||
NvHandle hClient;
|
||||
NvHandle hDevice;
|
||||
NvU32 fd;
|
||||
NvU32 Status;
|
||||
} nv_ioctl_alloc_os_event_t;
|
||||
|
||||
/* free event */
|
||||
typedef struct nv_ioctl_free_os_event
|
||||
{
|
||||
NvHandle hClient;
|
||||
NvHandle hDevice;
|
||||
NvU32 fd;
|
||||
NvU32 Status;
|
||||
} nv_ioctl_free_os_event_t;
|
||||
|
||||
/* status code */
|
||||
typedef struct nv_ioctl_status_code
|
||||
{
|
||||
NvU32 domain;
|
||||
NvU8 bus;
|
||||
NvU8 slot;
|
||||
NvU32 status;
|
||||
} nv_ioctl_status_code_t;
|
||||
|
||||
/* check version string */
|
||||
#define NV_RM_API_VERSION_STRING_LENGTH 64
|
||||
|
||||
typedef struct nv_ioctl_rm_api_version
|
||||
{
|
||||
NvU32 cmd;
|
||||
NvU32 reply;
|
||||
char versionString[NV_RM_API_VERSION_STRING_LENGTH];
|
||||
} nv_ioctl_rm_api_version_t;
|
||||
|
||||
#define NV_RM_API_VERSION_CMD_STRICT 0
|
||||
#define NV_RM_API_VERSION_CMD_RELAXED '1'
|
||||
#define NV_RM_API_VERSION_CMD_OVERRIDE '2'
|
||||
|
||||
#define NV_RM_API_VERSION_REPLY_UNRECOGNIZED 0
|
||||
#define NV_RM_API_VERSION_REPLY_RECOGNIZED 1
|
||||
|
||||
typedef struct nv_ioctl_query_device_intr
|
||||
{
|
||||
NvU32 intrStatus NV_ALIGN_BYTES(4);
|
||||
NvU32 status;
|
||||
} nv_ioctl_query_device_intr;
|
||||
|
||||
/* system parameters that the kernel driver may use for configuration */
|
||||
typedef struct nv_ioctl_sys_params
|
||||
{
|
||||
NvU64 memblock_size NV_ALIGN_BYTES(8);
|
||||
} nv_ioctl_sys_params_t;
|
||||
|
||||
typedef struct nv_ioctl_register_fd
|
||||
{
|
||||
int ctl_fd;
|
||||
} nv_ioctl_register_fd_t;
|
||||
|
||||
#define NV_DMABUF_EXPORT_MAX_HANDLES 128
|
||||
|
||||
typedef struct nv_ioctl_export_to_dma_buf_fd
|
||||
{
|
||||
int fd;
|
||||
NvHandle hClient;
|
||||
NvU32 totalObjects;
|
||||
NvU32 numObjects;
|
||||
NvU32 index;
|
||||
NvU64 totalSize NV_ALIGN_BYTES(8);
|
||||
NvHandle handles[NV_DMABUF_EXPORT_MAX_HANDLES];
|
||||
NvU64 offsets[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
|
||||
NvU64 sizes[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
|
||||
NvU32 status;
|
||||
} nv_ioctl_export_to_dma_buf_fd_t;
|
||||
|
||||
#endif
|
||||
41
nvdisplay/kernel-open/common/inc/nv-kernel-interface-api.h
Normal file
41
nvdisplay/kernel-open/common/inc/nv-kernel-interface-api.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018-2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_KERNEL_INTERFACE_API_H
|
||||
#define _NV_KERNEL_INTERFACE_API_H
|
||||
/**************************************************************************************************************
|
||||
*
|
||||
* File: nv-kernel-interface-api.h
|
||||
*
|
||||
* Description:
|
||||
* Defines the NV API related macros.
|
||||
*
|
||||
**************************************************************************************************************/
|
||||
|
||||
#if NVOS_IS_UNIX && NVCPU_IS_X86_64 && defined(__use_altstack__)
|
||||
#define NV_API_CALL __attribute__((altstack(0)))
|
||||
#else
|
||||
#define NV_API_CALL
|
||||
#endif
|
||||
|
||||
#endif /* _NV_KERNEL_INTERFACE_API_H */
|
||||
61
nvdisplay/kernel-open/common/inc/nv-kref.h
Normal file
61
nvdisplay/kernel-open/common/inc/nv-kref.h
Normal file
@@ -0,0 +1,61 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NV_KREF_H__
|
||||
#define __NV_KREF_H__
|
||||
|
||||
#include <asm/atomic.h>
|
||||
|
||||
typedef struct nv_kref
|
||||
{
|
||||
atomic_t refcount;
|
||||
} nv_kref_t;
|
||||
|
||||
static inline void nv_kref_init(nv_kref_t *nv_kref)
|
||||
{
|
||||
atomic_set(&nv_kref->refcount, 1);
|
||||
}
|
||||
|
||||
static inline void nv_kref_get(nv_kref_t *nv_kref)
|
||||
{
|
||||
atomic_inc(&nv_kref->refcount);
|
||||
}
|
||||
|
||||
static inline int nv_kref_put(nv_kref_t *nv_kref,
|
||||
void (*release)(nv_kref_t *nv_kref))
|
||||
{
|
||||
if (atomic_dec_and_test(&nv_kref->refcount))
|
||||
{
|
||||
release(nv_kref);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline unsigned int nv_kref_read(const nv_kref_t *nv_kref)
|
||||
{
|
||||
return atomic_read(&nv_kref->refcount);
|
||||
}
|
||||
|
||||
#endif // __NV_KREF_H__
|
||||
255
nvdisplay/kernel-open/common/inc/nv-kthread-q.h
Normal file
255
nvdisplay/kernel-open/common/inc/nv-kthread-q.h
Normal file
@@ -0,0 +1,255 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NV_KTHREAD_QUEUE_H__
|
||||
#define __NV_KTHREAD_QUEUE_H__
|
||||
|
||||
#include <linux/types.h> // atomic_t
|
||||
#include <linux/list.h> // list
|
||||
#include <linux/sched.h> // task_struct
|
||||
#include <linux/numa.h> // NUMA_NO_NODE
|
||||
|
||||
#include "conftest.h"
|
||||
|
||||
#if defined(NV_LINUX_SEMAPHORE_H_PRESENT)
|
||||
#include <linux/semaphore.h>
|
||||
#else
|
||||
#include <asm/semaphore.h>
|
||||
#endif
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// nv_kthread_q:
|
||||
//
|
||||
// 1. API and overview
|
||||
//
|
||||
// This "nv_kthread_q" system implements a simple queuing system for deferred
|
||||
// work. The nv_kthread_q system has goals and use cases that are similar to
|
||||
// the named workqueues in the Linux kernel, but nv_kthread_q is much (10x or
|
||||
// so) smaller, simpler--and correspondingly less general. Deferred work
|
||||
// items are put into a queue, and run within the context of a dedicated set
|
||||
// of kernel threads (kthread).
|
||||
//
|
||||
// In order to avoid confusion with the Linux workqueue system, I have
|
||||
// avoided using the term "work", and instead refer to "queues" (also called
|
||||
// "q's") and "queue items" (also called "q_items"), in both variable names
|
||||
// and comments.
|
||||
//
|
||||
// This module depends only upon the Linux kernel.
|
||||
//
|
||||
// Queue items that are submitted to separate nv_kthread_q instances are
|
||||
// guaranteed to be run in different kthreads.
|
||||
//
|
||||
// Queue items that are submitted to the same nv_kthread_q are not guaranteed
|
||||
// to be serialized, nor are they guaranteed to run concurrently.
|
||||
//
|
||||
// 2. Allocations
|
||||
//
|
||||
// The caller allocates queues and queue items. The nv_kthread_q APIs do
|
||||
// the initialization (zeroing and setup) of queues and queue items.
|
||||
// Allocation is handled that way, because one of the first use cases is a
|
||||
// bottom half interrupt handler, and for that, queue items should be
|
||||
// pre-allocated (for example, one per GPU), so that no allocation is
|
||||
// required in the top-half interrupt handler. Relevant API calls:
|
||||
//
|
||||
// 3. Queue initialization
|
||||
//
|
||||
// nv_kthread_q_init() initializes a queue on the current NUMA node.
|
||||
//
|
||||
// or
|
||||
//
|
||||
// nv_kthread_q_init_on_node() initializes a queue on a specific NUMA node.
|
||||
//
|
||||
// 3. Scheduling things for the queue to run
|
||||
//
|
||||
// The nv_kthread_q_schedule_q_item() routine will schedule a q_item to run.
|
||||
//
|
||||
// 4. Stopping the queue(s)
|
||||
//
|
||||
// The nv_kthread_q_stop() routine will flush the queue, and safely stop
|
||||
// the kthread, before returning.
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct nv_kthread_q nv_kthread_q_t;
|
||||
typedef struct nv_kthread_q_item nv_kthread_q_item_t;
|
||||
|
||||
typedef void (*nv_q_func_t)(void *args);
|
||||
|
||||
struct nv_kthread_q
|
||||
{
|
||||
struct list_head q_list_head;
|
||||
spinlock_t q_lock;
|
||||
|
||||
// This is a counting semaphore. It gets incremented and decremented
|
||||
// exactly once for each item that is added to the queue.
|
||||
struct semaphore q_sem;
|
||||
atomic_t main_loop_should_exit;
|
||||
|
||||
struct task_struct *q_kthread;
|
||||
};
|
||||
|
||||
struct nv_kthread_q_item
|
||||
{
|
||||
struct list_head q_list_node;
|
||||
nv_q_func_t function_to_run;
|
||||
void *function_args;
|
||||
};
|
||||
|
||||
#if defined(NV_KTHREAD_CREATE_ON_NODE_PRESENT)
|
||||
#define NV_KTHREAD_Q_SUPPORTS_AFFINITY() 1
|
||||
#else
|
||||
#define NV_KTHREAD_Q_SUPPORTS_AFFINITY() 0
|
||||
#endif
|
||||
|
||||
#ifndef NUMA_NO_NODE
|
||||
#define NUMA_NO_NODE (-1)
|
||||
#endif
|
||||
|
||||
#define NV_KTHREAD_NO_NODE NUMA_NO_NODE
|
||||
|
||||
//
|
||||
// The queue must not be used before calling this routine.
|
||||
//
|
||||
// The caller allocates an nv_kthread_q_t item. This routine initializes
|
||||
// the queue, and starts up a kernel thread ("kthread") to service the queue.
|
||||
// The queue will initially be empty; there is intentionally no way to
|
||||
// pre-initialize the queue with items to run.
|
||||
//
|
||||
// In order to avoid external dependencies (specifically, NV_STATUS codes), this
|
||||
// returns a Linux kernel (negative) errno on failure, and zero on success. It
|
||||
// is safe to call nv_kthread_q_stop() on a queue that nv_kthread_q_init()
|
||||
// failed for.
|
||||
//
|
||||
// A short prefix of the qname arg will show up in []'s, via the ps(1) utility.
|
||||
//
|
||||
// The kernel thread stack is preferably allocated on the specified NUMA node if
|
||||
// NUMA-affinity (NV_KTHREAD_Q_SUPPORTS_AFFINITY() == 1) is supported, but
|
||||
// fallback to another node is possible because kernel allocators do not
|
||||
// guarantee affinity. Note that NUMA-affinity applies only to
|
||||
// the kthread stack. This API does not do anything about limiting the CPU
|
||||
// affinity of the kthread. That is left to the caller.
|
||||
//
|
||||
// On kernels, which do not support NUMA-aware kthread stack allocations
|
||||
// (NV_KTHTREAD_Q_SUPPORTS_AFFINITY() == 0), the API will return -ENOTSUPP
|
||||
// if the value supplied for 'preferred_node' is anything other than
|
||||
// NV_KTHREAD_NO_NODE.
|
||||
//
|
||||
// Reusing a queue: once a queue is initialized, it must be safely shut down
|
||||
// (see "Stopping the queue(s)", below), before it can be reused. So, for
|
||||
// a simple queue use case, the following will work:
|
||||
//
|
||||
// nv_kthread_q_init_on_node(&some_q, "display_name", preferred_node);
|
||||
// nv_kthread_q_stop(&some_q);
|
||||
// nv_kthread_q_init_on_node(&some_q, "reincarnated", preferred_node);
|
||||
// nv_kthread_q_stop(&some_q);
|
||||
//
|
||||
int nv_kthread_q_init_on_node(nv_kthread_q_t *q,
|
||||
const char *qname,
|
||||
int preferred_node);
|
||||
|
||||
//
|
||||
// This routine is the same as nv_kthread_q_init_on_node() with the exception
|
||||
// that the queue stack will be allocated on the NUMA node of the caller.
|
||||
//
|
||||
static inline int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname)
|
||||
{
|
||||
return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE);
|
||||
}
|
||||
|
||||
//
|
||||
// The caller is responsible for stopping all queues, by calling this routine
|
||||
// before, for example, kernel module unloading. This nv_kthread_q_stop()
|
||||
// routine will flush the queue, and safely stop the kthread, before returning.
|
||||
//
|
||||
// You may ONLY call nv_kthread_q_stop() once, unless you reinitialize the
|
||||
// queue in between, as shown in the nv_kthread_q_init() documentation, above.
|
||||
//
|
||||
// Do not add any more items to the queue after calling nv_kthread_q_stop.
|
||||
//
|
||||
// Calling nv_kthread_q_stop() on a queue which has been zero-initialized or
|
||||
// for which nv_kthread_q_init() failed, is a no-op.
|
||||
//
|
||||
void nv_kthread_q_stop(nv_kthread_q_t *q);
|
||||
|
||||
//
|
||||
// All items that were in the queue before nv_kthread_q_flush was called, and
|
||||
// all items scheduled by those items, will get run before this function
|
||||
// returns.
|
||||
//
|
||||
// You may NOT call nv_kthread_q_flush() after having called nv_kthread_q_stop.
|
||||
//
|
||||
// This actually flushes the queue twice. That ensures that the queue is fully
|
||||
// flushed, for an important use case: rescheduling from within one's own
|
||||
// callback. In order to do that safely, you need to:
|
||||
//
|
||||
// -- set a flag that tells the callback to stop rescheduling itself.
|
||||
//
|
||||
// -- call either nv_kthread_q_flush or nv_kthread_q_stop (which internally
|
||||
// calls nv_kthread_q_flush). The nv_kthread_q_flush, in turn, actually
|
||||
// flushes the queue *twice*. The first flush waits for any callbacks
|
||||
// to finish, that missed seeing the "stop_rescheduling" flag. The
|
||||
// second flush waits for callbacks that were already scheduled when the
|
||||
// first flush finished.
|
||||
//
|
||||
void nv_kthread_q_flush(nv_kthread_q_t *q);
|
||||
|
||||
// Assigns function_to_run and function_args to the q_item.
|
||||
//
|
||||
// This must be called before calling nv_kthread_q_schedule_q_item.
|
||||
void nv_kthread_q_item_init(nv_kthread_q_item_t *q_item,
|
||||
nv_q_func_t function_to_run,
|
||||
void *function_args);
|
||||
|
||||
//
|
||||
// The caller must have already set up the queue, via nv_kthread_q_init().
|
||||
// The caller owns the lifetime of the q_item. The nv_kthread_q system runs
|
||||
// q_items, and adds or removes them from the queue. However, due to the first
|
||||
// law of q-dynamics, it neither creates nor destroys q_items.
|
||||
//
|
||||
// When the callback (the function_to_run argument) is actually run, it is OK
|
||||
// to free the q_item from within that routine. The nv_kthread_q system
|
||||
// promises to be done with the q_item before that point.
|
||||
//
|
||||
// nv_kthread_q_schedule_q_item may be called from multiple threads at once,
|
||||
// without danger of corrupting anything. This routine may also be safely
|
||||
// called from interrupt context, including top-half ISRs.
|
||||
//
|
||||
// It is OK to reschedule the same q_item from within its own callback function.
|
||||
//
|
||||
// It is also OK to attempt to reschedule the same q_item, if that q_item is
|
||||
// already pending in the queue. The q_item will not be rescheduled if it is
|
||||
// already pending.
|
||||
//
|
||||
// Returns true (non-zero) if the item was actually scheduled. Returns false if
|
||||
// the item was not scheduled, which can happen if:
|
||||
//
|
||||
// -- The q_item was already pending in a queue, or
|
||||
// -- The queue is shutting down (or not yet started up).
|
||||
//
|
||||
int nv_kthread_q_schedule_q_item(nv_kthread_q_t *q,
|
||||
nv_kthread_q_item_t *q_item);
|
||||
|
||||
// Built-in test. Returns -1 if any subtest failed, or 0 upon success.
|
||||
int nv_kthread_q_run_self_test(void);
|
||||
|
||||
#endif // __NV_KTHREAD_QUEUE_H__
|
||||
2058
nvdisplay/kernel-open/common/inc/nv-linux.h
Normal file
2058
nvdisplay/kernel-open/common/inc/nv-linux.h
Normal file
File diff suppressed because it is too large
Load Diff
93
nvdisplay/kernel-open/common/inc/nv-list-helpers.h
Normal file
93
nvdisplay/kernel-open/common/inc/nv-list-helpers.h
Normal file
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef __NV_LIST_HELPERS_H__
|
||||
#define __NV_LIST_HELPERS_H__
|
||||
|
||||
#include <linux/list.h>
|
||||
#include "conftest.h"
|
||||
|
||||
/*
|
||||
* list_first_entry_or_null added by commit 6d7581e62f8b ("list: introduce
|
||||
* list_first_entry_or_null") in v3.10 (2013-05-29).
|
||||
*/
|
||||
#if !defined(list_first_entry_or_null)
|
||||
#define list_first_entry_or_null(ptr, type, member) \
|
||||
(!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Added by commit 93be3c2eb337 ("list: introduce list_last_entry(), use
|
||||
* list_{first,last}_entry()") in v3.13 (2013-11-12).
|
||||
*/
|
||||
#if !defined(list_last_entry)
|
||||
#define list_last_entry(ptr, type, member) \
|
||||
list_entry((ptr)->prev, type, member)
|
||||
#endif
|
||||
|
||||
/* list_last_entry_or_null() doesn't actually exist in the kernel */
|
||||
#if !defined(list_last_entry_or_null)
|
||||
#define list_last_entry_or_null(ptr, type, member) \
|
||||
(!list_empty(ptr) ? list_last_entry(ptr, type, member) : NULL)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* list_prev_entry() and list_next_entry added by commit 008208c6b26f
|
||||
* ("list: introduce list_next_entry() and list_prev_entry()") in
|
||||
* v3.13 (2013-11-12).
|
||||
*/
|
||||
#if !defined(list_prev_entry)
|
||||
#define list_prev_entry(pos, member) \
|
||||
list_entry((pos)->member.prev, typeof(*(pos)), member)
|
||||
#endif
|
||||
|
||||
#if !defined(list_next_entry)
|
||||
#define list_next_entry(pos, member) \
|
||||
list_entry((pos)->member.next, typeof(*(pos)), member)
|
||||
#endif
|
||||
|
||||
#if !defined(NV_LIST_IS_FIRST_PRESENT)
|
||||
static inline int list_is_first(const struct list_head *list,
|
||||
const struct list_head *head)
|
||||
{
|
||||
return list->prev == head;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT)
|
||||
#if NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT == 3
|
||||
#define nv_hlist_for_each_entry(pos, head, member) \
|
||||
hlist_for_each_entry(pos, head, member)
|
||||
#else
|
||||
#if !defined(hlist_entry_safe)
|
||||
#define hlist_entry_safe(ptr, type, member) \
|
||||
(ptr) ? hlist_entry(ptr, type, member) : NULL
|
||||
#endif
|
||||
|
||||
#define nv_hlist_for_each_entry(pos, head, member) \
|
||||
for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); \
|
||||
pos; \
|
||||
pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
|
||||
#endif
|
||||
#endif // NV_HLIST_FOR_EACH_ENTRY_ARGUMENT_COUNT
|
||||
|
||||
#endif // __NV_LIST_HELPERS_H__
|
||||
92
nvdisplay/kernel-open/common/inc/nv-lock.h
Normal file
92
nvdisplay/kernel-open/common/inc/nv-lock.h
Normal file
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_LOCK_H_
|
||||
#define _NV_LOCK_H_
|
||||
|
||||
#include "conftest.h"
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/sched.h> /* signal_pending, cond_resched */
|
||||
|
||||
#if defined(NV_LINUX_SCHED_SIGNAL_H_PRESENT)
|
||||
#include <linux/sched/signal.h> /* signal_pending for kernels >= 4.11 */
|
||||
#endif
|
||||
|
||||
#if defined(NV_LINUX_SEMAPHORE_H_PRESENT)
|
||||
#include <linux/semaphore.h>
|
||||
#else
|
||||
#include <asm/semaphore.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL)
|
||||
typedef raw_spinlock_t nv_spinlock_t;
|
||||
#define NV_SPIN_LOCK_INIT(lock) raw_spin_lock_init(lock)
|
||||
#define NV_SPIN_LOCK_IRQ(lock) raw_spin_lock_irq(lock)
|
||||
#define NV_SPIN_UNLOCK_IRQ(lock) raw_spin_unlock_irq(lock)
|
||||
#define NV_SPIN_LOCK_IRQSAVE(lock,flags) raw_spin_lock_irqsave(lock,flags)
|
||||
#define NV_SPIN_UNLOCK_IRQRESTORE(lock,flags) raw_spin_unlock_irqrestore(lock,flags)
|
||||
#define NV_SPIN_LOCK(lock) raw_spin_lock(lock)
|
||||
#define NV_SPIN_UNLOCK(lock) raw_spin_unlock(lock)
|
||||
#define NV_SPIN_UNLOCK_WAIT(lock) raw_spin_unlock_wait(lock)
|
||||
#else
|
||||
typedef spinlock_t nv_spinlock_t;
|
||||
#define NV_SPIN_LOCK_INIT(lock) spin_lock_init(lock)
|
||||
#define NV_SPIN_LOCK_IRQ(lock) spin_lock_irq(lock)
|
||||
#define NV_SPIN_UNLOCK_IRQ(lock) spin_unlock_irq(lock)
|
||||
#define NV_SPIN_LOCK_IRQSAVE(lock,flags) spin_lock_irqsave(lock,flags)
|
||||
#define NV_SPIN_UNLOCK_IRQRESTORE(lock,flags) spin_unlock_irqrestore(lock,flags)
|
||||
#define NV_SPIN_LOCK(lock) spin_lock(lock)
|
||||
#define NV_SPIN_UNLOCK(lock) spin_unlock(lock)
|
||||
#define NV_SPIN_UNLOCK_WAIT(lock) spin_unlock_wait(lock)
|
||||
#endif
|
||||
|
||||
#if defined(NV_CONFIG_PREEMPT_RT)
|
||||
#define NV_INIT_SEMA(sema, val) sema_init(sema,val)
|
||||
#else
|
||||
#if !defined(__SEMAPHORE_INITIALIZER) && defined(__COMPAT_SEMAPHORE_INITIALIZER)
|
||||
#define __SEMAPHORE_INITIALIZER __COMPAT_SEMAPHORE_INITIALIZER
|
||||
#endif
|
||||
#define NV_INIT_SEMA(sema, val) \
|
||||
{ \
|
||||
struct semaphore __sema = \
|
||||
__SEMAPHORE_INITIALIZER(*(sema), val); \
|
||||
*(sema) = __sema; \
|
||||
}
|
||||
#endif
|
||||
#define NV_INIT_MUTEX(mutex) NV_INIT_SEMA(mutex, 1)
|
||||
|
||||
static inline int nv_down_read_interruptible(struct rw_semaphore *lock)
|
||||
{
|
||||
while (!down_read_trylock(lock))
|
||||
{
|
||||
if (signal_pending(current))
|
||||
return -EINTR;
|
||||
cond_resched();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#endif /* _NV_LOCK_H_ */
|
||||
49
nvdisplay/kernel-open/common/inc/nv-memdbg.h
Normal file
49
nvdisplay/kernel-open/common/inc/nv-memdbg.h
Normal file
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NVMEMDBG_H_
|
||||
#define _NVMEMDBG_H_
|
||||
|
||||
#include <nvtypes.h>
|
||||
|
||||
void nv_memdbg_init(void);
|
||||
void nv_memdbg_add(void *addr, NvU64 size, const char *file, int line);
|
||||
void nv_memdbg_remove(void *addr, NvU64 size, const char *file, int line);
|
||||
void nv_memdbg_exit(void);
|
||||
|
||||
#if defined(NV_MEM_LOGGER)
|
||||
|
||||
#define NV_MEMDBG_ADD(ptr, size) \
|
||||
nv_memdbg_add(ptr, size, __FILE__, __LINE__)
|
||||
|
||||
#define NV_MEMDBG_REMOVE(ptr, size) \
|
||||
nv_memdbg_remove(ptr, size, __FILE__, __LINE__)
|
||||
|
||||
#else
|
||||
|
||||
#define NV_MEMDBG_ADD(ptr, size)
|
||||
#define NV_MEMDBG_REMOVE(ptr, size)
|
||||
|
||||
#endif /* NV_MEM_LOGGER */
|
||||
|
||||
#endif /* _NVMEMDBG_H_ */
|
||||
264
nvdisplay/kernel-open/common/inc/nv-mm.h
Normal file
264
nvdisplay/kernel-open/common/inc/nv-mm.h
Normal file
@@ -0,0 +1,264 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016-2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef __NV_MM_H__
|
||||
#define __NV_MM_H__
|
||||
|
||||
#include "conftest.h"
|
||||
|
||||
#if !defined(NV_VM_FAULT_T_IS_PRESENT)
|
||||
typedef int vm_fault_t;
|
||||
#endif
|
||||
|
||||
/* pin_user_pages
|
||||
* Presence of pin_user_pages() also implies the presence of unpin-user_page().
|
||||
* Both were added in the v5.6-rc1
|
||||
*
|
||||
* pin_user_pages() was added by commit eddb1c228f7951d399240
|
||||
* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6-rc1 (2020-01-30)
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
#if defined(NV_PIN_USER_PAGES_PRESENT)
|
||||
#define NV_PIN_USER_PAGES pin_user_pages
|
||||
#define NV_UNPIN_USER_PAGE unpin_user_page
|
||||
#else
|
||||
#define NV_PIN_USER_PAGES NV_GET_USER_PAGES
|
||||
#define NV_UNPIN_USER_PAGE put_page
|
||||
#endif // NV_PIN_USER_PAGES_PRESENT
|
||||
|
||||
/* get_user_pages
|
||||
*
|
||||
* The 8-argument version of get_user_pages was deprecated by commit
|
||||
* (2016 Feb 12: cde70140fed8429acf7a14e2e2cbd3e329036653)for the non-remote case
|
||||
* (calling get_user_pages with current and current->mm).
|
||||
*
|
||||
* Completely moved to the 6 argument version of get_user_pages -
|
||||
* 2016 Apr 4: c12d2da56d0e07d230968ee2305aaa86b93a6832
|
||||
*
|
||||
* write and force parameters were replaced with gup_flags by -
|
||||
* 2016 Oct 12: 768ae309a96103ed02eb1e111e838c87854d8b51
|
||||
*
|
||||
* A 7-argument version of get_user_pages was introduced into linux-4.4.y by
|
||||
* commit 8e50b8b07f462ab4b91bc1491b1c91bd75e4ad40 which cherry-picked the
|
||||
* replacement of the write and force parameters with gup_flags
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(NV_GET_USER_PAGES_HAS_ARGS_FLAGS)
|
||||
#define NV_GET_USER_PAGES get_user_pages
|
||||
#elif defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_FLAGS)
|
||||
#define NV_GET_USER_PAGES(start, nr_pages, flags, pages, vmas) \
|
||||
get_user_pages(current, current->mm, start, nr_pages, flags, pages, vmas)
|
||||
#else
|
||||
static inline long NV_GET_USER_PAGES(unsigned long start,
|
||||
unsigned long nr_pages,
|
||||
unsigned int flags,
|
||||
struct page **pages,
|
||||
struct vm_area_struct **vmas)
|
||||
{
|
||||
int write = flags & FOLL_WRITE;
|
||||
int force = flags & FOLL_FORCE;
|
||||
|
||||
#if defined(NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE)
|
||||
return get_user_pages(start, nr_pages, write, force, pages, vmas);
|
||||
#else
|
||||
// NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE
|
||||
return get_user_pages(current, current->mm, start, nr_pages, write,
|
||||
force, pages, vmas);
|
||||
#endif // NV_GET_USER_PAGES_HAS_ARGS_WRITE_FORCE
|
||||
}
|
||||
#endif // NV_GET_USER_PAGES_HAS_ARGS_FLAGS
|
||||
|
||||
/* pin_user_pages_remote
|
||||
*
|
||||
* pin_user_pages_remote() was added by commit eddb1c228f7951d399240
|
||||
* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6 (2020-01-30)
|
||||
*
|
||||
* pin_user_pages_remote() removed 'tsk' parameter by commit
|
||||
* 64019a2e467a ("mm/gup: remove task_struct pointer for all gup code")
|
||||
* in v5.9-rc1 (2020-08-11). *
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(NV_PIN_USER_PAGES_REMOTE_PRESENT)
|
||||
#if defined (NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK)
|
||||
#define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
|
||||
pin_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked)
|
||||
#else
|
||||
#define NV_PIN_USER_PAGES_REMOTE pin_user_pages_remote
|
||||
#endif // NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK
|
||||
#else
|
||||
#define NV_PIN_USER_PAGES_REMOTE NV_GET_USER_PAGES_REMOTE
|
||||
#endif // NV_PIN_USER_PAGES_REMOTE_PRESENT
|
||||
|
||||
/*
|
||||
* get_user_pages_remote() was added by commit 1e9877902dc7
|
||||
* ("mm/gup: Introduce get_user_pages_remote()") in v4.6 (2016-02-12).
|
||||
*
|
||||
* Note that get_user_pages_remote() requires the caller to hold a reference on
|
||||
* the task_struct (if non-NULL and if this API has tsk argument) and the mm_struct.
|
||||
* This will always be true when using current and current->mm. If the kernel passes
|
||||
* the driver a vma via driver callback, the kernel holds a reference on vma->vm_mm
|
||||
* over that callback.
|
||||
*
|
||||
* get_user_pages_remote() write/force parameters were replaced
|
||||
* with gup_flags by commit 9beae1ea8930 ("mm: replace get_user_pages_remote()
|
||||
* write/force parameters with gup_flags") in v4.9 (2016-10-13).
|
||||
*
|
||||
* get_user_pages_remote() added 'locked' parameter by commit 5b56d49fc31d
|
||||
* ("mm: add locked parameter to get_user_pages_remote()") in
|
||||
* v4.10 (2016-12-14).
|
||||
*
|
||||
* get_user_pages_remote() removed 'tsk' parameter by
|
||||
* commit 64019a2e467a ("mm/gup: remove task_struct pointer for
|
||||
* all gup code") in v5.9-rc1 (2020-08-11).
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(NV_GET_USER_PAGES_REMOTE_PRESENT)
|
||||
#if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED)
|
||||
#define NV_GET_USER_PAGES_REMOTE get_user_pages_remote
|
||||
|
||||
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS_LOCKED)
|
||||
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
|
||||
get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas, locked)
|
||||
|
||||
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_FLAGS)
|
||||
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
|
||||
get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, vmas)
|
||||
|
||||
#else
|
||||
// NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_WRITE_FORCE
|
||||
static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm,
|
||||
unsigned long start,
|
||||
unsigned long nr_pages,
|
||||
unsigned int flags,
|
||||
struct page **pages,
|
||||
struct vm_area_struct **vmas,
|
||||
int *locked)
|
||||
{
|
||||
int write = flags & FOLL_WRITE;
|
||||
int force = flags & FOLL_FORCE;
|
||||
|
||||
return get_user_pages_remote(NULL, mm, start, nr_pages, write, force,
|
||||
pages, vmas);
|
||||
}
|
||||
#endif // NV_GET_USER_PAGES_REMOTE_HAS_ARGS_FLAGS_LOCKED
|
||||
#else
|
||||
#if defined(NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE)
|
||||
static inline long NV_GET_USER_PAGES_REMOTE(struct mm_struct *mm,
|
||||
unsigned long start,
|
||||
unsigned long nr_pages,
|
||||
unsigned int flags,
|
||||
struct page **pages,
|
||||
struct vm_area_struct **vmas,
|
||||
int *locked)
|
||||
{
|
||||
int write = flags & FOLL_WRITE;
|
||||
int force = flags & FOLL_FORCE;
|
||||
|
||||
return get_user_pages(NULL, mm, start, nr_pages, write, force, pages, vmas);
|
||||
}
|
||||
|
||||
#else
|
||||
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, vmas, locked) \
|
||||
get_user_pages(NULL, mm, start, nr_pages, flags, pages, vmas)
|
||||
#endif // NV_GET_USER_PAGES_HAS_ARGS_TSK_WRITE_FORCE
|
||||
#endif // NV_GET_USER_PAGES_REMOTE_PRESENT
|
||||
|
||||
/*
|
||||
* The .virtual_address field was effectively renamed to .address, by these
|
||||
* two commits:
|
||||
*
|
||||
* struct vm_fault: .address was added by:
|
||||
* 2016-12-14 82b0f8c39a3869b6fd2a10e180a862248736ec6f
|
||||
*
|
||||
* struct vm_fault: .virtual_address was removed by:
|
||||
* 2016-12-14 1a29d85eb0f19b7d8271923d8917d7b4f5540b3e
|
||||
*/
|
||||
static inline unsigned long nv_page_fault_va(struct vm_fault *vmf)
|
||||
{
|
||||
#if defined(NV_VM_FAULT_HAS_ADDRESS)
|
||||
return vmf->address;
|
||||
#else
|
||||
return (unsigned long)(vmf->virtual_address);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_mmap_read_lock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_read_lock(mm);
|
||||
#else
|
||||
down_read(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_mmap_read_unlock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_read_unlock(mm);
|
||||
#else
|
||||
up_read(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_mmap_write_lock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_write_lock(mm);
|
||||
#else
|
||||
down_write(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_mmap_write_unlock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_write_unlock(mm);
|
||||
#else
|
||||
up_write(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline int nv_mm_rwsem_is_locked(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
return rwsem_is_locked(&mm->mmap_lock);
|
||||
#else
|
||||
return rwsem_is_locked(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline struct rw_semaphore *nv_mmap_get_lock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
return &mm->mmap_lock;
|
||||
#else
|
||||
return &mm->mmap_sem;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // __NV_MM_H__
|
||||
122
nvdisplay/kernel-open/common/inc/nv-modeset-interface.h
Normal file
122
nvdisplay/kernel-open/common/inc/nv-modeset-interface.h
Normal file
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_MODESET_INTERFACE_H_
|
||||
#define _NV_MODESET_INTERFACE_H_
|
||||
|
||||
/*
|
||||
* This file defines the interface between the nvidia and
|
||||
* nvidia-modeset UNIX kernel modules.
|
||||
*
|
||||
* The nvidia-modeset kernel module calls the nvidia kernel module's
|
||||
* nvidia_get_rm_ops() function to get the RM API function pointers
|
||||
* which it will need.
|
||||
*/
|
||||
|
||||
#include "nvstatus.h"
|
||||
|
||||
#include "nv-gpu-info.h"
|
||||
|
||||
/*
|
||||
* nvidia_stack_s is defined in nv.h, which pulls in a lot of other
|
||||
* dependencies. The nvidia-modeset kernel module doesn't need to
|
||||
* dereference the nvidia_stack_s pointer, so just treat is as an
|
||||
* opaque pointer for purposes of this API definition.
|
||||
*/
|
||||
typedef struct nvidia_stack_s *nvidia_modeset_stack_ptr;
|
||||
|
||||
/*
|
||||
* Callback functions from the RM OS interface layer into the NVKMS OS interface
|
||||
* layer.
|
||||
*
|
||||
* These functions should be called without the RM lock held, using the kernel's
|
||||
* native calling convention.
|
||||
*/
|
||||
typedef struct {
|
||||
/*
|
||||
* Suspend & resume callbacks. Note that these are called once per GPU.
|
||||
*/
|
||||
void (*suspend)(NvU32 gpu_id);
|
||||
void (*resume)(NvU32 gpu_id);
|
||||
} nvidia_modeset_callbacks_t;
|
||||
|
||||
/*
|
||||
* The RM API entry points which the nvidia-modeset kernel module should
|
||||
* call in the nvidia kernel module.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
/*
|
||||
* The nvidia-modeset kernel module should assign version_string
|
||||
* before passing the structure to the nvidia kernel module, so
|
||||
* that a version match can be confirmed: it is not supported to
|
||||
* mix nvidia and nvidia-modeset kernel modules from different
|
||||
* releases.
|
||||
*/
|
||||
const char *version_string;
|
||||
|
||||
/*
|
||||
* Return system information.
|
||||
*/
|
||||
struct {
|
||||
/* Availability of write combining support for video memory */
|
||||
NvBool allow_write_combining;
|
||||
} system_info;
|
||||
|
||||
/*
|
||||
* Allocate and free an nvidia_stack_t to pass into
|
||||
* nvidia_modeset_rm_ops_t::op(). An nvidia_stack_t must only be
|
||||
* used by one thread at a time.
|
||||
*
|
||||
* Note that on architectures where an alternate stack is not
|
||||
* used, alloc_stack() will set sp=NULL even when it returns 0
|
||||
* (success). I.e., check the return value, not the sp value.
|
||||
*/
|
||||
int (*alloc_stack)(nvidia_modeset_stack_ptr *sp);
|
||||
void (*free_stack)(nvidia_modeset_stack_ptr sp);
|
||||
|
||||
/*
|
||||
* Enumerate list of gpus probed by nvidia driver.
|
||||
*
|
||||
* gpu_info is an array of NVIDIA_MAX_GPUS elements. The number of GPUs
|
||||
* in the system is returned.
|
||||
*/
|
||||
NvU32 (*enumerate_gpus)(nv_gpu_info_t *gpu_info);
|
||||
|
||||
/*
|
||||
* {open,close}_gpu() raise and lower the reference count of the
|
||||
* specified GPU. This is equivalent to opening and closing a
|
||||
* /dev/nvidiaN device file from user-space.
|
||||
*/
|
||||
int (*open_gpu)(NvU32 gpu_id, nvidia_modeset_stack_ptr sp);
|
||||
void (*close_gpu)(NvU32 gpu_id, nvidia_modeset_stack_ptr sp);
|
||||
|
||||
void (*op)(nvidia_modeset_stack_ptr sp, void *ops_cmd);
|
||||
|
||||
int (*set_callbacks)(const nvidia_modeset_callbacks_t *cb);
|
||||
|
||||
} nvidia_modeset_rm_ops_t;
|
||||
|
||||
NV_STATUS nvidia_get_rm_ops(nvidia_modeset_rm_ops_t *rm_ops);
|
||||
|
||||
#endif /* _NV_MODESET_INTERFACE_H_ */
|
||||
115
nvdisplay/kernel-open/common/inc/nv-msi.h
Normal file
115
nvdisplay/kernel-open/common/inc/nv-msi.h
Normal file
@@ -0,0 +1,115 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_MSI_H_
|
||||
#define _NV_MSI_H_
|
||||
|
||||
#include "nv-linux.h"
|
||||
|
||||
#if (defined(CONFIG_X86_LOCAL_APIC) || defined(NVCPU_AARCH64) || \
|
||||
defined(NVCPU_PPC64LE)) && \
|
||||
(defined(CONFIG_PCI_MSI) || defined(CONFIG_PCI_USE_VECTOR))
|
||||
#define NV_LINUX_PCIE_MSI_SUPPORTED
|
||||
#endif
|
||||
|
||||
#if !defined(NV_LINUX_PCIE_MSI_SUPPORTED) || !defined(CONFIG_PCI_MSI)
|
||||
#define NV_PCI_DISABLE_MSI(pci_dev)
|
||||
#else
|
||||
#define NV_PCI_DISABLE_MSI(pci_dev) pci_disable_msi(pci_dev)
|
||||
#endif
|
||||
|
||||
irqreturn_t nvidia_isr (int, void *);
|
||||
irqreturn_t nvidia_isr_msix (int, void *);
|
||||
irqreturn_t nvidia_isr_kthread_bh (int, void *);
|
||||
irqreturn_t nvidia_isr_msix_kthread_bh(int, void *);
|
||||
|
||||
#if defined(NV_LINUX_PCIE_MSI_SUPPORTED)
|
||||
void NV_API_CALL nv_init_msi (nv_state_t *);
|
||||
void NV_API_CALL nv_init_msix (nv_state_t *);
|
||||
NvS32 NV_API_CALL nv_request_msix_irq (nv_linux_state_t *);
|
||||
|
||||
#define NV_PCI_MSIX_FLAGS 2
|
||||
#define NV_PCI_MSIX_FLAGS_QSIZE 0x7FF
|
||||
|
||||
static inline void nv_free_msix_irq(nv_linux_state_t *nvl)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nvl->num_intr; i++)
|
||||
{
|
||||
free_irq(nvl->msix_entries[i].vector, (void *)nvl);
|
||||
}
|
||||
}
|
||||
|
||||
static inline int nv_get_max_irq(struct pci_dev *pci_dev)
|
||||
{
|
||||
int nvec;
|
||||
int cap_ptr;
|
||||
NvU16 ctrl;
|
||||
|
||||
cap_ptr = pci_find_capability(pci_dev, PCI_CAP_ID_MSIX);
|
||||
/*
|
||||
* The 'PCI_MSIX_FLAGS' was added in 2.6.21-rc3 by:
|
||||
* 2007-03-05 f5f2b13129a6541debf8851bae843cbbf48298b7
|
||||
*/
|
||||
#if defined(PCI_MSIX_FLAGS)
|
||||
pci_read_config_word(pci_dev, cap_ptr + PCI_MSIX_FLAGS, &ctrl);
|
||||
nvec = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
|
||||
#else
|
||||
pci_read_config_word(pci_dev, cap_ptr + NV_PCI_MSIX_FLAGS, &ctrl);
|
||||
nvec = (ctrl & NV_PCI_MSIX_FLAGS_QSIZE) + 1;
|
||||
#endif
|
||||
|
||||
return nvec;
|
||||
}
|
||||
|
||||
static inline int nv_pci_enable_msix(nv_linux_state_t *nvl, int nvec)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
/*
|
||||
* pci_enable_msix_range() replaced pci_enable_msix() in 3.14-rc1:
|
||||
* 2014-01-03 302a2523c277bea0bbe8340312b09507905849ed
|
||||
*/
|
||||
|
||||
#if defined(NV_PCI_ENABLE_MSIX_RANGE_PRESENT)
|
||||
// We require all the vectors we are requesting so use the same min and max
|
||||
rc = pci_enable_msix_range(nvl->pci_dev, nvl->msix_entries, nvec, nvec);
|
||||
if (rc < 0)
|
||||
{
|
||||
return NV_ERR_OPERATING_SYSTEM;
|
||||
}
|
||||
WARN_ON(nvec != rc);
|
||||
#else
|
||||
rc = pci_enable_msix(nvl->pci_dev, nvl->msix_entries, nvec);
|
||||
if (rc != 0)
|
||||
{
|
||||
return NV_ERR_OPERATING_SYSTEM;
|
||||
}
|
||||
#endif
|
||||
|
||||
nvl->num_intr = nvec;
|
||||
return NV_OK;
|
||||
}
|
||||
#endif
|
||||
#endif /* _NV_MSI_H_ */
|
||||
36
nvdisplay/kernel-open/common/inc/nv-pci-types.h
Normal file
36
nvdisplay/kernel-open/common/inc/nv-pci-types.h
Normal file
@@ -0,0 +1,36 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_PCI_TYPES_H_
|
||||
#define _NV_PCI_TYPES_H_
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include "conftest.h"
|
||||
|
||||
#if defined(NV_PCI_CHANNEL_STATE_PRESENT)
|
||||
typedef enum pci_channel_state nv_pci_channel_state_t;
|
||||
#else
|
||||
typedef pci_channel_state_t nv_pci_channel_state_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
48
nvdisplay/kernel-open/common/inc/nv-pci.h
Normal file
48
nvdisplay/kernel-open/common/inc/nv-pci.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_PCI_H_
|
||||
#define _NV_PCI_H_
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include "nv-linux.h"
|
||||
|
||||
#if defined(NV_DEV_IS_PCI_PRESENT)
|
||||
#define nv_dev_is_pci(dev) dev_is_pci(dev)
|
||||
#else
|
||||
/*
|
||||
* Non-PCI devices are only supported on kernels which expose the
|
||||
* dev_is_pci() function. For older kernels, we only support PCI
|
||||
* devices, hence returning true to take all the PCI code paths.
|
||||
*/
|
||||
#define nv_dev_is_pci(dev) (true)
|
||||
#endif
|
||||
|
||||
int nv_pci_register_driver(void);
|
||||
void nv_pci_unregister_driver(void);
|
||||
int nv_pci_count_devices(void);
|
||||
NvU8 nv_find_pci_capability(struct pci_dev *, NvU8);
|
||||
int nvidia_dev_get_pci_info(const NvU8 *, struct pci_dev **, NvU64 *, NvU64 *);
|
||||
nv_linux_state_t * find_pci(NvU32, NvU8, NvU8, NvU8);
|
||||
|
||||
#endif
|
||||
134
nvdisplay/kernel-open/common/inc/nv-pgprot.h
Normal file
134
nvdisplay/kernel-open/common/inc/nv-pgprot.h
Normal file
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NV_PGPROT_H__
|
||||
|
||||
#define __NV_PGPROT_H__
|
||||
|
||||
#include "cpuopsys.h"
|
||||
|
||||
#include <linux/mm.h>
|
||||
|
||||
#if !defined(NV_VMWARE)
|
||||
#if defined(NVCPU_X86_64)
|
||||
/* mark memory UC-, rather than UC (don't use _PAGE_PWT) */
|
||||
static inline pgprot_t pgprot_noncached_weak(pgprot_t old_prot)
|
||||
{
|
||||
pgprot_t new_prot = old_prot;
|
||||
if (boot_cpu_data.x86 > 3)
|
||||
new_prot = __pgprot(pgprot_val(old_prot) | _PAGE_PCD);
|
||||
return new_prot;
|
||||
}
|
||||
|
||||
#if !defined (pgprot_noncached)
|
||||
static inline pgprot_t pgprot_noncached(pgprot_t old_prot)
|
||||
{
|
||||
pgprot_t new_prot = old_prot;
|
||||
if (boot_cpu_data.x86 > 3)
|
||||
new_prot = __pgprot(pgprot_val(old_prot) | _PAGE_PCD | _PAGE_PWT);
|
||||
return new_prot;
|
||||
}
|
||||
#endif
|
||||
static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot)
|
||||
{
|
||||
pgprot_t new_prot = old_prot;
|
||||
pgprot_val(new_prot) &= ~(_PAGE_PSE | _PAGE_PCD | _PAGE_PWT);
|
||||
new_prot = __pgprot(pgprot_val(new_prot) | _PAGE_PWT);
|
||||
return new_prot;
|
||||
}
|
||||
#endif /* defined(NVCPU_X86_64) */
|
||||
#endif /* !defined(NV_VMWARE) */
|
||||
|
||||
#if defined(NVCPU_AARCH64)
|
||||
/*
|
||||
* Don't rely on the kernel's definition of pgprot_noncached(), as on 64-bit
|
||||
* ARM that's not for system memory, but device memory instead. For I/O cache
|
||||
* coherent systems, use cached mappings instead of uncached.
|
||||
*/
|
||||
#define NV_PGPROT_UNCACHED(old_prot) \
|
||||
((nvos_is_chipset_io_coherent()) ? \
|
||||
(old_prot) : \
|
||||
__pgprot_modify((old_prot), PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)))
|
||||
#elif defined(NVCPU_PPC64LE)
|
||||
/* Don't attempt to mark sysmem pages as uncached on ppc64le */
|
||||
#define NV_PGPROT_UNCACHED(old_prot) old_prot
|
||||
#else
|
||||
#define NV_PGPROT_UNCACHED(old_prot) pgprot_noncached(old_prot)
|
||||
#endif
|
||||
|
||||
#define NV_PGPROT_UNCACHED_DEVICE(old_prot) pgprot_noncached(old_prot)
|
||||
#if defined(NVCPU_AARCH64)
|
||||
#if defined(NV_MT_DEVICE_GRE_PRESENT)
|
||||
#define NV_PROT_WRITE_COMBINED_DEVICE (PROT_DEFAULT | PTE_PXN | PTE_UXN | \
|
||||
PTE_ATTRINDX(MT_DEVICE_GRE))
|
||||
#else
|
||||
#define NV_PROT_WRITE_COMBINED_DEVICE (PROT_DEFAULT | PTE_PXN | PTE_UXN | \
|
||||
PTE_ATTRINDX(MT_DEVICE_nGnRE))
|
||||
#endif
|
||||
#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
|
||||
__pgprot_modify(old_prot, PTE_ATTRINDX_MASK, NV_PROT_WRITE_COMBINED_DEVICE)
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) NV_PGPROT_UNCACHED(old_prot)
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot_modify(old_prot, 0, PTE_RDONLY)
|
||||
#elif defined(NVCPU_X86_64)
|
||||
#define NV_PGPROT_UNCACHED_WEAK(old_prot) pgprot_noncached_weak(old_prot)
|
||||
#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
|
||||
pgprot_modify_writecombine(old_prot)
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) \
|
||||
NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot(pgprot_val((old_prot)) & ~_PAGE_RW)
|
||||
#elif defined(NVCPU_PPC64LE)
|
||||
/*
|
||||
* Some kernels use H_PAGE instead of _PAGE
|
||||
*/
|
||||
#if defined(_PAGE_RW)
|
||||
#define NV_PAGE_RW _PAGE_RW
|
||||
#elif defined(H_PAGE_RW)
|
||||
#define NV_PAGE_RW H_PAGE_RW
|
||||
#else
|
||||
#warning "The kernel does not provide page protection defines!"
|
||||
#endif
|
||||
|
||||
#if defined(_PAGE_4K_PFN)
|
||||
#define NV_PAGE_4K_PFN _PAGE_4K_PFN
|
||||
#elif defined(H_PAGE_4K_PFN)
|
||||
#define NV_PAGE_4K_PFN H_PAGE_4K_PFN
|
||||
#else
|
||||
#undef NV_PAGE_4K_PFN
|
||||
#endif
|
||||
|
||||
#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
|
||||
pgprot_writecombine(old_prot)
|
||||
/* Don't attempt to mark sysmem pages as write combined on ppc64le */
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot(pgprot_val((old_prot)) & ~NV_PAGE_RW)
|
||||
#else
|
||||
/* Writecombine is not supported */
|
||||
#undef NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
|
||||
#undef NV_PGPROT_WRITE_COMBINED(old_prot)
|
||||
#define NV_PGPROT_READ_ONLY(old_prot)
|
||||
#endif
|
||||
|
||||
#endif /* __NV_PGPROT_H__ */
|
||||
40
nvdisplay/kernel-open/common/inc/nv-platform.h
Normal file
40
nvdisplay/kernel-open/common/inc/nv-platform.h
Normal file
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef NV_PLATFORM_H
|
||||
#define NV_PLATFORM_H
|
||||
|
||||
#include "nv-linux.h"
|
||||
|
||||
irqreturn_t nvidia_isr (int, void *);
|
||||
irqreturn_t nvidia_isr_kthread_bh (int, void *);
|
||||
|
||||
|
||||
int nv_platform_register_driver(void);
|
||||
void nv_platform_unregister_driver(void);
|
||||
int nv_platform_count_devices(void);
|
||||
int nv_soc_register_irqs(nv_state_t *nv);
|
||||
void nv_soc_free_irqs(nv_state_t *nv);
|
||||
|
||||
|
||||
#endif
|
||||
227
nvdisplay/kernel-open/common/inc/nv-procfs-utils.h
Normal file
227
nvdisplay/kernel-open/common/inc/nv-procfs-utils.h
Normal file
@@ -0,0 +1,227 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _NV_PROCFS_UTILS_H
|
||||
#define _NV_PROCFS_UTILS_H
|
||||
|
||||
#include "conftest.h"
|
||||
|
||||
#ifdef CONFIG_PROC_FS
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
/*
|
||||
* Allow procfs to create file to exercise error forwarding.
|
||||
* This is supported by CRAY platforms.
|
||||
*/
|
||||
#if defined(CONFIG_CRAY_XT)
|
||||
#define EXERCISE_ERROR_FORWARDING NV_TRUE
|
||||
#else
|
||||
#define EXERCISE_ERROR_FORWARDING NV_FALSE
|
||||
#endif
|
||||
|
||||
#define IS_EXERCISE_ERROR_FORWARDING_ENABLED() (EXERCISE_ERROR_FORWARDING)
|
||||
|
||||
#if defined(NV_PROC_OPS_PRESENT)
|
||||
typedef struct proc_ops nv_proc_ops_t;
|
||||
|
||||
#define NV_PROC_OPS_SET_OWNER()
|
||||
|
||||
#define NV_PROC_OPS_OPEN proc_open
|
||||
#define NV_PROC_OPS_READ proc_read
|
||||
#define NV_PROC_OPS_WRITE proc_write
|
||||
#define NV_PROC_OPS_LSEEK proc_lseek
|
||||
#define NV_PROC_OPS_RELEASE proc_release
|
||||
#else
|
||||
typedef struct file_operations nv_proc_ops_t;
|
||||
|
||||
#define NV_PROC_OPS_SET_OWNER() .owner = THIS_MODULE,
|
||||
|
||||
#define NV_PROC_OPS_OPEN open
|
||||
#define NV_PROC_OPS_READ read
|
||||
#define NV_PROC_OPS_WRITE write
|
||||
#define NV_PROC_OPS_LSEEK llseek
|
||||
#define NV_PROC_OPS_RELEASE release
|
||||
#endif
|
||||
|
||||
#define NV_CREATE_PROC_FILE(filename,parent,__name,__data) \
|
||||
({ \
|
||||
struct proc_dir_entry *__entry; \
|
||||
int mode = (S_IFREG | S_IRUGO); \
|
||||
const nv_proc_ops_t *fops = &nv_procfs_##__name##_fops; \
|
||||
if (fops->NV_PROC_OPS_WRITE != 0) \
|
||||
mode |= S_IWUSR; \
|
||||
__entry = proc_create_data(filename, mode, parent, fops, __data);\
|
||||
__entry; \
|
||||
})
|
||||
|
||||
/*
|
||||
* proc_mkdir_mode exists in Linux 2.6.9, but isn't exported until Linux 3.0.
|
||||
* Use the older interface instead unless the newer interface is necessary.
|
||||
*/
|
||||
#if defined(NV_PROC_REMOVE_PRESENT)
|
||||
# define NV_PROC_MKDIR_MODE(name, mode, parent) \
|
||||
proc_mkdir_mode(name, mode, parent)
|
||||
#else
|
||||
# define NV_PROC_MKDIR_MODE(name, mode, parent) \
|
||||
({ \
|
||||
struct proc_dir_entry *__entry; \
|
||||
__entry = create_proc_entry(name, mode, parent); \
|
||||
__entry; \
|
||||
})
|
||||
#endif
|
||||
|
||||
#define NV_CREATE_PROC_DIR(name,parent) \
|
||||
({ \
|
||||
struct proc_dir_entry *__entry; \
|
||||
int mode = (S_IFDIR | S_IRUGO | S_IXUGO); \
|
||||
__entry = NV_PROC_MKDIR_MODE(name, mode, parent); \
|
||||
__entry; \
|
||||
})
|
||||
|
||||
#if defined(NV_PDE_DATA_LOWER_CASE_PRESENT)
|
||||
#define NV_PDE_DATA(inode) pde_data(inode)
|
||||
#else
|
||||
#define NV_PDE_DATA(inode) PDE_DATA(inode)
|
||||
#endif
|
||||
|
||||
#if defined(NV_PROC_REMOVE_PRESENT)
|
||||
# define NV_REMOVE_PROC_ENTRY(entry) \
|
||||
proc_remove(entry);
|
||||
#else
|
||||
# define NV_REMOVE_PROC_ENTRY(entry) \
|
||||
remove_proc_entry(entry->name, entry->parent);
|
||||
#endif
|
||||
|
||||
void nv_procfs_unregister_all(struct proc_dir_entry *entry,
|
||||
struct proc_dir_entry *delimiter);
|
||||
#define NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \
|
||||
static int nv_procfs_open_##name( \
|
||||
struct inode *inode, \
|
||||
struct file *filep \
|
||||
) \
|
||||
{ \
|
||||
int ret; \
|
||||
ret = single_open(filep, nv_procfs_read_##name, \
|
||||
NV_PDE_DATA(inode)); \
|
||||
if (ret < 0) \
|
||||
{ \
|
||||
return ret; \
|
||||
} \
|
||||
ret = nv_down_read_interruptible(&lock); \
|
||||
if (ret < 0) \
|
||||
{ \
|
||||
single_release(inode, filep); \
|
||||
} \
|
||||
return ret; \
|
||||
} \
|
||||
\
|
||||
static int nv_procfs_release_##name( \
|
||||
struct inode *inode, \
|
||||
struct file *filep \
|
||||
) \
|
||||
{ \
|
||||
up_read(&lock); \
|
||||
return single_release(inode, filep); \
|
||||
}
|
||||
|
||||
#define NV_DEFINE_SINGLE_PROCFS_FILE_READ_ONLY(name, lock) \
|
||||
NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \
|
||||
\
|
||||
static const nv_proc_ops_t nv_procfs_##name##_fops = { \
|
||||
NV_PROC_OPS_SET_OWNER() \
|
||||
.NV_PROC_OPS_OPEN = nv_procfs_open_##name, \
|
||||
.NV_PROC_OPS_READ = seq_read, \
|
||||
.NV_PROC_OPS_LSEEK = seq_lseek, \
|
||||
.NV_PROC_OPS_RELEASE = nv_procfs_release_##name, \
|
||||
};
|
||||
|
||||
|
||||
#define NV_DEFINE_SINGLE_PROCFS_FILE_READ_WRITE(name, lock, \
|
||||
write_callback) \
|
||||
NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \
|
||||
\
|
||||
static ssize_t nv_procfs_write_##name( \
|
||||
struct file *file, \
|
||||
const char __user *buf, \
|
||||
size_t size, \
|
||||
loff_t *ppos \
|
||||
) \
|
||||
{ \
|
||||
ssize_t ret; \
|
||||
struct seq_file *s; \
|
||||
\
|
||||
s = file->private_data; \
|
||||
if (s == NULL) \
|
||||
{ \
|
||||
return -EIO; \
|
||||
} \
|
||||
\
|
||||
ret = write_callback(s, buf + *ppos, size - *ppos); \
|
||||
if (ret == 0) \
|
||||
{ \
|
||||
/* avoid infinite loop */ \
|
||||
ret = -EIO; \
|
||||
} \
|
||||
return ret; \
|
||||
} \
|
||||
\
|
||||
static const nv_proc_ops_t nv_procfs_##name##_fops = { \
|
||||
NV_PROC_OPS_SET_OWNER() \
|
||||
.NV_PROC_OPS_OPEN = nv_procfs_open_##name, \
|
||||
.NV_PROC_OPS_READ = seq_read, \
|
||||
.NV_PROC_OPS_WRITE = nv_procfs_write_##name, \
|
||||
.NV_PROC_OPS_LSEEK = seq_lseek, \
|
||||
.NV_PROC_OPS_RELEASE = nv_procfs_release_##name, \
|
||||
};
|
||||
|
||||
#define NV_DEFINE_SINGLE_PROCFS_FILE_READ_ONLY_WITHOUT_LOCK(name) \
|
||||
static int nv_procfs_open_##name( \
|
||||
struct inode *inode, \
|
||||
struct file *filep \
|
||||
) \
|
||||
{ \
|
||||
int ret; \
|
||||
ret = single_open(filep, nv_procfs_read_##name, \
|
||||
NV_PDE_DATA(inode)); \
|
||||
return ret; \
|
||||
} \
|
||||
\
|
||||
static int nv_procfs_release_##name( \
|
||||
struct inode *inode, \
|
||||
struct file *filep \
|
||||
) \
|
||||
{ \
|
||||
return single_release(inode, filep); \
|
||||
} \
|
||||
\
|
||||
static const nv_proc_ops_t nv_procfs_##name##_fops = { \
|
||||
NV_PROC_OPS_SET_OWNER() \
|
||||
.NV_PROC_OPS_OPEN = nv_procfs_open_##name, \
|
||||
.NV_PROC_OPS_READ = seq_read, \
|
||||
.NV_PROC_OPS_LSEEK = seq_lseek, \
|
||||
.NV_PROC_OPS_RELEASE = nv_procfs_release_##name, \
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PROC_FS */
|
||||
|
||||
#endif /* _NV_PROCFS_UTILS_H */
|
||||
28
nvdisplay/kernel-open/common/inc/nv-procfs.h
Normal file
28
nvdisplay/kernel-open/common/inc/nv-procfs.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _NV_PROCFS_H
|
||||
#define _NV_PROCFS_H
|
||||
|
||||
#include "nv-procfs-utils.h"
|
||||
|
||||
#endif /* _NV_PROCFS_H */
|
||||
98
nvdisplay/kernel-open/common/inc/nv-proto.h
Normal file
98
nvdisplay/kernel-open/common/inc/nv-proto.h
Normal file
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_PROTO_H_
|
||||
#define _NV_PROTO_H_
|
||||
|
||||
#include "nv-pci.h"
|
||||
#include "nv-register-module.h"
|
||||
|
||||
#include "nv-platform.h"
|
||||
|
||||
|
||||
extern const char *nv_device_name;
|
||||
extern nvidia_module_t nv_fops;
|
||||
|
||||
void nv_acpi_register_notifier (nv_linux_state_t *);
|
||||
void nv_acpi_unregister_notifier (nv_linux_state_t *);
|
||||
|
||||
NvU8 nv_find_pci_capability (struct pci_dev *, NvU8);
|
||||
|
||||
int nv_procfs_init (void);
|
||||
void nv_procfs_exit (void);
|
||||
void nv_procfs_add_warning (const char *, const char *);
|
||||
int nv_procfs_add_gpu (nv_linux_state_t *);
|
||||
void nv_procfs_remove_gpu (nv_linux_state_t *);
|
||||
|
||||
int nvidia_mmap (struct file *, struct vm_area_struct *);
|
||||
int nvidia_mmap_helper (nv_state_t *, nv_linux_file_private_t *, nvidia_stack_t *, struct vm_area_struct *, void *);
|
||||
int nv_encode_caching (pgprot_t *, NvU32, NvU32);
|
||||
void nv_revoke_gpu_mappings_locked(nv_state_t *);
|
||||
|
||||
NvUPtr nv_vm_map_pages (struct page **, NvU32, NvBool, NvBool);
|
||||
void nv_vm_unmap_pages (NvUPtr, NvU32);
|
||||
|
||||
NV_STATUS nv_alloc_contig_pages (nv_state_t *, nv_alloc_t *);
|
||||
void nv_free_contig_pages (nv_alloc_t *);
|
||||
NV_STATUS nv_alloc_system_pages (nv_state_t *, nv_alloc_t *);
|
||||
void nv_free_system_pages (nv_alloc_t *);
|
||||
|
||||
void nv_address_space_init_once (struct address_space *mapping);
|
||||
|
||||
int nv_uvm_init (void);
|
||||
void nv_uvm_exit (void);
|
||||
NV_STATUS nv_uvm_suspend (void);
|
||||
NV_STATUS nv_uvm_resume (void);
|
||||
void nv_uvm_notify_start_device (const NvU8 *uuid);
|
||||
void nv_uvm_notify_stop_device (const NvU8 *uuid);
|
||||
NV_STATUS nv_uvm_event_interrupt (const NvU8 *uuid);
|
||||
|
||||
/* Move these to nv.h once implemented by other UNIX platforms */
|
||||
NvBool nvidia_get_gpuid_list (NvU32 *gpu_ids, NvU32 *gpu_count);
|
||||
int nvidia_dev_get (NvU32, nvidia_stack_t *);
|
||||
void nvidia_dev_put (NvU32, nvidia_stack_t *);
|
||||
int nvidia_dev_get_uuid (const NvU8 *, nvidia_stack_t *);
|
||||
void nvidia_dev_put_uuid (const NvU8 *, nvidia_stack_t *);
|
||||
int nvidia_dev_block_gc6 (const NvU8 *, nvidia_stack_t *);
|
||||
int nvidia_dev_unblock_gc6 (const NvU8 *, nvidia_stack_t *);
|
||||
|
||||
#if defined(CONFIG_PM)
|
||||
NV_STATUS nv_set_system_power_state (nv_power_state_t, nv_pm_action_depth_t);
|
||||
#endif
|
||||
|
||||
void nvidia_modeset_suspend (NvU32 gpuId);
|
||||
void nvidia_modeset_resume (NvU32 gpuId);
|
||||
NvBool nv_is_uuid_in_gpu_exclusion_list (const char *);
|
||||
|
||||
NV_STATUS nv_parse_per_device_option_string(nvidia_stack_t *sp);
|
||||
nv_linux_state_t * find_uuid(const NvU8 *uuid);
|
||||
void nv_report_error(struct pci_dev *dev, NvU32 error_number, const char *format, va_list ap);
|
||||
void nv_shutdown_adapter(nvidia_stack_t *, nv_state_t *, nv_linux_state_t *);
|
||||
void nv_dev_free_stacks(nv_linux_state_t *);
|
||||
NvBool nv_lock_init_locks(nvidia_stack_t *, nv_state_t *);
|
||||
void nv_lock_destroy_locks(nvidia_stack_t *, nv_state_t *);
|
||||
void nv_linux_add_device_locked(nv_linux_state_t *);
|
||||
void nv_linux_remove_device_locked(nv_linux_state_t *);
|
||||
NvBool nv_acpi_power_resource_method_present(struct pci_dev *);
|
||||
|
||||
#endif /* _NV_PROTO_H_ */
|
||||
55
nvdisplay/kernel-open/common/inc/nv-register-module.h
Normal file
55
nvdisplay/kernel-open/common/inc/nv-register-module.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2012-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _NV_REGISTER_MODULE_H_
|
||||
#define _NV_REGISTER_MODULE_H_
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/poll.h>
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
typedef struct nvidia_module_s {
|
||||
struct module *owner;
|
||||
|
||||
/* nvidia0, nvidia1 ..*/
|
||||
const char *module_name;
|
||||
|
||||
/* module instance */
|
||||
NvU32 instance;
|
||||
|
||||
/* file operations */
|
||||
int (*open)(struct inode *, struct file *filp);
|
||||
int (*close)(struct inode *, struct file *filp);
|
||||
int (*mmap)(struct file *filp, struct vm_area_struct *vma);
|
||||
int (*ioctl)(struct inode *, struct file * file, unsigned int cmd, unsigned long arg);
|
||||
unsigned int (*poll)(struct file * file, poll_table *wait);
|
||||
|
||||
} nvidia_module_t;
|
||||
|
||||
int nvidia_register_module(nvidia_module_t *);
|
||||
int nvidia_unregister_module(nvidia_module_t *);
|
||||
|
||||
#endif
|
||||
82
nvdisplay/kernel-open/common/inc/nv-retpoline.h
Normal file
82
nvdisplay/kernel-open/common/inc/nv-retpoline.h
Normal file
@@ -0,0 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_RETPOLINE_H_
|
||||
#define _NV_RETPOLINE_H_
|
||||
|
||||
#include "cpuopsys.h"
|
||||
|
||||
#if (NV_SPECTRE_V2 == 0)
|
||||
#define NV_RETPOLINE_THUNK NV_SPEC_THUNK
|
||||
#else
|
||||
#define NV_RETPOLINE_THUNK NV_NOSPEC_THUNK
|
||||
#endif
|
||||
|
||||
#if defined(NVCPU_X86_64)
|
||||
#define NV_SPEC_THUNK(REG) \
|
||||
__asm__( \
|
||||
".weak __x86_indirect_thunk_" #REG ";" \
|
||||
".type __x86_indirect_thunk_" #REG ", @function;" \
|
||||
"__x86_indirect_thunk_" #REG ":" \
|
||||
" .cfi_startproc;" \
|
||||
" jmp *%" #REG ";" \
|
||||
" .cfi_endproc;" \
|
||||
".size __x86_indirect_thunk_" #REG ", .-__x86_indirect_thunk_" #REG)
|
||||
|
||||
#define NV_NOSPEC_THUNK(REG) \
|
||||
__asm__( \
|
||||
".weak __x86_indirect_thunk_" #REG ";" \
|
||||
".type __x86_indirect_thunk_" #REG ", @function;" \
|
||||
"__x86_indirect_thunk_" #REG ":" \
|
||||
" .cfi_startproc;" \
|
||||
" call .Lnv_no_fence_" #REG ";" \
|
||||
".Lnv_fence_" #REG ":" \
|
||||
" pause;" \
|
||||
" lfence;" \
|
||||
" jmp .Lnv_fence_" #REG ";" \
|
||||
".Lnv_no_fence_" #REG ":" \
|
||||
" mov %" #REG ", (%rsp);" \
|
||||
" ret;" \
|
||||
" .cfi_endproc;" \
|
||||
".size __x86_indirect_thunk_" #REG ", .-__x86_indirect_thunk_" #REG)
|
||||
|
||||
__asm__(".pushsection .text");
|
||||
NV_RETPOLINE_THUNK(rax);
|
||||
NV_RETPOLINE_THUNK(rbx);
|
||||
NV_RETPOLINE_THUNK(rcx);
|
||||
NV_RETPOLINE_THUNK(rdx);
|
||||
NV_RETPOLINE_THUNK(rsi);
|
||||
NV_RETPOLINE_THUNK(rdi);
|
||||
NV_RETPOLINE_THUNK(rbp);
|
||||
NV_RETPOLINE_THUNK(r8);
|
||||
NV_RETPOLINE_THUNK(r9);
|
||||
NV_RETPOLINE_THUNK(r10);
|
||||
NV_RETPOLINE_THUNK(r11);
|
||||
NV_RETPOLINE_THUNK(r12);
|
||||
NV_RETPOLINE_THUNK(r13);
|
||||
NV_RETPOLINE_THUNK(r14);
|
||||
NV_RETPOLINE_THUNK(r15);
|
||||
__asm__(".popsection");
|
||||
#endif
|
||||
|
||||
#endif /* _NV_RETPOLINE_H_ */
|
||||
251
nvdisplay/kernel-open/common/inc/nv-time.h
Normal file
251
nvdisplay/kernel-open/common/inc/nv-time.h
Normal file
@@ -0,0 +1,251 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NV_TIME_H__
|
||||
#define __NV_TIME_H__
|
||||
|
||||
#include "conftest.h"
|
||||
#include <linux/sched.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ktime.h>
|
||||
|
||||
#include <nvstatus.h>
|
||||
|
||||
#define NV_MAX_ISR_DELAY_US 20000
|
||||
#define NV_MAX_ISR_DELAY_MS (NV_MAX_ISR_DELAY_US / 1000)
|
||||
#define NV_NSECS_TO_JIFFIES(nsec) ((nsec) * HZ / 1000000000)
|
||||
|
||||
#if !defined(NV_TIMESPEC64_PRESENT)
|
||||
struct timespec64 {
|
||||
__s64 tv_sec;
|
||||
long tv_nsec;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if !defined(NV_KTIME_GET_RAW_TS64_PRESENT)
|
||||
static inline void ktime_get_raw_ts64(struct timespec64 *ts64)
|
||||
{
|
||||
struct timespec ts;
|
||||
getrawmonotonic(&ts);
|
||||
ts64->tv_sec = ts.tv_sec;
|
||||
ts64->tv_nsec = ts.tv_nsec;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(NV_KTIME_GET_REAL_TS64_PRESENT)
|
||||
static inline void ktime_get_real_ts64(struct timespec64 *ts64)
|
||||
{
|
||||
struct timeval tv;
|
||||
do_gettimeofday(&tv);
|
||||
ts64->tv_sec = tv.tv_sec;
|
||||
ts64->tv_nsec = tv.tv_usec * (NvU64) NSEC_PER_USEC;
|
||||
}
|
||||
#endif
|
||||
|
||||
static NvBool nv_timer_less_than
|
||||
(
|
||||
const struct timespec64 *a,
|
||||
const struct timespec64 *b
|
||||
)
|
||||
{
|
||||
return (a->tv_sec == b->tv_sec) ? (a->tv_nsec < b->tv_nsec)
|
||||
: (a->tv_sec < b->tv_sec);
|
||||
}
|
||||
|
||||
#if !defined(NV_TIMESPEC64_PRESENT)
|
||||
static inline struct timespec64 timespec64_add
|
||||
(
|
||||
const struct timespec64 a,
|
||||
const struct timespec64 b
|
||||
)
|
||||
{
|
||||
struct timespec64 result;
|
||||
|
||||
result.tv_sec = a.tv_sec + b.tv_sec;
|
||||
result.tv_nsec = a.tv_nsec + b.tv_nsec;
|
||||
while (result.tv_nsec >= NSEC_PER_SEC)
|
||||
{
|
||||
++result.tv_sec;
|
||||
result.tv_nsec -= NSEC_PER_SEC;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline struct timespec64 timespec64_sub
|
||||
(
|
||||
const struct timespec64 a,
|
||||
const struct timespec64 b
|
||||
)
|
||||
{
|
||||
struct timespec64 result;
|
||||
|
||||
result.tv_sec = a.tv_sec - b.tv_sec;
|
||||
result.tv_nsec = a.tv_nsec - b.tv_nsec;
|
||||
while (result.tv_nsec < 0)
|
||||
{
|
||||
--(result.tv_sec);
|
||||
result.tv_nsec += NSEC_PER_SEC;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline s64 timespec64_to_ns(struct timespec64 *ts)
|
||||
{
|
||||
return ((s64) ts->tv_sec * NSEC_PER_SEC) + ts->tv_nsec;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline NvU64 nv_ktime_get_raw_ns(void)
|
||||
{
|
||||
struct timespec64 ts;
|
||||
ktime_get_raw_ts64(&ts);
|
||||
return (NvU64)timespec64_to_ns(&ts);
|
||||
}
|
||||
|
||||
// #define NV_CHECK_DELAY_ACCURACY 1
|
||||
|
||||
/*
|
||||
* It is generally a bad idea to use udelay() to wait for more than
|
||||
* a few milliseconds. Since the caller is most likely not aware of
|
||||
* this, we use mdelay() for any full millisecond to be safe.
|
||||
*/
|
||||
static inline NV_STATUS nv_sleep_us(unsigned int us)
|
||||
{
|
||||
|
||||
unsigned long mdelay_safe_msec;
|
||||
unsigned long usec;
|
||||
|
||||
#ifdef NV_CHECK_DELAY_ACCURACY
|
||||
struct timespec64 tm1, tm2, tm_diff;
|
||||
|
||||
ktime_get_raw_ts64(&tm1);
|
||||
#endif
|
||||
|
||||
if (in_irq() && (us > NV_MAX_ISR_DELAY_US))
|
||||
return NV_ERR_GENERIC;
|
||||
|
||||
mdelay_safe_msec = us / 1000;
|
||||
if (mdelay_safe_msec)
|
||||
mdelay(mdelay_safe_msec);
|
||||
|
||||
usec = us % 1000;
|
||||
if (usec)
|
||||
udelay(usec);
|
||||
|
||||
#ifdef NV_CHECK_DELAY_ACCURACY
|
||||
ktime_get_raw_ts64(&tm2);
|
||||
tm_diff = timespec64_sub(tm2, tm1);
|
||||
pr_info("NVRM: delay of %d usec results in actual delay of 0x%llu nsec\n",
|
||||
us, timespec64_to_ns(&tm_diff));
|
||||
#endif
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* Sleep for specified milliseconds. Yields the CPU to scheduler.
|
||||
*
|
||||
* On Linux, a jiffie represents the time passed in between two timer
|
||||
* interrupts. The number of jiffies per second (HZ) varies across the
|
||||
* supported platforms. On i386, where HZ is 100, a timer interrupt is
|
||||
* generated every 10ms. NV_MSECS_TO_JIFFIES should be accurate independent of
|
||||
* the actual value of HZ; any partial jiffies will be 'floor'ed, the
|
||||
* remainder will be accounted for with mdelay().
|
||||
*/
|
||||
static inline NV_STATUS nv_sleep_ms(unsigned int ms)
|
||||
{
|
||||
NvU64 ns;
|
||||
unsigned long jiffies;
|
||||
unsigned long mdelay_safe_msec;
|
||||
struct timespec64 tm_end, tm_aux;
|
||||
#ifdef NV_CHECK_DELAY_ACCURACY
|
||||
struct timespec64 tm_start;
|
||||
#endif
|
||||
|
||||
ktime_get_raw_ts64(&tm_aux);
|
||||
#ifdef NV_CHECK_DELAY_ACCURACY
|
||||
tm_start = tm_aux;
|
||||
#endif
|
||||
|
||||
if (in_irq() && (ms > NV_MAX_ISR_DELAY_MS))
|
||||
{
|
||||
return NV_ERR_GENERIC;
|
||||
}
|
||||
|
||||
if (irqs_disabled() || in_interrupt() || in_atomic())
|
||||
{
|
||||
mdelay(ms);
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
ns = ms * (NvU64) NSEC_PER_MSEC;
|
||||
tm_end.tv_nsec = ns;
|
||||
tm_end.tv_sec = 0;
|
||||
tm_end = timespec64_add(tm_aux, tm_end);
|
||||
|
||||
/* do we have a full jiffie to wait? */
|
||||
jiffies = NV_NSECS_TO_JIFFIES(ns);
|
||||
|
||||
if (jiffies)
|
||||
{
|
||||
//
|
||||
// If we have at least one full jiffy to wait, give up
|
||||
// up the CPU; since we may be rescheduled before
|
||||
// the requested timeout has expired, loop until less
|
||||
// than a jiffie of the desired delay remains.
|
||||
//
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
do
|
||||
{
|
||||
schedule_timeout(jiffies);
|
||||
ktime_get_raw_ts64(&tm_aux);
|
||||
if (nv_timer_less_than(&tm_aux, &tm_end))
|
||||
{
|
||||
tm_aux = timespec64_sub(tm_end, tm_aux);
|
||||
ns = (NvU64) timespec64_to_ns(&tm_aux);
|
||||
}
|
||||
else
|
||||
ns = 0;
|
||||
} while ((jiffies = NV_NSECS_TO_JIFFIES(ns)) != 0);
|
||||
}
|
||||
|
||||
if (ns > (NvU64) NSEC_PER_MSEC)
|
||||
{
|
||||
mdelay_safe_msec = ns / (NvU64) NSEC_PER_MSEC;
|
||||
mdelay(mdelay_safe_msec);
|
||||
ns %= (NvU64) NSEC_PER_MSEC;
|
||||
}
|
||||
if (ns)
|
||||
{
|
||||
ndelay(ns);
|
||||
}
|
||||
#ifdef NV_CHECK_DELAY_ACCURACY
|
||||
ktime_get_raw_ts64(&tm_aux);
|
||||
tm_aux = timespec64_sub(tm_aux, tm_start);
|
||||
pr_info("NVRM: delay of %d msec results in actual delay of %lld.%09ld sec\n",
|
||||
ms, tm_aux.tv_sec, tm_aux.tv_nsec);
|
||||
#endif
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
#endif // __NV_TIME_H__
|
||||
66
nvdisplay/kernel-open/common/inc/nv-timer.h
Normal file
66
nvdisplay/kernel-open/common/inc/nv-timer.h
Normal file
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef __NV_TIMER_H__
|
||||
#define __NV_TIMER_H__
|
||||
|
||||
#include <linux/timer.h>
|
||||
#include <linux/kernel.h> // For container_of
|
||||
|
||||
#include "conftest.h"
|
||||
|
||||
struct nv_timer
|
||||
{
|
||||
struct timer_list kernel_timer;
|
||||
void (*nv_timer_callback)(struct nv_timer *nv_timer);
|
||||
};
|
||||
|
||||
static inline void nv_timer_callback_typed_data(struct timer_list *timer)
|
||||
{
|
||||
struct nv_timer *nv_timer =
|
||||
container_of(timer, struct nv_timer, kernel_timer);
|
||||
|
||||
nv_timer->nv_timer_callback(nv_timer);
|
||||
}
|
||||
|
||||
static inline void nv_timer_callback_anon_data(unsigned long arg)
|
||||
{
|
||||
struct nv_timer *nv_timer = (struct nv_timer *)arg;
|
||||
|
||||
nv_timer->nv_timer_callback(nv_timer);
|
||||
}
|
||||
|
||||
static inline void nv_timer_setup(struct nv_timer *nv_timer,
|
||||
void (*callback)(struct nv_timer *nv_timer))
|
||||
{
|
||||
nv_timer->nv_timer_callback = callback;
|
||||
|
||||
#if defined(NV_TIMER_SETUP_PRESENT)
|
||||
timer_setup(&nv_timer->kernel_timer, nv_timer_callback_typed_data, 0);
|
||||
#else
|
||||
init_timer(&nv_timer->kernel_timer);
|
||||
nv_timer->kernel_timer.function = nv_timer_callback_anon_data;
|
||||
nv_timer->kernel_timer.data = (unsigned long)nv_timer;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // __NV_TIMER_H__
|
||||
1103
nvdisplay/kernel-open/common/inc/nv.h
Normal file
1103
nvdisplay/kernel-open/common/inc/nv.h
Normal file
File diff suppressed because it is too large
Load Diff
44
nvdisplay/kernel-open/common/inc/nvCpuUuid.h
Normal file
44
nvdisplay/kernel-open/common/inc/nvCpuUuid.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _NV_CPU_UUID_H_
|
||||
#define _NV_CPU_UUID_H_
|
||||
|
||||
#define NV_UUID_LEN 16
|
||||
|
||||
typedef struct nv_uuid
|
||||
{
|
||||
NvU8 uuid[NV_UUID_LEN];
|
||||
|
||||
} NvUuid;
|
||||
|
||||
#define NV_UUID_HI(pUuid) (*((NvU64*)((pUuid)->uuid + (NV_UUID_LEN >> 1))))
|
||||
#define NV_UUID_LO(pUuid) (*((NvU64*)((pUuid)->uuid + 0)))
|
||||
|
||||
typedef NvUuid NvSystemUuid;
|
||||
|
||||
typedef NvUuid NvProcessorUuid;
|
||||
|
||||
extern const NvProcessorUuid NV_PROCESSOR_UUID_CPU_DEFAULT;
|
||||
|
||||
#endif // _NV_CPU_UUID_H_
|
||||
34
nvdisplay/kernel-open/common/inc/nv_firmware_types.h
Normal file
34
nvdisplay/kernel-open/common/inc/nv_firmware_types.h
Normal file
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef NV_FIRMWARE_TYPES_H
|
||||
#define NV_FIRMWARE_TYPES_H
|
||||
|
||||
typedef enum {
|
||||
NV_FIRMWARE_MODE_DISABLED = 0,
|
||||
NV_FIRMWARE_MODE_ENABLED = 1,
|
||||
NV_FIRMWARE_MODE_DEFAULT = 2,
|
||||
NV_FIRMWARE_MODE_INVALID = 0xFF
|
||||
} NvFirmwareMode;
|
||||
|
||||
#endif // NV_FIRMWARE_TYPES_H
|
||||
227
nvdisplay/kernel-open/common/inc/nv_speculation_barrier.h
Normal file
227
nvdisplay/kernel-open/common/inc/nv_speculation_barrier.h
Normal file
@@ -0,0 +1,227 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2018 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* NVIDIA GPZ vulnerability mitigation definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* There are two copies of this file for legacy reasons:
|
||||
*
|
||||
* P4: <$NV_SOURCE/>drivers/common/inc/nv_speculation_barrier.h
|
||||
* Git: <tegra/core/>include/nv_speculation_barrier.h
|
||||
*
|
||||
* Both files need to be kept in sync if any changes are required.
|
||||
*/
|
||||
|
||||
#ifndef _NV_SPECULATION_BARRIER_H_
|
||||
#define _NV_SPECULATION_BARRIER_H_
|
||||
|
||||
#define NV_SPECULATION_BARRIER_VERSION 2
|
||||
|
||||
/*
|
||||
* GNU-C/MSC/clang - x86/x86_64 : x86_64, __i386, __i386__
|
||||
* GNU-C - THUMB mode : __GNUC__, __thumb__
|
||||
* GNU-C - ARM modes : __GNUC__, __arm__, __aarch64__
|
||||
* armclang - THUMB mode : __ARMCC_VERSION, __thumb__
|
||||
* armclang - ARM modes : __ARMCC_VERSION, __arm__, __aarch64__
|
||||
* GHS - THUMB mode : __ghs__, __THUMB__
|
||||
* GHS - ARM modes : __ghs__, __ARM__, __ARM64__
|
||||
*/
|
||||
|
||||
#if defined(_M_IX86) || defined(__i386__) || defined(__i386) \
|
||||
|| defined(__x86_64) || defined(AMD64) || defined(_M_AMD64)
|
||||
/* All x86 */
|
||||
#define NV_SPECULATION_BARRIER_x86
|
||||
|
||||
#elif defined(macintosh) || defined(__APPLE__) \
|
||||
|| defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) \
|
||||
|| defined(__POWERPC__) || defined(__ppc) || defined(__ppc__) \
|
||||
|| defined(__ppc64__) || defined(__PPC__) \
|
||||
|| defined(__PPC64__) || defined(_ARCH_PPC) || defined(_ARCH_PPC64)
|
||||
/* All PowerPC */
|
||||
#define NV_SPECULATION_BARRIER_PPC
|
||||
|
||||
#elif (defined(__GNUC__) && defined(__thumb__)) \
|
||||
|| (defined(__ARMCC_VERSION) && defined(__thumb__)) \
|
||||
|| (defined(__ghs__) && defined(__THUMB__))
|
||||
/* ARM-thumb mode(<=ARMv7)/T32 (ARMv8) */
|
||||
#define NV_SPECULATION_BARRIER_ARM_COMMON
|
||||
#define NV_SPEC_BARRIER_CSDB ".inst.w 0xf3af8014\n"
|
||||
|
||||
#elif (defined(__GNUC__) && defined(__arm__)) \
|
||||
|| (defined(__ARMCC_VERSION) && defined(__arm__)) \
|
||||
|| (defined(__ghs__) && defined(__ARM__))
|
||||
/* aarch32(ARMv8) / arm(<=ARMv7) mode */
|
||||
#define NV_SPECULATION_BARRIER_ARM_COMMON
|
||||
#define NV_SPEC_BARRIER_CSDB ".inst 0xe320f014\n"
|
||||
|
||||
#elif (defined(__GNUC__) && defined(__aarch64__)) \
|
||||
|| (defined(__ARMCC_VERSION) && defined(__aarch64__)) \
|
||||
|| (defined(__ghs__) && defined(__ARM64__))
|
||||
/* aarch64(ARMv8) mode */
|
||||
#define NV_SPECULATION_BARRIER_ARM_COMMON
|
||||
#define NV_SPEC_BARRIER_CSDB "HINT #20\n"
|
||||
#elif (defined(_MSC_VER) && ( defined(_M_ARM64) || defined(_M_ARM)) )
|
||||
/* Not currently implemented for MSVC/ARM64. See bug 3366890. */
|
||||
# define nv_speculation_barrier()
|
||||
# define speculation_barrier() nv_speculation_barrier()
|
||||
#elif defined(NVCPU_NVRISCV64) && NVOS_IS_LIBOS
|
||||
# define nv_speculation_barrier()
|
||||
#else
|
||||
#error "Unknown compiler/chip family"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* nv_speculation_barrier -- General-purpose speculation barrier
|
||||
*
|
||||
* This approach provides full protection against variant-1 vulnerability.
|
||||
* However, the recommended approach is detailed below (See:
|
||||
* nv_array_index_no_speculate)
|
||||
*
|
||||
* Semantics:
|
||||
* Any memory read that is sequenced after a nv_speculation_barrier(),
|
||||
* and contained directly within the scope of nv_speculation_barrier() or
|
||||
* directly within a nested scope, will not speculatively execute until all
|
||||
* conditions for entering that scope have been architecturally resolved.
|
||||
*
|
||||
* Example:
|
||||
* if (untrusted_index_from_user < bound) {
|
||||
* ...
|
||||
* nv_speculation_barrier();
|
||||
* ...
|
||||
* x = array1[untrusted_index_from_user];
|
||||
* bit = x & 1;
|
||||
* y = array2[0x100 * bit];
|
||||
* }
|
||||
*/
|
||||
|
||||
#if defined(NV_SPECULATION_BARRIER_x86)
|
||||
// Delete after all references are changed to nv_speculation_barrier
|
||||
#define speculation_barrier() nv_speculation_barrier()
|
||||
|
||||
static inline void nv_speculation_barrier(void)
|
||||
{
|
||||
|
||||
#if defined(_MSC_VER) && !defined(__clang__)
|
||||
_mm_lfence();
|
||||
#endif
|
||||
|
||||
#if defined(__GNUC__) || defined(__clang__)
|
||||
__asm__ __volatile__ ("lfence" : : : "memory");
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#elif defined(NV_SPECULATION_BARRIER_PPC)
|
||||
|
||||
static inline void nv_speculation_barrier(void)
|
||||
{
|
||||
asm volatile("ori 31,31,0");
|
||||
}
|
||||
|
||||
#elif defined(NV_SPECULATION_BARRIER_ARM_COMMON)
|
||||
|
||||
/* Note: Cortex-A9 GNU-assembler seems to complain about DSB SY */
|
||||
#define nv_speculation_barrier() \
|
||||
asm volatile \
|
||||
( \
|
||||
"DSB sy\n" \
|
||||
"ISB\n" \
|
||||
: : : "memory" \
|
||||
)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* nv_array_index_no_speculate -- Recommended variant-1 mitigation approach
|
||||
*
|
||||
* The array-index-no-speculate approach "de-speculates" an array index that
|
||||
* has already been bounds-checked.
|
||||
*
|
||||
* This approach is preferred over nv_speculation_barrier due to the following
|
||||
* reasons:
|
||||
* - It is just as effective as the general-purpose speculation barrier.
|
||||
* - It clearly identifies what array index is being de-speculated and is thus
|
||||
* self-commenting, whereas the general-purpose speculation barrier requires
|
||||
* an explanation of what array index is being de-speculated.
|
||||
* - It performs substantially better than the general-purpose speculation
|
||||
* barrier on ARM Cortex-A cores (the difference is expected to be tens of
|
||||
* cycles per invocation). Within tight loops, this difference may become
|
||||
* noticeable.
|
||||
*
|
||||
* Semantics:
|
||||
* Provided count is non-zero and the caller has already validated or otherwise
|
||||
* established that index < count, any speculative use of the return value will
|
||||
* use a speculative value that is less than count.
|
||||
*
|
||||
* Example:
|
||||
* if (untrusted_index_from_user < bound) {
|
||||
* untrusted_index_from_user = nv_array_index_no_speculate(
|
||||
* untrusted_index_from_user, bound);
|
||||
* ...
|
||||
* x = array1[untrusted_index_from_user];
|
||||
* ...
|
||||
* }
|
||||
*
|
||||
* The use of nv_array_index_no_speculate() in the above example ensures that
|
||||
* subsequent uses of untrusted_index_from_user will not execute speculatively
|
||||
* (they will wait for the bounds check to complete).
|
||||
*/
|
||||
|
||||
static inline unsigned long nv_array_index_no_speculate(unsigned long index,
|
||||
unsigned long count)
|
||||
{
|
||||
#if defined(NV_SPECULATION_BARRIER_x86) && (defined(__GNUC__) || defined(__clang__))
|
||||
unsigned long mask;
|
||||
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"CMP %2, %1 \n"
|
||||
"SBB %0, %0 \n"
|
||||
: "=r"(mask) : "r"(index), "r"(count) : "cc"
|
||||
);
|
||||
|
||||
return (index & mask);
|
||||
|
||||
#elif defined(NV_SPECULATION_BARRIER_ARM_COMMON)
|
||||
unsigned long mask;
|
||||
|
||||
asm volatile
|
||||
(
|
||||
"CMP %[ind], %[cnt] \n"
|
||||
"SBC %[res], %[cnt], %[cnt] \n"
|
||||
NV_SPEC_BARRIER_CSDB
|
||||
: [res] "=r" (mask) : [ind] "r" (index), [cnt] "r" (count): "cc"
|
||||
);
|
||||
|
||||
return (index & mask);
|
||||
|
||||
/* Fallback to generic speculation barrier for unsupported platforms */
|
||||
#else
|
||||
nv_speculation_barrier();
|
||||
|
||||
return index;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif //_NV_SPECULATION_BARRIER_H_
|
||||
39
nvdisplay/kernel-open/common/inc/nv_stdarg.h
Normal file
39
nvdisplay/kernel-open/common/inc/nv_stdarg.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _NV_STDARG_H_
|
||||
#define _NV_STDARG_H_
|
||||
|
||||
#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX)
|
||||
#include "conftest.h"
|
||||
#if defined(NV_LINUX_STDARG_H_PRESENT)
|
||||
#include <linux/stdarg.h>
|
||||
#else
|
||||
#include <stdarg.h>
|
||||
#endif
|
||||
#else
|
||||
#include <stdarg.h>
|
||||
#endif
|
||||
|
||||
#endif // _NV_STDARG_H_
|
||||
1520
nvdisplay/kernel-open/common/inc/nv_uvm_interface.h
Normal file
1520
nvdisplay/kernel-open/common/inc/nv_uvm_interface.h
Normal file
File diff suppressed because it is too large
Load Diff
964
nvdisplay/kernel-open/common/inc/nv_uvm_types.h
Normal file
964
nvdisplay/kernel-open/common/inc/nv_uvm_types.h
Normal file
@@ -0,0 +1,964 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// This file provides common types for both UVM driver and RM's UVM interface.
|
||||
//
|
||||
|
||||
#ifndef _NV_UVM_TYPES_H_
|
||||
#define _NV_UVM_TYPES_H_
|
||||
|
||||
#include "nvtypes.h"
|
||||
#include "nvstatus.h"
|
||||
#include "nvgputypes.h"
|
||||
#include "nvCpuUuid.h"
|
||||
|
||||
|
||||
//
|
||||
// Default Page Size if left "0" because in RM BIG page size is default & there
|
||||
// are multiple BIG page sizes in RM. These defines are used as flags to "0"
|
||||
// should be OK when user is not sure which pagesize allocation it wants
|
||||
//
|
||||
#define UVM_PAGE_SIZE_DEFAULT 0x0
|
||||
#define UVM_PAGE_SIZE_4K 0x1000
|
||||
#define UVM_PAGE_SIZE_64K 0x10000
|
||||
#define UVM_PAGE_SIZE_128K 0x20000
|
||||
#define UVM_PAGE_SIZE_2M 0x200000
|
||||
#define UVM_PAGE_SIZE_512M 0x20000000
|
||||
|
||||
//
|
||||
// When modifying flags, make sure they are compatible with the mirrored
|
||||
// PMA_* flags in phys_mem_allocator.h.
|
||||
//
|
||||
// Input flags
|
||||
#define UVM_PMA_ALLOCATE_DONT_EVICT NVBIT(0)
|
||||
#define UVM_PMA_ALLOCATE_PINNED NVBIT(1)
|
||||
#define UVM_PMA_ALLOCATE_SPECIFY_MINIMUM_SPEED NVBIT(2)
|
||||
#define UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE NVBIT(3)
|
||||
#define UVM_PMA_ALLOCATE_SPECIFY_REGION_ID NVBIT(4)
|
||||
#define UVM_PMA_ALLOCATE_PREFER_SLOWEST NVBIT(5)
|
||||
#define UVM_PMA_ALLOCATE_CONTIGUOUS NVBIT(6)
|
||||
#define UVM_PMA_ALLOCATE_PERSISTENT NVBIT(7)
|
||||
#define UVM_PMA_ALLOCATE_PROTECTED_REGION NVBIT(8)
|
||||
#define UVM_PMA_ALLOCATE_FORCE_ALIGNMENT NVBIT(9)
|
||||
#define UVM_PMA_ALLOCATE_NO_ZERO NVBIT(10)
|
||||
#define UVM_PMA_ALLOCATE_TURN_BLACKLIST_OFF NVBIT(11)
|
||||
#define UVM_PMA_ALLOCATE_ALLOW_PARTIAL NVBIT(12)
|
||||
|
||||
// Output flags
|
||||
#define UVM_PMA_ALLOCATE_RESULT_IS_ZERO NVBIT(0)
|
||||
|
||||
// Input flags to pmaFree
|
||||
#define UVM_PMA_FREE_IS_ZERO NVBIT(0)
|
||||
|
||||
//
|
||||
// Indicate that the PMA operation is being done from one of the PMA eviction
|
||||
// callbacks.
|
||||
//
|
||||
// Notably this flag is currently used only by the UVM/RM interface and not
|
||||
// mirrored in PMA.
|
||||
//
|
||||
#define UVM_PMA_CALLED_FROM_PMA_EVICTION 16384
|
||||
|
||||
#define UVM_UUID_LEN 16
|
||||
#define UVM_SW_OBJ_SUBCHANNEL 5
|
||||
|
||||
typedef unsigned long long UvmGpuPointer;
|
||||
|
||||
//
|
||||
// The following typedefs serve to explain the resources they point to.
|
||||
// The actual resources remain RM internal and not exposed.
|
||||
//
|
||||
typedef struct uvmGpuSession_tag *uvmGpuSessionHandle; // gpuSessionHandle
|
||||
typedef struct uvmGpuDevice_tag *uvmGpuDeviceHandle; // gpuDeviceHandle
|
||||
typedef struct uvmGpuAddressSpace_tag *uvmGpuAddressSpaceHandle; // gpuAddressSpaceHandle
|
||||
typedef struct uvmGpuChannel_tag *uvmGpuChannelHandle; // gpuChannelHandle
|
||||
typedef struct uvmGpuCopyEngine_tag *uvmGpuCopyEngineHandle; // gpuObjectHandle
|
||||
|
||||
typedef struct UvmGpuMemoryInfo_tag
|
||||
{
|
||||
// Out: Memory layout.
|
||||
NvU32 kind;
|
||||
|
||||
// Out: Set to TRUE, if the allocation is in sysmem.
|
||||
NvBool sysmem;
|
||||
|
||||
// Out: Set to TRUE, if the allocation is a constructed
|
||||
// under a Device or Subdevice.
|
||||
// All permutations of sysmem and deviceDescendant are valid.
|
||||
// !sysmem && !deviceDescendant implies a fabric allocation.
|
||||
NvBool deviceDescendant;
|
||||
|
||||
// Out: Page size associated with the phys alloc.
|
||||
NvU32 pageSize;
|
||||
|
||||
// Out: Set to TRUE, if the allocation is contiguous.
|
||||
NvBool contig;
|
||||
|
||||
// Out: Starting Addr if the allocation is contiguous.
|
||||
// This is only valid if contig is NV_TRUE.
|
||||
NvU64 physAddr;
|
||||
|
||||
// Out: Total size of the allocation.
|
||||
NvU64 size;
|
||||
|
||||
// Out: Uuid of the GPU to which the allocation belongs.
|
||||
// This is only valid if deviceDescendant is NV_TRUE.
|
||||
// Note: If the allocation is owned by a device in
|
||||
// an SLI group and the allocation is broadcast
|
||||
// across the SLI group, this UUID will be any one
|
||||
// of the subdevices in the SLI group.
|
||||
NvProcessorUuid uuid;
|
||||
} UvmGpuMemoryInfo;
|
||||
|
||||
// Some resources must share the same virtual mappings across channels. A mapped
|
||||
// resource must be shared by a channel iff:
|
||||
//
|
||||
// 1) The channel belongs to a TSG (UvmGpuChannelInstanceInfo::bTsgChannel is
|
||||
// NV_TRUE).
|
||||
//
|
||||
// 2) The channel is in the same TSG as all other channels sharing that mapping
|
||||
// (UvmGpuChannelInstanceInfo::tsgId matches among channels).
|
||||
//
|
||||
// 3) The channel is in the same GPU address space as the other channels
|
||||
// sharing that mapping.
|
||||
//
|
||||
// 4) The resource handle(s) match those of the shared mapping
|
||||
// (UvmGpuChannelResourceInfo::resourceDescriptor and
|
||||
// UvmGpuChannelResourceInfo::resourceId).
|
||||
typedef struct UvmGpuChannelResourceInfo_tag
|
||||
{
|
||||
// Out: Ptr to the RM memDesc of the channel resource.
|
||||
NvP64 resourceDescriptor;
|
||||
|
||||
// Out: RM ID of the channel resource.
|
||||
NvU32 resourceId;
|
||||
|
||||
// Out: Alignment needed for the resource allocation.
|
||||
NvU64 alignment;
|
||||
|
||||
// Out: Info about the resource allocation.
|
||||
UvmGpuMemoryInfo resourceInfo;
|
||||
} UvmGpuChannelResourceInfo;
|
||||
|
||||
typedef struct UvmGpuPagingChannelInfo_tag
|
||||
{
|
||||
// Pointer to a shadown buffer mirroring the contents of the error notifier
|
||||
// for the paging channel
|
||||
NvNotification *shadowErrorNotifier;
|
||||
} UvmGpuPagingChannelInfo;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_GPU_CHANNEL_ENGINE_TYPE_GR = 1,
|
||||
UVM_GPU_CHANNEL_ENGINE_TYPE_CE = 2,
|
||||
UVM_GPU_CHANNEL_ENGINE_TYPE_SEC2 = 3,
|
||||
} UVM_GPU_CHANNEL_ENGINE_TYPE;
|
||||
|
||||
#define UVM_GPU_CHANNEL_MAX_RESOURCES 13
|
||||
|
||||
typedef struct UvmGpuChannelInstanceInfo_tag
|
||||
{
|
||||
// Out: Starting address of the channel instance.
|
||||
NvU64 base;
|
||||
|
||||
// Out: Set to NV_TRUE, if the instance is in sysmem.
|
||||
// Set to NV_FALSE, if the instance is in vidmem.
|
||||
NvBool sysmem;
|
||||
|
||||
// Out: Hardware runlist ID.
|
||||
NvU32 runlistId;
|
||||
|
||||
// Out: Hardware channel ID.
|
||||
NvU32 chId;
|
||||
|
||||
// Out: NV_TRUE if the channel belongs to a subcontext or NV_FALSE if it
|
||||
// belongs to a regular context.
|
||||
NvBool bInSubctx;
|
||||
|
||||
// Out: ID of the subcontext to which the channel belongs.
|
||||
NvU32 subctxId;
|
||||
|
||||
// Out: Whether the channel belongs to a TSG or not
|
||||
NvBool bTsgChannel;
|
||||
|
||||
// Out: ID of the TSG to which the channel belongs
|
||||
NvU32 tsgId;
|
||||
|
||||
// Out: Maximum number of subcontexts in the TSG to which the channel belongs
|
||||
NvU32 tsgMaxSubctxCount;
|
||||
|
||||
// Out: Info of channel resources associated with the channel.
|
||||
UvmGpuChannelResourceInfo resourceInfo[UVM_GPU_CHANNEL_MAX_RESOURCES];
|
||||
|
||||
// Out: Number of valid entries in resourceInfo array.
|
||||
NvU32 resourceCount;
|
||||
|
||||
// Out: Type of the engine the channel is bound to
|
||||
NvU32 channelEngineType;
|
||||
|
||||
// Out: Channel handle to be used in the CLEAR_FAULTED method
|
||||
NvU32 clearFaultedToken;
|
||||
|
||||
// Out: Address of the NV_CHRAM_CHANNEL register required to clear the
|
||||
// ENG_FAULTED/PBDMA_FAULTED bits after servicing non-replayable faults on
|
||||
// Ampere+ GPUs
|
||||
volatile NvU32 *pChramChannelRegister;
|
||||
|
||||
// Out: Address of the Runlist PRI Base Register required to ring the
|
||||
// doorbell after clearing the faulted bit.
|
||||
volatile NvU32 *pRunlistPRIBaseRegister;
|
||||
|
||||
// Out: SMC engine id to which the GR channel is bound, or zero if the GPU
|
||||
// does not support SMC or it is a CE channel
|
||||
NvU32 smcEngineId;
|
||||
|
||||
// Out: Start of the VEID range assigned to the SMC engine the GR channel
|
||||
// is bound to, or zero if the GPU does not support SMC or it is a CE
|
||||
// channel
|
||||
NvU32 smcEngineVeIdOffset;
|
||||
} UvmGpuChannelInstanceInfo;
|
||||
|
||||
typedef struct UvmGpuChannelResourceBindParams_tag
|
||||
{
|
||||
// In: RM ID of the channel resource.
|
||||
NvU32 resourceId;
|
||||
|
||||
// In: Starting VA at which the channel resource is mapped.
|
||||
NvU64 resourceVa;
|
||||
} UvmGpuChannelResourceBindParams;
|
||||
|
||||
typedef struct UvmGpuChannelInfo_tag
|
||||
{
|
||||
volatile unsigned *gpGet;
|
||||
volatile unsigned *gpPut;
|
||||
UvmGpuPointer *gpFifoEntries;
|
||||
unsigned numGpFifoEntries;
|
||||
unsigned channelClassNum;
|
||||
|
||||
// The errorNotifier is filled out when the channel hits an RC error.
|
||||
NvNotification *errorNotifier;
|
||||
|
||||
NvU32 hwRunlistId;
|
||||
NvU32 hwChannelId;
|
||||
|
||||
volatile unsigned *dummyBar1Mapping;
|
||||
|
||||
// These values are filled by nvUvmInterfaceCopyEngineAlloc. The work
|
||||
// submission token requires the channel to be bound to a runlist and that
|
||||
// happens after CE allocation.
|
||||
volatile NvU32 *workSubmissionOffset;
|
||||
|
||||
// To be deprecated. See pWorkSubmissionToken below.
|
||||
NvU32 workSubmissionToken;
|
||||
|
||||
//
|
||||
// This is the memory location where the most recently updated work
|
||||
// submission token for this channel will be written to. After submitting
|
||||
// new work and updating GP_PUT with the appropriate fence, the token must
|
||||
// be read from this location before writing it to the workSubmissionOffset
|
||||
// to kick off the new work.
|
||||
//
|
||||
volatile NvU32 *pWorkSubmissionToken;
|
||||
} UvmGpuChannelInfo;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
// This value must be passed by Pascal and pre-Pascal GPUs for those
|
||||
// allocations for which a specific location cannot be enforced.
|
||||
UVM_BUFFER_LOCATION_DEFAULT = 0,
|
||||
|
||||
UVM_BUFFER_LOCATION_SYS = 1,
|
||||
UVM_BUFFER_LOCATION_VID = 2,
|
||||
} UVM_BUFFER_LOCATION;
|
||||
|
||||
typedef struct UvmGpuChannelAllocParams_tag
|
||||
{
|
||||
NvU32 numGpFifoEntries;
|
||||
|
||||
// The next two fields store UVM_BUFFER_LOCATION values
|
||||
NvU32 gpFifoLoc;
|
||||
NvU32 gpPutLoc;
|
||||
|
||||
// Index of the engine the channel will be bound to
|
||||
// ignored if engineType is anything other than UVM_GPU_CHANNEL_ENGINE_TYPE_CE
|
||||
NvU32 engineIndex;
|
||||
|
||||
// interpreted as UVM_GPU_CHANNEL_ENGINE_TYPE
|
||||
NvU32 engineType;
|
||||
} UvmGpuChannelAllocParams;
|
||||
|
||||
typedef struct UvmGpuPagingChannelAllocParams_tag
|
||||
{
|
||||
// Index of the LCE engine the channel will be bound to, a zero-based offset
|
||||
// from NV2080_ENGINE_TYPE_COPY0.
|
||||
NvU32 engineIndex;
|
||||
} UvmGpuPagingChannelAllocParams;
|
||||
|
||||
// The max number of Copy Engines supported by a GPU.
|
||||
// The gpu ops build has a static assert that this is the correct number.
|
||||
#define UVM_COPY_ENGINE_COUNT_MAX 10
|
||||
|
||||
typedef struct
|
||||
{
|
||||
// True if the CE is supported at all
|
||||
NvBool supported:1;
|
||||
|
||||
// True if the CE is synchronous with GR
|
||||
NvBool grce:1;
|
||||
|
||||
// True if the CE shares physical CEs with any other CE
|
||||
//
|
||||
// The value returned by RM for this field may change when a GPU is
|
||||
// registered with RM for the first time, so UVM needs to query it
|
||||
// again each time a GPU is registered.
|
||||
NvBool shared:1;
|
||||
|
||||
// True if the CE can give enhanced performance for SYSMEM reads over other CEs
|
||||
NvBool sysmemRead:1;
|
||||
|
||||
// True if the CE can give enhanced performance for SYSMEM writes over other CEs
|
||||
NvBool sysmemWrite:1;
|
||||
|
||||
// True if the CE can be used for SYSMEM transactions
|
||||
NvBool sysmem:1;
|
||||
|
||||
// True if the CE can be used for P2P transactions using NVLINK
|
||||
NvBool nvlinkP2p:1;
|
||||
|
||||
// True if the CE can be used for P2P transactions
|
||||
NvBool p2p:1;
|
||||
|
||||
// Mask of physical CEs assigned to this LCE
|
||||
//
|
||||
// The value returned by RM for this field may change when a GPU is
|
||||
// registered with RM for the first time, so UVM needs to query it
|
||||
// again each time a GPU is registered.
|
||||
NvU32 cePceMask;
|
||||
} UvmGpuCopyEngineCaps;
|
||||
|
||||
typedef struct UvmGpuCopyEnginesCaps_tag
|
||||
{
|
||||
// Supported CEs may not be contiguous
|
||||
UvmGpuCopyEngineCaps copyEngineCaps[UVM_COPY_ENGINE_COUNT_MAX];
|
||||
} UvmGpuCopyEnginesCaps;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_LINK_TYPE_NONE,
|
||||
UVM_LINK_TYPE_PCIE,
|
||||
UVM_LINK_TYPE_NVLINK_1,
|
||||
UVM_LINK_TYPE_NVLINK_2,
|
||||
UVM_LINK_TYPE_NVLINK_3,
|
||||
|
||||
|
||||
|
||||
|
||||
} UVM_LINK_TYPE;
|
||||
|
||||
typedef struct UvmGpuCaps_tag
|
||||
{
|
||||
NvU32 sysmemLink; // UVM_LINK_TYPE
|
||||
NvU32 sysmemLinkRateMBps; // See UvmGpuP2PCapsParams::totalLinkLineRateMBps
|
||||
NvBool numaEnabled;
|
||||
NvU32 numaNodeId;
|
||||
|
||||
// On ATS systems, GPUs connected to different CPU sockets can have peer
|
||||
// traffic. They are called indirect peers. However, indirect peers are
|
||||
// mapped using sysmem aperture. In order to disambiguate the location of a
|
||||
// specific memory address, each GPU maps its memory to a different window
|
||||
// in the System Physical Address (SPA) space. The following fields contain
|
||||
// the base + size of such window for the GPU. systemMemoryWindowSize
|
||||
// different than 0 indicates that the window is valid.
|
||||
//
|
||||
// - If the window is valid, then we can map GPU memory to the CPU as
|
||||
// cache-coherent by adding the GPU address to the window start.
|
||||
// - If numaEnabled is NV_TRUE, then we can also convert the system
|
||||
// addresses of allocated GPU memory to struct pages.
|
||||
//
|
||||
// TODO: Bug 1986868: fix window start computation for SIMICS
|
||||
NvU64 systemMemoryWindowStart;
|
||||
NvU64 systemMemoryWindowSize;
|
||||
|
||||
// This tells if the GPU is connected to NVSwitch. On systems with NVSwitch
|
||||
// all GPUs are connected to it. If connectedToSwitch is NV_TRUE,
|
||||
// nvswitchMemoryWindowStart tells the base address for the GPU in the
|
||||
// NVSwitch address space. It is used when creating PTEs of memory mappings
|
||||
// to NVSwitch peers.
|
||||
NvBool connectedToSwitch;
|
||||
NvU64 nvswitchMemoryWindowStart;
|
||||
} UvmGpuCaps;
|
||||
|
||||
typedef struct UvmGpuAddressSpaceInfo_tag
|
||||
{
|
||||
NvU32 bigPageSize;
|
||||
|
||||
NvBool atsEnabled;
|
||||
|
||||
// Mapped registers that contain the current GPU time
|
||||
volatile NvU32 *time0Offset;
|
||||
volatile NvU32 *time1Offset;
|
||||
|
||||
// Maximum number of subcontexts supported under this GPU address space
|
||||
NvU32 maxSubctxCount;
|
||||
|
||||
NvBool smcEnabled;
|
||||
|
||||
NvU32 smcSwizzId;
|
||||
|
||||
NvU32 smcGpcCount;
|
||||
} UvmGpuAddressSpaceInfo;
|
||||
|
||||
typedef struct UvmGpuAllocInfo_tag
|
||||
{
|
||||
NvU64 gpuPhysOffset; // Returns gpuPhysOffset if contiguous requested
|
||||
NvU32 pageSize; // default is RM big page size - 64K or 128 K" else use 4K or 2M
|
||||
NvU64 alignment; // Virtual alignment
|
||||
NvBool bContiguousPhysAlloc; // Flag to request contiguous physical allocation
|
||||
NvBool bMemGrowsDown; // Causes RM to reserve physical heap from top of FB
|
||||
NvBool bPersistentVidmem; // Causes RM to allocate persistent video memory
|
||||
NvHandle hPhysHandle; // Handle for phys allocation either provided or retrieved
|
||||
|
||||
NvBool bUnprotected; // Allocation to be made in unprotected memory whenever
|
||||
// SEV or GPU CC modes are enabled. Ignored otherwise
|
||||
|
||||
} UvmGpuAllocInfo;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_VIRT_MODE_NONE = 0, // Baremetal or passthrough virtualization
|
||||
UVM_VIRT_MODE_LEGACY = 1, // Virtualization without SRIOV support
|
||||
UVM_VIRT_MODE_SRIOV_HEAVY = 2, // Virtualization with SRIOV Heavy configured
|
||||
UVM_VIRT_MODE_SRIOV_STANDARD = 3, // Virtualization with SRIOV Standard configured
|
||||
UVM_VIRT_MODE_COUNT = 4,
|
||||
} UVM_VIRT_MODE;
|
||||
|
||||
// !!! The following enums (with UvmRm prefix) are defined and documented in
|
||||
// mm/uvm/interface/uvm_types.h and must be mirrored. Please refer to that file
|
||||
// for more details.
|
||||
|
||||
// UVM GPU mapping types
|
||||
typedef enum
|
||||
{
|
||||
UvmRmGpuMappingTypeDefault = 0,
|
||||
UvmRmGpuMappingTypeReadWriteAtomic = 1,
|
||||
UvmRmGpuMappingTypeReadWrite = 2,
|
||||
UvmRmGpuMappingTypeReadOnly = 3,
|
||||
UvmRmGpuMappingTypeCount = 4
|
||||
} UvmRmGpuMappingType;
|
||||
|
||||
// UVM GPU caching types
|
||||
typedef enum
|
||||
{
|
||||
UvmRmGpuCachingTypeDefault = 0,
|
||||
UvmRmGpuCachingTypeForceUncached = 1,
|
||||
UvmRmGpuCachingTypeForceCached = 2,
|
||||
UvmRmGpuCachingTypeCount = 3
|
||||
} UvmRmGpuCachingType;
|
||||
|
||||
// UVM GPU format types
|
||||
typedef enum {
|
||||
UvmRmGpuFormatTypeDefault = 0,
|
||||
UvmRmGpuFormatTypeBlockLinear = 1,
|
||||
UvmRmGpuFormatTypeCount = 2
|
||||
} UvmRmGpuFormatType;
|
||||
|
||||
// UVM GPU Element bits types
|
||||
typedef enum {
|
||||
UvmRmGpuFormatElementBitsDefault = 0,
|
||||
UvmRmGpuFormatElementBits8 = 1,
|
||||
UvmRmGpuFormatElementBits16 = 2,
|
||||
// Cuda does not support 24-bit width
|
||||
UvmRmGpuFormatElementBits32 = 4,
|
||||
UvmRmGpuFormatElementBits64 = 5,
|
||||
UvmRmGpuFormatElementBits128 = 6,
|
||||
UvmRmGpuFormatElementBitsCount = 7
|
||||
} UvmRmGpuFormatElementBits;
|
||||
|
||||
// UVM GPU Compression types
|
||||
typedef enum {
|
||||
UvmRmGpuCompressionTypeDefault = 0,
|
||||
UvmRmGpuCompressionTypeEnabledNoPlc = 1,
|
||||
UvmRmGpuCompressionTypeCount = 2
|
||||
} UvmRmGpuCompressionType;
|
||||
|
||||
typedef struct UvmGpuExternalMappingInfo_tag
|
||||
{
|
||||
// In: GPU caching ability.
|
||||
UvmRmGpuCachingType cachingType;
|
||||
|
||||
// In: Virtual permissions.
|
||||
UvmRmGpuMappingType mappingType;
|
||||
|
||||
// In: RM virtual mapping memory format
|
||||
UvmRmGpuFormatType formatType;
|
||||
|
||||
// In: RM virtual mapping element bits
|
||||
UvmRmGpuFormatElementBits elementBits;
|
||||
|
||||
// In: RM virtual compression type
|
||||
UvmRmGpuCompressionType compressionType;
|
||||
|
||||
// In: Size of the buffer to store PTEs (in bytes).
|
||||
NvU64 pteBufferSize;
|
||||
|
||||
// In: Pointer to a buffer to store PTEs.
|
||||
// Out: The interface will fill the buffer with PTEs
|
||||
NvU64 *pteBuffer;
|
||||
|
||||
// Out: Number of PTEs filled in to the buffer.
|
||||
NvU64 numWrittenPtes;
|
||||
|
||||
// Out: Number of PTEs remaining to be filled
|
||||
// if the buffer is not sufficient to accommodate
|
||||
// requested PTEs.
|
||||
NvU64 numRemainingPtes;
|
||||
|
||||
// Out: PTE size (in bytes)
|
||||
NvU32 pteSize;
|
||||
} UvmGpuExternalMappingInfo;
|
||||
|
||||
typedef struct UvmGpuP2PCapsParams_tag
|
||||
{
|
||||
// Out: peerId[i] contains gpu[i]'s peer id of gpu[1 - i]. Only defined if
|
||||
// the GPUs are direct peers.
|
||||
NvU32 peerIds[2];
|
||||
|
||||
// Out: UVM_LINK_TYPE
|
||||
NvU32 p2pLink;
|
||||
|
||||
// Out: optimalNvlinkWriteCEs[i] contains gpu[i]'s optimal CE for writing to
|
||||
// gpu[1 - i]. The CE indexes are valid only if the GPUs are NVLink peers.
|
||||
//
|
||||
// The value returned by RM for this field may change when a GPU is
|
||||
// registered with RM for the first time, so UVM needs to query it again
|
||||
// each time a GPU is registered.
|
||||
NvU32 optimalNvlinkWriteCEs[2];
|
||||
|
||||
// Out: Maximum unidirectional bandwidth between the peers in megabytes per
|
||||
// second, not taking into account the protocols overhead. The reported
|
||||
// bandwidth for indirect peers is zero.
|
||||
NvU32 totalLinkLineRateMBps;
|
||||
|
||||
// Out: True if the peers have a indirect link to communicate. On P9
|
||||
// systems, this is true if peers are connected to different NPUs that
|
||||
// forward the requests between them.
|
||||
NvU32 indirectAccess : 1;
|
||||
} UvmGpuP2PCapsParams;
|
||||
|
||||
// Platform-wide information
|
||||
typedef struct UvmPlatformInfo_tag
|
||||
{
|
||||
// Out: ATS (Address Translation Services) is supported
|
||||
NvBool atsSupported;
|
||||
|
||||
// Out: AMD SEV (Secure Encrypted Virtualization) is enabled
|
||||
NvBool sevEnabled;
|
||||
} UvmPlatformInfo;
|
||||
|
||||
typedef struct UvmGpuClientInfo_tag
|
||||
{
|
||||
NvHandle hClient;
|
||||
|
||||
NvHandle hSmcPartRef;
|
||||
} UvmGpuClientInfo;
|
||||
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_GPU_CONF_COMPUTE_MODE_NONE,
|
||||
UVM_GPU_CONF_COMPUTE_MODE_APM,
|
||||
|
||||
UVM_GPU_CONF_COMPUTE_MODE_HCC,
|
||||
|
||||
UVM_GPU_CONF_COMPUTE_MODE_COUNT
|
||||
} UvmGpuConfComputeMode;
|
||||
|
||||
typedef struct UvmGpuConfComputeCaps_tag
|
||||
{
|
||||
// Out: GPU's confidential compute mode
|
||||
UvmGpuConfComputeMode mode;
|
||||
} UvmGpuConfComputeCaps;
|
||||
|
||||
|
||||
#define UVM_GPU_NAME_LENGTH 0x40
|
||||
|
||||
typedef struct UvmGpuInfo_tag
|
||||
{
|
||||
// Printable gpu name
|
||||
char name[UVM_GPU_NAME_LENGTH];
|
||||
|
||||
// Uuid of this gpu
|
||||
NvProcessorUuid uuid;
|
||||
|
||||
// Gpu architecture; NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_*
|
||||
NvU32 gpuArch;
|
||||
|
||||
// Gpu implementation; NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_*
|
||||
NvU32 gpuImplementation;
|
||||
|
||||
// Host (gpfifo) class; *_CHANNEL_GPFIFO_*, e.g. KEPLER_CHANNEL_GPFIFO_A
|
||||
NvU32 hostClass;
|
||||
|
||||
// Copy engine (dma) class; *_DMA_COPY_*, e.g. KEPLER_DMA_COPY_A
|
||||
NvU32 ceClass;
|
||||
|
||||
// Compute class; *_COMPUTE_*, e.g. KEPLER_COMPUTE_A
|
||||
NvU32 computeClass;
|
||||
|
||||
// Set if GPU supports TCC Mode & is in TCC mode.
|
||||
NvBool gpuInTcc;
|
||||
|
||||
// Number of subdevices in SLI group.
|
||||
NvU32 subdeviceCount;
|
||||
|
||||
// Virtualization mode of this gpu.
|
||||
NvU32 virtMode; // UVM_VIRT_MODE
|
||||
|
||||
// NV_TRUE if this is a simulated/emulated GPU. NV_FALSE, otherwise.
|
||||
NvBool isSimulated;
|
||||
|
||||
// Number of GPCs
|
||||
// If SMC is enabled, this is the currently configured number of GPCs for
|
||||
// the given partition (also see the smcSwizzId field below).
|
||||
NvU32 gpcCount;
|
||||
|
||||
// Maximum number of GPCs; NV_SCAL_LITTER_NUM_GPCS
|
||||
// This number is independent of the partition configuration, and can be
|
||||
// used to conservatively size GPU-global constructs.
|
||||
NvU32 maxGpcCount;
|
||||
|
||||
// Number of TPCs
|
||||
NvU32 tpcCount;
|
||||
|
||||
// Maximum number of TPCs per GPC
|
||||
NvU32 maxTpcPerGpcCount;
|
||||
|
||||
// NV_TRUE if SMC is enabled on this GPU.
|
||||
NvBool smcEnabled;
|
||||
|
||||
// SMC partition ID (unique per GPU); note: valid when first looked up in
|
||||
// nvUvmInterfaceGetGpuInfo(), but not guaranteed to remain valid.
|
||||
// nvUvmInterfaceDeviceCreate() re-verifies the swizzId and fails if it is
|
||||
// no longer valid.
|
||||
NvU32 smcSwizzId;
|
||||
|
||||
UvmGpuClientInfo smcUserClientInfo;
|
||||
|
||||
|
||||
// Confidential Compute capabilities of this GPU
|
||||
UvmGpuConfComputeCaps gpuConfComputeCaps;
|
||||
|
||||
} UvmGpuInfo;
|
||||
|
||||
typedef struct UvmGpuFbInfo_tag
|
||||
{
|
||||
// Max physical address that can be allocated by UVM. This excludes internal
|
||||
// RM regions that are not registered with PMA either.
|
||||
NvU64 maxAllocatableAddress;
|
||||
|
||||
NvU32 heapSize; // RAM in KB available for user allocations
|
||||
NvU32 reservedHeapSize; // RAM in KB reserved for internal RM allocation
|
||||
NvBool bZeroFb; // Zero FB mode enabled.
|
||||
} UvmGpuFbInfo;
|
||||
|
||||
typedef struct UvmGpuEccInfo_tag
|
||||
{
|
||||
unsigned eccMask;
|
||||
unsigned eccOffset;
|
||||
void *eccReadLocation;
|
||||
NvBool *eccErrorNotifier;
|
||||
NvBool bEccEnabled;
|
||||
} UvmGpuEccInfo;
|
||||
|
||||
typedef struct UvmPmaAllocationOptions_tag
|
||||
{
|
||||
NvU32 flags;
|
||||
NvU32 minimumSpeed; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_MININUM_SPEED
|
||||
NvU64 physBegin, physEnd; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_ADDRESS_RANGE
|
||||
NvU32 regionId; // valid if flags & UVM_PMA_ALLOCATE_SPECIFY_REGION_ID
|
||||
NvU64 alignment; // valid if flags & UVM_PMA_ALLOCATE_FORCE_ALIGNMENT
|
||||
NvLength numPagesAllocated; // valid if flags & UVM_PMA_ALLOCATE_ALLOW_PARTIAL
|
||||
|
||||
NvU32 resultFlags; // valid if the allocation function returns NV_OK
|
||||
} UvmPmaAllocationOptions;
|
||||
|
||||
//
|
||||
// Mirrored in PMA (PMA_STATS)
|
||||
//
|
||||
typedef struct UvmPmaStatistics_tag
|
||||
{
|
||||
volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions
|
||||
volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions
|
||||
volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions
|
||||
|
||||
volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory
|
||||
volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory
|
||||
volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory
|
||||
|
||||
} UvmPmaStatistics;
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventSuspend
|
||||
This function will be called by the GPU driver to signal to UVM that the
|
||||
system is about to enter a sleep state. When it is called, the
|
||||
following assumptions/guarantees are valid/made:
|
||||
|
||||
* User channels have been preempted and disabled
|
||||
* UVM channels are still running normally and will continue to do
|
||||
so until after this function returns control
|
||||
* User threads are still running, but can no longer issue system
|
||||
system calls to the GPU driver
|
||||
* Until exit from this function, UVM is allowed to make full use of
|
||||
the GPUs under its control, as well as of the GPU driver
|
||||
|
||||
Upon return from this function, UVM may not access GPUs under its control
|
||||
until the GPU driver calls uvmEventResume(). It may still receive
|
||||
calls to uvmEventIsrTopHalf() during this time, which it should return
|
||||
NV_ERR_NO_INTR_PENDING from. It will not receive any other calls.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventSuspend_t) (void);
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventResume
|
||||
This function will be called by the GPU driver to signal to UVM that the
|
||||
system has exited a previously entered sleep state. When it is called,
|
||||
the following assumptions/guarantees are valid/made:
|
||||
|
||||
* UVM is again allowed to make full use of the GPUs under its
|
||||
control, as well as of the GPU driver
|
||||
* UVM channels are running normally
|
||||
* User channels are still preempted and disabled
|
||||
* User threads are again running, but still cannot issue system
|
||||
calls to the GPU driver, nor submit new work
|
||||
|
||||
Upon return from this function, UVM is expected to be fully functional.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventResume_t) (void);
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventStartDevice
|
||||
This function will be called by the GPU driver once it has finished its
|
||||
initialization to tell the UVM driver that this GPU has come up.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventStartDevice_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventStopDevice
|
||||
This function will be called by the GPU driver to let UVM know that a GPU
|
||||
is going down.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventStopDevice_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
#if defined (_WIN32)
|
||||
/*******************************************************************************
|
||||
uvmEventWddmResetDuringTimeout
|
||||
This function will be called by KMD in a TDR servicing path to unmap channel
|
||||
resources and to destroy channels. This is a Windows specific event.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventWddmResetDuringTimeout_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventWddmRestartAfterTimeout
|
||||
This function will be called by KMD in a TDR servicing path to map channel
|
||||
resources and to create channels. This is a Windows specific event.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventWddmRestartAfterTimeout_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventServiceInterrupt
|
||||
This function gets called from RM's intr service routine when an interrupt
|
||||
to service a page fault is triggered.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventServiceInterrupt_t) (void *pDeviceObject,
|
||||
NvU32 deviceId, NvU32 subdeviceId);
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventIsrTopHalf_t
|
||||
This function will be called by the GPU driver to let UVM know
|
||||
that an interrupt has occurred.
|
||||
|
||||
Returns:
|
||||
NV_OK if the UVM driver handled the interrupt
|
||||
NV_ERR_NO_INTR_PENDING if the interrupt is not for the UVM driver
|
||||
*/
|
||||
#if defined (__linux__)
|
||||
typedef NV_STATUS (*uvmEventIsrTopHalf_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
#else
|
||||
typedef void (*uvmEventIsrTopHalf_t) (void);
|
||||
#endif
|
||||
|
||||
struct UvmOpsUvmEvents
|
||||
{
|
||||
uvmEventSuspend_t suspend;
|
||||
uvmEventResume_t resume;
|
||||
uvmEventStartDevice_t startDevice;
|
||||
uvmEventStopDevice_t stopDevice;
|
||||
uvmEventIsrTopHalf_t isrTopHalf;
|
||||
#if defined (_WIN32)
|
||||
uvmEventWddmResetDuringTimeout_t wddmResetDuringTimeout;
|
||||
uvmEventWddmRestartAfterTimeout_t wddmRestartAfterTimeout;
|
||||
uvmEventServiceInterrupt_t serviceInterrupt;
|
||||
#endif
|
||||
};
|
||||
|
||||
typedef struct UvmGpuFaultInfo_tag
|
||||
{
|
||||
struct
|
||||
{
|
||||
// Register mappings obtained from RM
|
||||
volatile NvU32* pFaultBufferGet;
|
||||
volatile NvU32* pFaultBufferPut;
|
||||
// Note: this variable is deprecated since buffer overflow is not a separate
|
||||
// register from future chips.
|
||||
volatile NvU32* pFaultBufferInfo;
|
||||
volatile NvU32* pPmcIntr;
|
||||
volatile NvU32* pPmcIntrEnSet;
|
||||
volatile NvU32* pPmcIntrEnClear;
|
||||
volatile NvU32* pPrefetchCtrl;
|
||||
NvU32 replayableFaultMask;
|
||||
// fault buffer cpu mapping and size
|
||||
void* bufferAddress;
|
||||
NvU32 bufferSize;
|
||||
} replayable;
|
||||
struct
|
||||
{
|
||||
// Shadow buffer for non-replayable faults on cpu memory. Resman copies
|
||||
// here the non-replayable faults that need to be handled by UVM
|
||||
void* shadowBufferAddress;
|
||||
|
||||
// Execution context for the queue associated with the fault buffer
|
||||
void* shadowBufferContext;
|
||||
|
||||
// Fault buffer size
|
||||
NvU32 bufferSize;
|
||||
|
||||
// Preallocated stack for functions called from the UVM isr top half
|
||||
void *isr_sp;
|
||||
|
||||
// Preallocated stack for functions called from the UVM isr bottom half
|
||||
void *isr_bh_sp;
|
||||
} nonReplayable;
|
||||
NvHandle faultBufferHandle;
|
||||
} UvmGpuFaultInfo;
|
||||
|
||||
typedef struct UvmGpuPagingChannel_tag
|
||||
{
|
||||
struct gpuDevice *device;
|
||||
NvNotification *errorNotifier;
|
||||
NvHandle channelHandle;
|
||||
NvHandle errorNotifierHandle;
|
||||
void *pushStreamSp;
|
||||
} UvmGpuPagingChannel, *UvmGpuPagingChannelHandle;
|
||||
|
||||
typedef struct UvmGpuAccessCntrInfo_tag
|
||||
{
|
||||
// Register mappings obtained from RM
|
||||
// pointer to the Get register for the access counter buffer
|
||||
volatile NvU32* pAccessCntrBufferGet;
|
||||
// pointer to the Put register for the access counter buffer
|
||||
volatile NvU32* pAccessCntrBufferPut;
|
||||
// pointer to the Full register for the access counter buffer
|
||||
volatile NvU32* pAccessCntrBufferFull;
|
||||
// pointer to the hub interrupt
|
||||
volatile NvU32* pHubIntr;
|
||||
// pointer to interrupt enable register
|
||||
volatile NvU32* pHubIntrEnSet;
|
||||
// pointer to interrupt disable register
|
||||
volatile NvU32* pHubIntrEnClear;
|
||||
// mask for the access counter buffer
|
||||
NvU32 accessCounterMask;
|
||||
// access counter buffer cpu mapping and size
|
||||
void* bufferAddress;
|
||||
NvU32 bufferSize;
|
||||
NvHandle accessCntrBufferHandle;
|
||||
|
||||
// The Notification address in the access counter notification msg does not
|
||||
// contain the correct upper bits 63-47 for GPA-based notifications. RM
|
||||
// provides us with the correct offset to be added.
|
||||
// See Bug 1803015
|
||||
NvU64 baseDmaSysmemAddr;
|
||||
} UvmGpuAccessCntrInfo;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_64K = 1,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_2M = 2,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_16M = 3,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_16G = 4,
|
||||
} UVM_ACCESS_COUNTER_GRANULARITY;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_NONE = 1,
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_QTR = 2,
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_HALF = 3,
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_FULL = 4,
|
||||
} UVM_ACCESS_COUNTER_USE_LIMIT;
|
||||
|
||||
typedef struct UvmGpuAccessCntrConfig_tag
|
||||
{
|
||||
NvU32 mimcGranularity;
|
||||
|
||||
NvU32 momcGranularity;
|
||||
|
||||
NvU32 mimcUseLimit;
|
||||
|
||||
NvU32 momcUseLimit;
|
||||
|
||||
NvU32 threshold;
|
||||
} UvmGpuAccessCntrConfig;
|
||||
|
||||
typedef UvmGpuChannelInfo gpuChannelInfo;
|
||||
typedef UvmGpuChannelAllocParams gpuChannelAllocParams;
|
||||
typedef UvmGpuCaps gpuCaps;
|
||||
typedef UvmGpuCopyEngineCaps gpuCeCaps;
|
||||
typedef UvmGpuCopyEnginesCaps gpuCesCaps;
|
||||
typedef UvmGpuP2PCapsParams getP2PCapsParams;
|
||||
typedef UvmGpuAddressSpaceInfo gpuAddressSpaceInfo;
|
||||
typedef UvmGpuAllocInfo gpuAllocInfo;
|
||||
typedef UvmGpuInfo gpuInfo;
|
||||
typedef UvmGpuClientInfo gpuClientInfo;
|
||||
typedef UvmGpuAccessCntrInfo gpuAccessCntrInfo;
|
||||
typedef UvmGpuAccessCntrConfig gpuAccessCntrConfig;
|
||||
typedef UvmGpuFaultInfo gpuFaultInfo;
|
||||
typedef UvmGpuMemoryInfo gpuMemoryInfo;
|
||||
typedef UvmGpuExternalMappingInfo gpuExternalMappingInfo;
|
||||
typedef UvmGpuChannelResourceInfo gpuChannelResourceInfo;
|
||||
typedef UvmGpuChannelInstanceInfo gpuChannelInstanceInfo;
|
||||
typedef UvmGpuChannelResourceBindParams gpuChannelResourceBindParams;
|
||||
typedef UvmGpuFbInfo gpuFbInfo;
|
||||
typedef UvmGpuEccInfo gpuEccInfo;
|
||||
typedef UvmGpuPagingChannel *gpuPagingChannelHandle;
|
||||
typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo;
|
||||
typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams;
|
||||
typedef UvmPmaAllocationOptions gpuPmaAllocationOptions;
|
||||
|
||||
|
||||
typedef struct ccslContext_t UvmCslContext;
|
||||
typedef NvU64 UvmCslIv;
|
||||
#define UVM_APM_CSL_AUTHTAG_SIZE 32
|
||||
|
||||
|
||||
#endif // _NV_UVM_TYPES_H_
|
||||
177
nvdisplay/kernel-open/common/inc/nvgputypes.h
Normal file
177
nvdisplay/kernel-open/common/inc/nvgputypes.h
Normal file
@@ -0,0 +1,177 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2006 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
/***************************************************************************\
|
||||
|* *|
|
||||
|* NV GPU Types *|
|
||||
|* *|
|
||||
|* This header contains definitions describing NVIDIA's GPU hardware state. *|
|
||||
|* *|
|
||||
\***************************************************************************/
|
||||
|
||||
|
||||
#ifndef NVGPUTYPES_INCLUDED
|
||||
#define NVGPUTYPES_INCLUDED
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
/***************************************************************************\
|
||||
|* NvNotification *|
|
||||
\***************************************************************************/
|
||||
|
||||
/***** NvNotification Structure *****/
|
||||
/*
|
||||
* NV objects return information about method completion to clients via an
|
||||
* array of notification structures in main memory.
|
||||
*
|
||||
* The client sets the status field to NV???_NOTIFICATION_STATUS_IN_PROGRESS.
|
||||
* NV fills in the NvNotification[] data structure in the following order:
|
||||
* timeStamp, otherInfo32, otherInfo16, and then status.
|
||||
*/
|
||||
|
||||
/* memory data structures */
|
||||
typedef volatile struct NvNotificationRec {
|
||||
struct { /* 0000- */
|
||||
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
|
||||
} timeStamp; /* -0007*/
|
||||
NvV32 info32; /* info returned depends on method 0008-000b*/
|
||||
NvV16 info16; /* info returned depends on method 000c-000d*/
|
||||
NvV16 status; /* user sets bit 15, NV sets status 000e-000f*/
|
||||
} NvNotification;
|
||||
|
||||
/***************************************************************************\
|
||||
|* NvGpuSemaphore *|
|
||||
\***************************************************************************/
|
||||
|
||||
/***** NvGpuSemaphore Structure *****/
|
||||
/*
|
||||
* NvGpuSemaphore objects are used by the GPU to synchronize multiple
|
||||
* command-streams.
|
||||
*
|
||||
* Please refer to class documentation for details regarding the content of
|
||||
* the data[] field.
|
||||
*/
|
||||
|
||||
/* memory data structures */
|
||||
typedef volatile struct NvGpuSemaphoreRec {
|
||||
NvV32 data[2]; /* Payload/Report data 0000-0007*/
|
||||
struct { /* 0008- */
|
||||
NvV32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 8- f*/
|
||||
} timeStamp; /* -000f*/
|
||||
} NvGpuSemaphore;
|
||||
|
||||
/***************************************************************************\
|
||||
|* NvGetReport *|
|
||||
\***************************************************************************/
|
||||
|
||||
/*
|
||||
* NV objects, starting with Kelvin, return information such as pixel counts to
|
||||
* the user via the NV*_GET_REPORT method.
|
||||
*
|
||||
* The client fills in the "zero" field to any nonzero value and waits until it
|
||||
* becomes zero. NV fills in the timeStamp, value, and zero fields.
|
||||
*/
|
||||
typedef volatile struct NVGetReportRec {
|
||||
struct { /* 0000- */
|
||||
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
|
||||
} timeStamp; /* -0007*/
|
||||
NvU32 value; /* info returned depends on method 0008-000b*/
|
||||
NvU32 zero; /* always written to zero 000c-000f*/
|
||||
} NvGetReport;
|
||||
|
||||
/***************************************************************************\
|
||||
|* NvRcNotification *|
|
||||
\***************************************************************************/
|
||||
|
||||
/*
|
||||
* NV robust channel notification information is reported to clients via
|
||||
* standard NV01_EVENT objects bound to instance of the NV*_CHANNEL_DMA and
|
||||
* NV*_CHANNEL_GPFIFO objects.
|
||||
*/
|
||||
typedef struct NvRcNotificationRec {
|
||||
struct {
|
||||
NvU32 nanoseconds[2]; /* nanoseconds since Jan. 1, 1970 0- 7*/
|
||||
} timeStamp; /* -0007*/
|
||||
NvU32 exceptLevel; /* exception level 000c-000f*/
|
||||
NvU32 exceptType; /* exception type 0010-0013*/
|
||||
} NvRcNotification;
|
||||
|
||||
/***************************************************************************\
|
||||
|* NvSyncPointFence *|
|
||||
\***************************************************************************/
|
||||
|
||||
/***** NvSyncPointFence Structure *****/
|
||||
/*
|
||||
* NvSyncPointFence objects represent a syncpoint event. The syncPointID
|
||||
* identifies the syncpoint register and the value is the value that the
|
||||
* register will contain right after the event occurs.
|
||||
*
|
||||
* If syncPointID contains NV_INVALID_SYNCPOINT_ID then this is an invalid
|
||||
* event. This is often used to indicate an event in the past (i.e. no need to
|
||||
* wait).
|
||||
*
|
||||
* For more info on syncpoints refer to Mobile channel and syncpoint
|
||||
* documentation.
|
||||
*/
|
||||
typedef struct NvSyncPointFenceRec {
|
||||
NvU32 syncPointID;
|
||||
NvU32 value;
|
||||
} NvSyncPointFence;
|
||||
|
||||
#define NV_INVALID_SYNCPOINT_ID ((NvU32)-1)
|
||||
|
||||
/***************************************************************************\
|
||||
|* *|
|
||||
|* 64 bit type definitions for use in interface structures. *|
|
||||
|* *|
|
||||
\***************************************************************************/
|
||||
|
||||
typedef NvU64 NvOffset; /* GPU address */
|
||||
|
||||
#define NvOffset_HI32(n) ((NvU32)(((NvU64)(n)) >> 32))
|
||||
#define NvOffset_LO32(n) ((NvU32)((NvU64)(n)))
|
||||
|
||||
/*
|
||||
* There are two types of GPU-UUIDs available:
|
||||
*
|
||||
* (1) a SHA-256 based 32 byte ID, formatted as a 64 character
|
||||
* hexadecimal string as "GPU-%16x-%08x-%08x-%08x-%024x"; this is
|
||||
* deprecated.
|
||||
*
|
||||
* (2) a SHA-1 based 16 byte ID, formatted as a 32 character
|
||||
* hexadecimal string as "GPU-%08x-%04x-%04x-%04x-%012x" (the
|
||||
* canonical format of a UUID); this is the default.
|
||||
*/
|
||||
#define NV_GPU_UUID_SHA1_LEN (16)
|
||||
#define NV_GPU_UUID_SHA256_LEN (32)
|
||||
#define NV_GPU_UUID_LEN NV_GPU_UUID_SHA1_LEN
|
||||
|
||||
#ifdef __cplusplus
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* NVGPUTYPES_INCLUDED */
|
||||
37
nvdisplay/kernel-open/common/inc/nvi2c.h
Normal file
37
nvdisplay/kernel-open/common/inc/nvi2c.h
Normal file
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _NV_I2C_H_
|
||||
#define _NV_I2C_H_
|
||||
|
||||
#define NV_I2C_MSG_WR 0x0000
|
||||
#define NV_I2C_MSG_RD 0x0001
|
||||
|
||||
typedef struct nv_i2c_msg_s
|
||||
{
|
||||
NvU16 addr;
|
||||
NvU16 flags;
|
||||
NvU16 len;
|
||||
NvU8* buf;
|
||||
} nv_i2c_msg_t;
|
||||
|
||||
#endif
|
||||
108
nvdisplay/kernel-open/common/inc/nvimpshared.h
Normal file
108
nvdisplay/kernel-open/common/inc/nvimpshared.h
Normal file
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/******************************************************************************\
|
||||
* *
|
||||
* Description: *
|
||||
* Accommodates sharing of IMP-related structures between kernel interface *
|
||||
* files and core RM. *
|
||||
* *
|
||||
\******************************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <nvtypes.h>
|
||||
#if defined(_MSC_VER)
|
||||
#pragma warning(disable:4324)
|
||||
#endif
|
||||
|
||||
//
|
||||
// This file was generated with FINN, an NVIDIA coding tool.
|
||||
// Source file: nvimpshared.finn
|
||||
//
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//
|
||||
// There are only a small number of discrete dramclk frequencies available on
|
||||
// the system. This structure contains IMP-relevant information associated
|
||||
// with a specific dramclk frequency.
|
||||
//
|
||||
typedef struct DRAM_CLK_INSTANCE {
|
||||
NvU32 dram_clk_freq_khz;
|
||||
|
||||
NvU32 mchub_clk_khz;
|
||||
|
||||
NvU32 mc_clk_khz;
|
||||
|
||||
NvU32 max_iso_bw_kbps;
|
||||
|
||||
//
|
||||
// switch_latency_ns is the maximum time required to switch the dramclk
|
||||
// frequency to the frequency specified in dram_clk_freq_khz.
|
||||
//
|
||||
NvU32 switch_latency_ns;
|
||||
} DRAM_CLK_INSTANCE;
|
||||
|
||||
//
|
||||
// This table is used to collect information from other modules that is needed
|
||||
// for RM IMP calculations. (Used on Tegra only.)
|
||||
//
|
||||
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_UNKNOWN 0U
|
||||
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR4 1U
|
||||
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR5 2U
|
||||
|
||||
typedef struct TEGRA_IMP_IMPORT_DATA {
|
||||
//
|
||||
// max_iso_bw_kbps stores the maximum possible ISO bandwidth available to
|
||||
// display, assuming display is the only active ISO client. (Note that ISO
|
||||
// bandwidth will typically be allocated to multiple clients, so display
|
||||
// will generally not have access to the maximum possible bandwidth.)
|
||||
//
|
||||
NvU32 max_iso_bw_kbps;
|
||||
|
||||
NvU32 dram_type;
|
||||
// On Orin, each dram channel is 16 bits wide.
|
||||
NvU32 num_dram_channels;
|
||||
|
||||
//
|
||||
// dram_clk_instance stores entries for all possible dramclk frequencies,
|
||||
// sorted by dramclk frequency in increasing order.
|
||||
//
|
||||
// "24" is expected to be larger than the actual number of required entries
|
||||
// (which is provided by a BPMP API), but it can be increased if necessary.
|
||||
//
|
||||
// num_dram_clk_entries is filled in with the actual number of distinct
|
||||
// dramclk entries.
|
||||
//
|
||||
NvU32 num_dram_clk_entries;
|
||||
DRAM_CLK_INSTANCE dram_clk_instance[24];
|
||||
} TEGRA_IMP_IMPORT_DATA;
|
||||
607
nvdisplay/kernel-open/common/inc/nvkms-api-types.h
Normal file
607
nvdisplay/kernel-open/common/inc/nvkms-api-types.h
Normal file
@@ -0,0 +1,607 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#if !defined(NVKMS_API_TYPES_H)
|
||||
#define NVKMS_API_TYPES_H
|
||||
|
||||
#include <nvtypes.h>
|
||||
#include <nvmisc.h>
|
||||
#include <nvlimits.h>
|
||||
|
||||
#define NVKMS_MAX_SUBDEVICES NV_MAX_SUBDEVICES
|
||||
|
||||
#define NVKMS_LEFT 0
|
||||
#define NVKMS_RIGHT 1
|
||||
#define NVKMS_MAX_EYES 2
|
||||
|
||||
#define NVKMS_MAIN_LAYER 0
|
||||
#define NVKMS_OVERLAY_LAYER 1
|
||||
#define NVKMS_MAX_LAYERS_PER_HEAD 8
|
||||
|
||||
#define NVKMS_MAX_PLANES_PER_SURFACE 3
|
||||
|
||||
#define NVKMS_DP_ADDRESS_STRING_LENGTH 64
|
||||
|
||||
#define NVKMS_DEVICE_ID_TEGRA 0x0000ffff
|
||||
|
||||
typedef NvU32 NvKmsDeviceHandle;
|
||||
typedef NvU32 NvKmsDispHandle;
|
||||
typedef NvU32 NvKmsConnectorHandle;
|
||||
typedef NvU32 NvKmsSurfaceHandle;
|
||||
typedef NvU32 NvKmsFrameLockHandle;
|
||||
typedef NvU32 NvKmsDeferredRequestFifoHandle;
|
||||
typedef NvU32 NvKmsSwapGroupHandle;
|
||||
typedef NvU32 NvKmsVblankSyncObjectHandle;
|
||||
|
||||
struct NvKmsSize {
|
||||
NvU16 width;
|
||||
NvU16 height;
|
||||
};
|
||||
|
||||
struct NvKmsPoint {
|
||||
NvU16 x;
|
||||
NvU16 y;
|
||||
};
|
||||
|
||||
struct NvKmsSignedPoint {
|
||||
NvS16 x;
|
||||
NvS16 y;
|
||||
};
|
||||
|
||||
struct NvKmsRect {
|
||||
NvU16 x;
|
||||
NvU16 y;
|
||||
NvU16 width;
|
||||
NvU16 height;
|
||||
};
|
||||
|
||||
/*
|
||||
* A 3x3 row-major matrix.
|
||||
*
|
||||
* The elements are 32-bit single-precision IEEE floating point values. The
|
||||
* floating point bit pattern should be stored in NvU32s to be passed into the
|
||||
* kernel.
|
||||
*/
|
||||
struct NvKmsMatrix {
|
||||
NvU32 m[3][3];
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
NVKMS_CONNECTOR_TYPE_DP = 0,
|
||||
NVKMS_CONNECTOR_TYPE_VGA = 1,
|
||||
NVKMS_CONNECTOR_TYPE_DVI_I = 2,
|
||||
NVKMS_CONNECTOR_TYPE_DVI_D = 3,
|
||||
NVKMS_CONNECTOR_TYPE_ADC = 4,
|
||||
NVKMS_CONNECTOR_TYPE_LVDS = 5,
|
||||
NVKMS_CONNECTOR_TYPE_HDMI = 6,
|
||||
NVKMS_CONNECTOR_TYPE_USBC = 7,
|
||||
NVKMS_CONNECTOR_TYPE_DSI = 8,
|
||||
NVKMS_CONNECTOR_TYPE_DP_SERIALIZER = 9,
|
||||
NVKMS_CONNECTOR_TYPE_UNKNOWN = 10,
|
||||
NVKMS_CONNECTOR_TYPE_MAX = NVKMS_CONNECTOR_TYPE_UNKNOWN,
|
||||
} NvKmsConnectorType;
|
||||
|
||||
static inline
|
||||
const char *NvKmsConnectorTypeString(const NvKmsConnectorType connectorType)
|
||||
{
|
||||
switch (connectorType) {
|
||||
case NVKMS_CONNECTOR_TYPE_DP: return "DP";
|
||||
case NVKMS_CONNECTOR_TYPE_VGA: return "VGA";
|
||||
case NVKMS_CONNECTOR_TYPE_DVI_I: return "DVI-I";
|
||||
case NVKMS_CONNECTOR_TYPE_DVI_D: return "DVI-D";
|
||||
case NVKMS_CONNECTOR_TYPE_ADC: return "ADC";
|
||||
case NVKMS_CONNECTOR_TYPE_LVDS: return "LVDS";
|
||||
case NVKMS_CONNECTOR_TYPE_HDMI: return "HDMI";
|
||||
case NVKMS_CONNECTOR_TYPE_USBC: return "USB-C";
|
||||
case NVKMS_CONNECTOR_TYPE_DSI: return "DSI";
|
||||
case NVKMS_CONNECTOR_TYPE_DP_SERIALIZER: return "DP-SERIALIZER";
|
||||
default: break;
|
||||
}
|
||||
return "Unknown";
|
||||
}
|
||||
|
||||
typedef enum {
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_VGA = 0,
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_LVDS = 1,
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_TMDS = 2,
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_DP = 3,
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_DSI = 4,
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN = 5,
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_MAX =
|
||||
NVKMS_CONNECTOR_SIGNAL_FORMAT_UNKNOWN,
|
||||
} NvKmsConnectorSignalFormat;
|
||||
|
||||
/*!
|
||||
* Description of Notifiers and Semaphores (Non-isochronous (NISO) surfaces).
|
||||
*
|
||||
* When flipping, the client can optionally specify a notifier and/or
|
||||
* a semaphore to use with the flip. The surfaces used for these
|
||||
* should be registered with NVKMS to get an NvKmsSurfaceHandle.
|
||||
*
|
||||
* NvKmsNIsoSurface::offsetInWords indicates the starting location, in
|
||||
* 32-bit words, within the surface where EVO should write the
|
||||
* notifier or semaphore. Note that only the first 4096 bytes of a
|
||||
* surface can be used by semaphores or notifiers; offsetInWords must
|
||||
* allow for the semaphore or notifier to be written within the first
|
||||
* 4096 bytes of the surface. I.e., this must be satisfied:
|
||||
*
|
||||
* ((offsetInWords * 4) + elementSizeInBytes) <= 4096
|
||||
*
|
||||
* Where elementSizeInBytes is:
|
||||
*
|
||||
* if NISO_FORMAT_FOUR_WORD*, elementSizeInBytes = 16
|
||||
* if NISO_FORMAT_LEGACY,
|
||||
* if overlay && notifier, elementSizeInBytes = 16
|
||||
* else, elementSizeInBytes = 4
|
||||
*
|
||||
* Note that different GPUs support different semaphore and notifier formats.
|
||||
* Check NvKmsAllocDeviceReply::validNIsoFormatMask to determine which are
|
||||
* valid for the given device.
|
||||
*
|
||||
* Note also that FOUR_WORD and FOUR_WORD_NVDISPLAY are the same size, but
|
||||
* FOUR_WORD uses a format compatible with display class 907[ce], and
|
||||
* FOUR_WORD_NVDISPLAY uses a format compatible with c37e (actually defined by
|
||||
* the NV_DISP_NOTIFIER definition in clc37d.h).
|
||||
*/
|
||||
enum NvKmsNIsoFormat {
|
||||
NVKMS_NISO_FORMAT_LEGACY,
|
||||
NVKMS_NISO_FORMAT_FOUR_WORD,
|
||||
NVKMS_NISO_FORMAT_FOUR_WORD_NVDISPLAY,
|
||||
};
|
||||
|
||||
enum NvKmsEventType {
|
||||
NVKMS_EVENT_TYPE_DPY_CHANGED,
|
||||
NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED,
|
||||
NVKMS_EVENT_TYPE_DYNAMIC_DPY_DISCONNECTED,
|
||||
NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED,
|
||||
NVKMS_EVENT_TYPE_FRAMELOCK_ATTRIBUTE_CHANGED,
|
||||
NVKMS_EVENT_TYPE_FLIP_OCCURRED,
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
NV_EVO_SCALER_1TAP = 0,
|
||||
NV_EVO_SCALER_2TAPS = 1,
|
||||
NV_EVO_SCALER_3TAPS = 2,
|
||||
NV_EVO_SCALER_5TAPS = 3,
|
||||
NV_EVO_SCALER_8TAPS = 4,
|
||||
NV_EVO_SCALER_TAPS_MIN = NV_EVO_SCALER_1TAP,
|
||||
NV_EVO_SCALER_TAPS_MAX = NV_EVO_SCALER_8TAPS,
|
||||
} NVEvoScalerTaps;
|
||||
|
||||
/* This structure describes the scaling bounds for a given layer. */
|
||||
struct NvKmsScalingUsageBounds {
|
||||
/*
|
||||
* Maximum vertical downscale factor (scaled by 1024)
|
||||
*
|
||||
* For example, if the downscale factor is 1.5, then maxVDownscaleFactor
|
||||
* would be 1.5 x 1024 = 1536.
|
||||
*/
|
||||
NvU16 maxVDownscaleFactor;
|
||||
|
||||
/*
|
||||
* Maximum horizontal downscale factor (scaled by 1024)
|
||||
*
|
||||
* See the example above for maxVDownscaleFactor.
|
||||
*/
|
||||
NvU16 maxHDownscaleFactor;
|
||||
|
||||
/* Maximum vertical taps allowed */
|
||||
NVEvoScalerTaps vTaps;
|
||||
|
||||
/* Whether vertical upscaling is allowed */
|
||||
NvBool vUpscalingAllowed;
|
||||
};
|
||||
|
||||
struct NvKmsUsageBounds {
|
||||
struct {
|
||||
NvBool usable;
|
||||
struct NvKmsScalingUsageBounds scaling;
|
||||
NvU64 supportedSurfaceMemoryFormats NV_ALIGN_BYTES(8);
|
||||
} layer[NVKMS_MAX_LAYERS_PER_HEAD];
|
||||
};
|
||||
|
||||
/*
|
||||
* A 3x4 row-major colorspace conversion matrix.
|
||||
*
|
||||
* The output color C' is the CSC matrix M times the column vector
|
||||
* [ R, G, B, 1 ].
|
||||
*
|
||||
* Each entry in the matrix is a signed 2's-complement fixed-point number with
|
||||
* 3 integer bits and 16 fractional bits.
|
||||
*/
|
||||
struct NvKmsCscMatrix {
|
||||
NvS32 m[3][4];
|
||||
};
|
||||
|
||||
#define NVKMS_IDENTITY_CSC_MATRIX \
|
||||
(struct NvKmsCscMatrix){{ \
|
||||
{ 0x10000, 0, 0, 0 }, \
|
||||
{ 0, 0x10000, 0, 0 }, \
|
||||
{ 0, 0, 0x10000, 0 } \
|
||||
}}
|
||||
|
||||
/*!
|
||||
* A color key match bit used in the blend equations and one can select the src
|
||||
* or dst Color Key when blending. Assert key bit means match, de-assert key
|
||||
* bit means nomatch.
|
||||
*
|
||||
* The src Color Key means using the key bit from the current layer, the dst
|
||||
* Color Key means using key bit from the previous layer composition stage. The
|
||||
* src or dst key bit will be inherited by blended pixel for the preparation of
|
||||
* next blending, as dst Color Key.
|
||||
*
|
||||
* src: Forward the color key match bit from the current layer pixel to next layer
|
||||
* composition stage.
|
||||
*
|
||||
* dst: Forward the color key match bit from the previous composition stage
|
||||
* pixel to next layer composition stage.
|
||||
*
|
||||
* disable: Forward “1” to the next layer composition stage as the color key.
|
||||
*/
|
||||
enum NvKmsCompositionColorKeySelect {
|
||||
NVKMS_COMPOSITION_COLOR_KEY_SELECT_DISABLE = 0,
|
||||
NVKMS_COMPOSITION_COLOR_KEY_SELECT_SRC,
|
||||
NVKMS_COMPOSITION_COLOR_KEY_SELECT_DST,
|
||||
};
|
||||
|
||||
#define NVKMS_COMPOSITION_NUMBER_OF_COLOR_KEY_SELECTS 3
|
||||
|
||||
/*!
|
||||
* Composition modes used for surfaces in general.
|
||||
* The various types of composition are:
|
||||
*
|
||||
* Opaque: source pixels are opaque regardless of alpha,
|
||||
* and will occlude the destination pixel.
|
||||
*
|
||||
* Alpha blending: aka opacity, which could be specified
|
||||
* for a surface in its entirety, or on a per-pixel basis.
|
||||
*
|
||||
* Non-premultiplied: alpha value applies to source pixel,
|
||||
* and also counter-weighs the destination pixel.
|
||||
* Premultiplied: alpha already applied to source pixel,
|
||||
* so it only counter-weighs the destination pixel.
|
||||
*
|
||||
* Color keying: use a color key structure to decide
|
||||
* the criteria for matching and compositing.
|
||||
* (See NVColorKey below.)
|
||||
*/
|
||||
enum NvKmsCompositionBlendingMode {
|
||||
/*!
|
||||
* Modes that use no other parameters.
|
||||
*/
|
||||
NVKMS_COMPOSITION_BLENDING_MODE_OPAQUE,
|
||||
|
||||
/*!
|
||||
* Mode that ignores both per-pixel alpha provided
|
||||
* by client and the surfaceAlpha, makes source pixel
|
||||
* totally transparent.
|
||||
*/
|
||||
NVKMS_COMPOSITION_BLENDING_MODE_TRANSPARENT,
|
||||
|
||||
/*!
|
||||
* Modes that use per-pixel alpha provided by client,
|
||||
* and the surfaceAlpha must be set to 0.
|
||||
*/
|
||||
NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA,
|
||||
NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA,
|
||||
|
||||
/*!
|
||||
* These use both the surface-wide and per-pixel alpha values.
|
||||
* surfaceAlpha is treated as numerator ranging from 0 to 255
|
||||
* of a fraction whose denominator is 255.
|
||||
*/
|
||||
NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA,
|
||||
NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA,
|
||||
};
|
||||
|
||||
static inline NvBool
|
||||
NvKmsIsCompositionModeUseAlpha(enum NvKmsCompositionBlendingMode mode)
|
||||
{
|
||||
return mode == NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_ALPHA ||
|
||||
mode == NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_ALPHA ||
|
||||
mode == NVKMS_COMPOSITION_BLENDING_MODE_PREMULT_SURFACE_ALPHA ||
|
||||
mode == NVKMS_COMPOSITION_BLENDING_MODE_NON_PREMULT_SURFACE_ALPHA;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Abstract description of a color key.
|
||||
*
|
||||
* a, r, g, and b are component values in the same width as the framebuffer
|
||||
* values being scanned out.
|
||||
*
|
||||
* match[ARGB] defines whether that component is considered when matching the
|
||||
* color key -- TRUE means that the value of the corresponding component must
|
||||
* match the given value for the given pixel to be considered a 'key match';
|
||||
* FALSE means that the value of that component is not a key match criterion.
|
||||
*/
|
||||
typedef struct {
|
||||
NvU16 a, r, g, b;
|
||||
NvBool matchA, matchR, matchG, matchB;
|
||||
} NVColorKey;
|
||||
|
||||
/*!
|
||||
* Describes the composition parameters for the single layer.
|
||||
*/
|
||||
struct NvKmsCompositionParams {
|
||||
enum NvKmsCompositionColorKeySelect colorKeySelect;
|
||||
NVColorKey colorKey;
|
||||
/*
|
||||
* It is possible to assign different blending mode for match pixels and
|
||||
* nomatch pixels. blendingMode[0] is used to blend a pixel with the color key
|
||||
* match bit "0", and blendingMode[1] is used to blend a pixel with the color
|
||||
* key match bit "1".
|
||||
*
|
||||
* But because of the hardware restrictions match and nomatch pixels can
|
||||
* not use blending mode PREMULT_ALPHA, NON_PREMULT_ALPHA,
|
||||
* PREMULT_SURFACE_ALPHA, and NON_PREMULT_SURFACE_ALPHA at once.
|
||||
*/
|
||||
enum NvKmsCompositionBlendingMode blendingMode[2];
|
||||
NvU8 surfaceAlpha; /* Applies to all pixels of entire surface */
|
||||
/*
|
||||
* Defines the composition order. A smaller value moves the layer closer to
|
||||
* the top (away from the background). No need to pick consecutive values,
|
||||
* requirements are that the value should be different for each of the
|
||||
* layers owned by the head and the value for the main layer should be
|
||||
* the greatest one.
|
||||
*
|
||||
* Cursor always remains at the top of all other layers, this parameter
|
||||
* has no effect on cursor. NVKMS assigns default depth to each of the
|
||||
* supported layers, by default depth of the layer is calculated as
|
||||
* (NVKMS_MAX_LAYERS_PER_HEAD - index of the layer). If depth is set to
|
||||
* '0' then default depth value will get used.
|
||||
*/
|
||||
NvU8 depth;
|
||||
};
|
||||
|
||||
/*!
|
||||
* Describes the composition capabilities supported by the hardware for
|
||||
* cursor or layer. It describes supported the color key selects and for each
|
||||
* of the supported color key selects it describes supported blending modes
|
||||
* for match and nomatch pixles.
|
||||
*/
|
||||
struct NvKmsCompositionCapabilities {
|
||||
|
||||
struct {
|
||||
/*
|
||||
* A bitmask of the supported blending modes for match and nomatch
|
||||
* pixels. It should be the bitwise 'or' of one or more
|
||||
* NVBIT(NVKMS_COMPOSITION_BLENDING_MODE_*) values.
|
||||
*/
|
||||
NvU32 supportedBlendModes[2];
|
||||
} colorKeySelect[NVKMS_COMPOSITION_NUMBER_OF_COLOR_KEY_SELECTS];
|
||||
|
||||
/*
|
||||
* A bitmask of the supported color key selects.
|
||||
*
|
||||
* It should be the bitwise 'or' of one or more
|
||||
* NVBIT(NVKMS_COMPOSITION_COLOR_KEY_SELECT_*)
|
||||
* values.
|
||||
*/
|
||||
NvU32 supportedColorKeySelects;
|
||||
};
|
||||
|
||||
struct NvKmsLayerCapabilities {
|
||||
/*!
|
||||
* Whether Layer supports the window mode. If window mode is supported,
|
||||
* then clients can set the layer's dimensions so that they're smaller than
|
||||
* the viewport, and can also change the output position of the layer to a
|
||||
* non-(0, 0) position.
|
||||
*
|
||||
* NOTE: Dimension changes are currently unsupported for the main layer,
|
||||
* and output position changes for the main layer are currently only
|
||||
* supported via IOCTL_SET_LAYER_POSITION but not via flips. Support for
|
||||
* these is coming soon, via changes to flip code.
|
||||
*/
|
||||
NvBool supportsWindowMode :1;
|
||||
|
||||
/*!
|
||||
* Whether layer supports HDR pipe.
|
||||
*/
|
||||
NvBool supportsHDR :1;
|
||||
|
||||
|
||||
/*!
|
||||
* Describes the supported Color Key selects and blending modes for
|
||||
* match and nomatch layer pixels.
|
||||
*/
|
||||
struct NvKmsCompositionCapabilities composition;
|
||||
|
||||
/*!
|
||||
* Which NvKmsSurfaceMemoryFormat enum values are supported by the NVKMS
|
||||
* device on the given scanout surface layer.
|
||||
*
|
||||
* Iff a particular enum NvKmsSurfaceMemoryFormat 'value' is supported,
|
||||
* then (1 << value) will be set in the appropriate bitmask.
|
||||
*
|
||||
* Note that these bitmasks just report the static SW/HW capabilities,
|
||||
* and are a superset of the formats that IMP may allow. Clients are
|
||||
* still expected to honor the NvKmsUsageBounds for each head.
|
||||
*/
|
||||
NvU64 supportedSurfaceMemoryFormats NV_ALIGN_BYTES(8);
|
||||
};
|
||||
|
||||
/*!
|
||||
* Surface layouts.
|
||||
*
|
||||
* BlockLinear is the NVIDIA GPU native tiling format, arranging pixels into
|
||||
* blocks or tiles for better locality during common GPU operations.
|
||||
*
|
||||
* Pitch is the naive "linear" surface layout with pixels laid out sequentially
|
||||
* in memory line-by-line, optionally with some padding at the end of each line
|
||||
* for alignment purposes.
|
||||
*/
|
||||
enum NvKmsSurfaceMemoryLayout {
|
||||
NvKmsSurfaceMemoryLayoutBlockLinear = 0,
|
||||
NvKmsSurfaceMemoryLayoutPitch = 1,
|
||||
};
|
||||
|
||||
static inline const char *NvKmsSurfaceMemoryLayoutToString(
|
||||
enum NvKmsSurfaceMemoryLayout layout)
|
||||
{
|
||||
switch (layout) {
|
||||
default:
|
||||
return "Unknown";
|
||||
case NvKmsSurfaceMemoryLayoutBlockLinear:
|
||||
return "BlockLinear";
|
||||
case NvKmsSurfaceMemoryLayoutPitch:
|
||||
return "Pitch";
|
||||
}
|
||||
}
|
||||
|
||||
typedef enum {
|
||||
MUX_STATE_GET = 0,
|
||||
MUX_STATE_INTEGRATED = 1,
|
||||
MUX_STATE_DISCRETE = 2,
|
||||
MUX_STATE_UNKNOWN = 3,
|
||||
} NvMuxState;
|
||||
|
||||
enum NvKmsRotation {
|
||||
NVKMS_ROTATION_0 = 0,
|
||||
NVKMS_ROTATION_90 = 1,
|
||||
NVKMS_ROTATION_180 = 2,
|
||||
NVKMS_ROTATION_270 = 3,
|
||||
NVKMS_ROTATION_MIN = NVKMS_ROTATION_0,
|
||||
NVKMS_ROTATION_MAX = NVKMS_ROTATION_270,
|
||||
};
|
||||
|
||||
struct NvKmsRRParams {
|
||||
enum NvKmsRotation rotation;
|
||||
NvBool reflectionX;
|
||||
NvBool reflectionY;
|
||||
};
|
||||
|
||||
/*!
|
||||
* Convert each possible NvKmsRRParams to a unique integer [0..15],
|
||||
* so that we can describe possible NvKmsRRParams with an NvU16 bitmask.
|
||||
*
|
||||
* E.g.
|
||||
* rotation = 0, reflectionX = F, reflectionY = F == 0|0|0 == 0
|
||||
* ...
|
||||
* rotation = 270, reflectionX = T, reflectionY = T == 3|4|8 == 15
|
||||
*/
|
||||
static inline NvU8 NvKmsRRParamsToCapBit(const struct NvKmsRRParams *rrParams)
|
||||
{
|
||||
NvU8 bitPosition = (NvU8)rrParams->rotation;
|
||||
if (rrParams->reflectionX) {
|
||||
bitPosition |= NVBIT(2);
|
||||
}
|
||||
if (rrParams->reflectionY) {
|
||||
bitPosition |= NVBIT(3);
|
||||
}
|
||||
return bitPosition;
|
||||
}
|
||||
|
||||
/*
|
||||
* NVKMS_MEMORY_ISO is used to tag surface memory that will be accessed via
|
||||
* display's isochronous interface. Examples of this type of memory are pixel
|
||||
* data and LUT entries.
|
||||
*
|
||||
* NVKMS_MEMORY_NISO is used to tag surface memory that will be accessed via
|
||||
* display's non-isochronous interface. Examples of this type of memory are
|
||||
* semaphores and notifiers.
|
||||
*/
|
||||
typedef enum {
|
||||
NVKMS_MEMORY_ISO = 0,
|
||||
NVKMS_MEMORY_NISO = 1,
|
||||
} NvKmsMemoryIsoType;
|
||||
|
||||
typedef struct {
|
||||
NvBool coherent;
|
||||
NvBool noncoherent;
|
||||
} NvKmsDispIOCoherencyModes;
|
||||
|
||||
enum NvKmsInputColorSpace {
|
||||
/* Unknown colorspace; no de-gamma will be applied */
|
||||
NVKMS_INPUT_COLORSPACE_NONE = 0,
|
||||
|
||||
/* Linear, Rec.709 [-0.5, 7.5) */
|
||||
NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR = 1,
|
||||
|
||||
/* PQ, Rec.2020 unity */
|
||||
NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2,
|
||||
};
|
||||
|
||||
enum NvKmsOutputTf {
|
||||
/*
|
||||
* NVKMS itself won't apply any OETF (clients are still
|
||||
* free to provide a custom OLUT)
|
||||
*/
|
||||
NVKMS_OUTPUT_TF_NONE = 0,
|
||||
NVKMS_OUTPUT_TF_TRADITIONAL_GAMMA_SDR = 1,
|
||||
NVKMS_OUTPUT_TF_PQ = 2,
|
||||
};
|
||||
|
||||
/*!
|
||||
* HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec.
|
||||
* This is expected to match exactly with the spec.
|
||||
*/
|
||||
struct NvKmsHDRStaticMetadata {
|
||||
/*!
|
||||
* Color primaries of the data.
|
||||
* These are coded as unsigned 16-bit values in units of 0.00002,
|
||||
* where 0x0000 represents zero and 0xC350 represents 1.0000.
|
||||
*/
|
||||
struct {
|
||||
NvU16 x, y;
|
||||
} displayPrimaries[3];
|
||||
|
||||
/*!
|
||||
* White point of colorspace data.
|
||||
* These are coded as unsigned 16-bit values in units of 0.00002,
|
||||
* where 0x0000 represents zero and 0xC350 represents 1.0000.
|
||||
*/
|
||||
struct {
|
||||
NvU16 x, y;
|
||||
} whitePoint;
|
||||
|
||||
/**
|
||||
* Maximum mastering display luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
NvU16 maxDisplayMasteringLuminance;
|
||||
|
||||
/*!
|
||||
* Minimum mastering display luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of
|
||||
* 0.0001 cd/m2, where 0x0001 represents 0.0001 cd/m2 and 0xFFFF
|
||||
* represents 6.5535 cd/m2.
|
||||
*/
|
||||
NvU16 minDisplayMasteringLuminance;
|
||||
|
||||
/*!
|
||||
* Maximum content light level.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
NvU16 maxCLL;
|
||||
|
||||
/*!
|
||||
* Maximum frame-average light level.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
* where 0x0001 represents 1 cd/m2 and 0xFFFF represents 65535 cd/m2.
|
||||
*/
|
||||
NvU16 maxFALL;
|
||||
};
|
||||
|
||||
#endif /* NVKMS_API_TYPES_H */
|
||||
125
nvdisplay/kernel-open/common/inc/nvkms-format.h
Normal file
125
nvdisplay/kernel-open/common/inc/nvkms-format.h
Normal file
@@ -0,0 +1,125 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#if !defined(NVKMS_FORMAT_H)
|
||||
#define NVKMS_FORMAT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
/*
|
||||
* In order to interpret these pixel format namings, please take note of these
|
||||
* conventions:
|
||||
* - The Y8_U8__Y8_V8_N422 and U8_Y8__V8_Y8_N422 formats are both packed formats
|
||||
* that have an interleaved chroma component across every two pixels. The
|
||||
* double-underscore is a separator between these two pixel groups.
|
||||
* - The triple-underscore is a separator between planes.
|
||||
* - The 'N' suffix is a delimiter for the chroma decimation factor.
|
||||
*
|
||||
* As examples of the above rules:
|
||||
* - The Y8_U8__Y8_V8_N422 format has one 8-bit luma component (Y8) and one
|
||||
* 8-bit chroma component (U8) in pixel N, and one 8-bit luma component (Y8)
|
||||
* and one 8-bit chroma component (V8) in pixel (N + 1). This format is
|
||||
* 422-decimated since the U and V chroma samples are shared between each
|
||||
* pair of adjacent pixels per line.
|
||||
* - The Y10___U10V10_N444 format has one plane of 10-bit luma (Y10) components,
|
||||
* and another plane of 10-bit chroma components (U10V10). This format has no
|
||||
* chroma decimation since the luma and chroma components are sampled at the
|
||||
* same rate.
|
||||
*/
|
||||
enum NvKmsSurfaceMemoryFormat {
|
||||
NvKmsSurfaceMemoryFormatI8 = 0,
|
||||
NvKmsSurfaceMemoryFormatA1R5G5B5 = 1,
|
||||
NvKmsSurfaceMemoryFormatX1R5G5B5 = 2,
|
||||
NvKmsSurfaceMemoryFormatR5G6B5 = 3,
|
||||
NvKmsSurfaceMemoryFormatA8R8G8B8 = 4,
|
||||
NvKmsSurfaceMemoryFormatX8R8G8B8 = 5,
|
||||
NvKmsSurfaceMemoryFormatA2B10G10R10 = 6,
|
||||
NvKmsSurfaceMemoryFormatX2B10G10R10 = 7,
|
||||
NvKmsSurfaceMemoryFormatA8B8G8R8 = 8,
|
||||
NvKmsSurfaceMemoryFormatX8B8G8R8 = 9,
|
||||
NvKmsSurfaceMemoryFormatRF16GF16BF16AF16 = 10,
|
||||
NvKmsSurfaceMemoryFormatR16G16B16A16 = 11,
|
||||
NvKmsSurfaceMemoryFormatRF32GF32BF32AF32 = 12,
|
||||
NvKmsSurfaceMemoryFormatY8_U8__Y8_V8_N422 = 13,
|
||||
NvKmsSurfaceMemoryFormatU8_Y8__V8_Y8_N422 = 14,
|
||||
NvKmsSurfaceMemoryFormatY8___U8V8_N444 = 15,
|
||||
NvKmsSurfaceMemoryFormatY8___V8U8_N444 = 16,
|
||||
NvKmsSurfaceMemoryFormatY8___U8V8_N422 = 17,
|
||||
NvKmsSurfaceMemoryFormatY8___V8U8_N422 = 18,
|
||||
NvKmsSurfaceMemoryFormatY8___U8V8_N420 = 19,
|
||||
NvKmsSurfaceMemoryFormatY8___V8U8_N420 = 20,
|
||||
NvKmsSurfaceMemoryFormatY10___U10V10_N444 = 21,
|
||||
NvKmsSurfaceMemoryFormatY10___V10U10_N444 = 22,
|
||||
NvKmsSurfaceMemoryFormatY10___U10V10_N422 = 23,
|
||||
NvKmsSurfaceMemoryFormatY10___V10U10_N422 = 24,
|
||||
NvKmsSurfaceMemoryFormatY10___U10V10_N420 = 25,
|
||||
NvKmsSurfaceMemoryFormatY10___V10U10_N420 = 26,
|
||||
NvKmsSurfaceMemoryFormatY12___U12V12_N444 = 27,
|
||||
NvKmsSurfaceMemoryFormatY12___V12U12_N444 = 28,
|
||||
NvKmsSurfaceMemoryFormatY12___U12V12_N422 = 29,
|
||||
NvKmsSurfaceMemoryFormatY12___V12U12_N422 = 30,
|
||||
NvKmsSurfaceMemoryFormatY12___U12V12_N420 = 31,
|
||||
NvKmsSurfaceMemoryFormatY12___V12U12_N420 = 32,
|
||||
NvKmsSurfaceMemoryFormatY8___U8___V8_N444 = 33,
|
||||
NvKmsSurfaceMemoryFormatY8___U8___V8_N420 = 34,
|
||||
NvKmsSurfaceMemoryFormatMin = NvKmsSurfaceMemoryFormatI8,
|
||||
NvKmsSurfaceMemoryFormatMax = NvKmsSurfaceMemoryFormatY8___U8___V8_N420,
|
||||
};
|
||||
|
||||
typedef struct NvKmsSurfaceMemoryFormatInfo {
|
||||
enum NvKmsSurfaceMemoryFormat format;
|
||||
const char *name;
|
||||
NvU8 depth;
|
||||
NvBool isYUV;
|
||||
NvU8 numPlanes;
|
||||
|
||||
union {
|
||||
struct {
|
||||
NvU8 bytesPerPixel;
|
||||
NvU8 bitsPerPixel;
|
||||
} rgb;
|
||||
|
||||
struct {
|
||||
NvU8 depthPerComponent;
|
||||
NvU8 storageBitsPerComponent;
|
||||
NvU8 horizChromaDecimationFactor;
|
||||
NvU8 vertChromaDecimationFactor;
|
||||
} yuv;
|
||||
};
|
||||
} NvKmsSurfaceMemoryFormatInfo;
|
||||
|
||||
const NvKmsSurfaceMemoryFormatInfo *nvKmsGetSurfaceMemoryFormatInfo(
|
||||
const enum NvKmsSurfaceMemoryFormat format);
|
||||
|
||||
const char *nvKmsSurfaceMemoryFormatToString(
|
||||
const enum NvKmsSurfaceMemoryFormat format);
|
||||
|
||||
#ifdef __cplusplus
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* NVKMS_FORMAT_H */
|
||||
1081
nvdisplay/kernel-open/common/inc/nvkms-kapi.h
Normal file
1081
nvdisplay/kernel-open/common/inc/nvkms-kapi.h
Normal file
File diff suppressed because it is too large
Load Diff
59
nvdisplay/kernel-open/common/inc/nvlimits.h
Normal file
59
nvdisplay/kernel-open/common/inc/nvlimits.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
//
|
||||
// This file was generated with FINN, an NVIDIA coding tool.
|
||||
// Source file: nvlimits.finn
|
||||
//
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* This is the maximum number of GPUs supported in a single system.
|
||||
*/
|
||||
#define NV_MAX_DEVICES 32
|
||||
|
||||
/*
|
||||
* This is the maximum number of subdevices within a single device.
|
||||
*/
|
||||
#define NV_MAX_SUBDEVICES 8
|
||||
|
||||
/*
|
||||
* This is the maximum length of the process name string.
|
||||
*/
|
||||
#define NV_PROC_NAME_MAX_LENGTH 100U
|
||||
|
||||
/*
|
||||
* This is the maximum number of heads per GPU.
|
||||
*/
|
||||
#define NV_MAX_HEADS 4
|
||||
915
nvdisplay/kernel-open/common/inc/nvmisc.h
Normal file
915
nvdisplay/kernel-open/common/inc/nvmisc.h
Normal file
@@ -0,0 +1,915 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* nvmisc.h
|
||||
*/
|
||||
#ifndef __NV_MISC_H
|
||||
#define __NV_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif //__cplusplus
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS)
|
||||
//
|
||||
// Miscellaneous macros useful for bit field manipulations
|
||||
//
|
||||
// STUPID HACK FOR CL 19434692. Will revert when fix CL is delivered bfm -> chips_a.
|
||||
#ifndef BIT
|
||||
#define BIT(b) (1U<<(b))
|
||||
#endif
|
||||
#ifndef BIT32
|
||||
#define BIT32(b) ((NvU32)1U<<(b))
|
||||
#endif
|
||||
#ifndef BIT64
|
||||
#define BIT64(b) ((NvU64)1U<<(b))
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// It is recommended to use the following bit macros to avoid macro name
|
||||
// collisions with other src code bases.
|
||||
//
|
||||
#ifndef NVBIT
|
||||
#define NVBIT(b) (1U<<(b))
|
||||
#endif
|
||||
#ifndef NVBIT_TYPE
|
||||
#define NVBIT_TYPE(b, t) (((t)1U)<<(b))
|
||||
#endif
|
||||
#ifndef NVBIT32
|
||||
#define NVBIT32(b) NVBIT_TYPE(b, NvU32)
|
||||
#endif
|
||||
#ifndef NVBIT64
|
||||
#define NVBIT64(b) NVBIT_TYPE(b, NvU64)
|
||||
#endif
|
||||
|
||||
// Helper macro's for 32 bit bitmasks
|
||||
#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3)
|
||||
#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5)
|
||||
#define NV_BITMASK32_OFFSET(chId) ((chId) & (0x1F))
|
||||
#define NV_BITMASK32_SET(pChannelMask, chId) \
|
||||
(pChannelMask)[NV_BITMASK32_IDX(chId)] |= NVBIT(NV_BITMASK32_OFFSET(chId))
|
||||
#define NV_BITMASK32_GET(pChannelMask, chId) \
|
||||
((pChannelMask)[NV_BITMASK32_IDX(chId)] & NVBIT(NV_BITMASK32_OFFSET(chId)))
|
||||
|
||||
|
||||
// Index of the 'on' bit (assuming that there is only one).
|
||||
// Even if multiple bits are 'on', result is in range of 0-31.
|
||||
#define BIT_IDX_32(n) \
|
||||
(((((n) & 0xFFFF0000U) != 0U) ? 0x10U: 0U) | \
|
||||
((((n) & 0xFF00FF00U) != 0U) ? 0x08U: 0U) | \
|
||||
((((n) & 0xF0F0F0F0U) != 0U) ? 0x04U: 0U) | \
|
||||
((((n) & 0xCCCCCCCCU) != 0U) ? 0x02U: 0U) | \
|
||||
((((n) & 0xAAAAAAAAU) != 0U) ? 0x01U: 0U) )
|
||||
|
||||
// Index of the 'on' bit (assuming that there is only one).
|
||||
// Even if multiple bits are 'on', result is in range of 0-63.
|
||||
#define BIT_IDX_64(n) \
|
||||
(((((n) & 0xFFFFFFFF00000000ULL) != 0U) ? 0x20U: 0U) | \
|
||||
((((n) & 0xFFFF0000FFFF0000ULL) != 0U) ? 0x10U: 0U) | \
|
||||
((((n) & 0xFF00FF00FF00FF00ULL) != 0U) ? 0x08U: 0U) | \
|
||||
((((n) & 0xF0F0F0F0F0F0F0F0ULL) != 0U) ? 0x04U: 0U) | \
|
||||
((((n) & 0xCCCCCCCCCCCCCCCCULL) != 0U) ? 0x02U: 0U) | \
|
||||
((((n) & 0xAAAAAAAAAAAAAAAAULL) != 0U) ? 0x01U: 0U) )
|
||||
|
||||
/*!
|
||||
* DRF MACRO README:
|
||||
*
|
||||
* Glossary:
|
||||
* DRF: Device, Register, Field
|
||||
* FLD: Field
|
||||
* REF: Reference
|
||||
*
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA 0xDEADBEEF
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_GAMMA 27:0
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA 31:28
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ZERO 0x00000000
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_ONE 0x00000001
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_TWO 0x00000002
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_THREE 0x00000003
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FOUR 0x00000004
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_FIVE 0x00000005
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SIX 0x00000006
|
||||
* #define NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA_SEVEN 0x00000007
|
||||
*
|
||||
*
|
||||
* Device = _DEVICE_OMEGA
|
||||
* This is the common "base" that a group of registers in a manual share
|
||||
*
|
||||
* Register = _REGISTER_ALPHA
|
||||
* Register for a given block of defines is the common root for one or more fields and constants
|
||||
*
|
||||
* Field(s) = _FIELD_GAMMA, _FIELD_ZETA
|
||||
* These are the bit ranges for a given field within the register
|
||||
* Fields are not required to have defined constant values (enumerations)
|
||||
*
|
||||
* Constant(s) = _ZERO, _ONE, _TWO, ...
|
||||
* These are named values (enums) a field can contain; the width of the constants should not be larger than the field width
|
||||
*
|
||||
* MACROS:
|
||||
*
|
||||
* DRF_SHIFT:
|
||||
* Bit index of the lower bound of a field
|
||||
* DRF_SHIFT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 28
|
||||
*
|
||||
* DRF_SHIFT_RT:
|
||||
* Bit index of the higher bound of a field
|
||||
* DRF_SHIFT_RT(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 31
|
||||
*
|
||||
* DRF_MASK:
|
||||
* Produces a mask of 1-s equal to the width of a field
|
||||
* DRF_MASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF (four 1s starting at bit 0)
|
||||
*
|
||||
* DRF_SHIFTMASK:
|
||||
* Produces a mask of 1s equal to the width of a field at the location of the field
|
||||
* DRF_SHIFTMASK(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 0xF0000000
|
||||
*
|
||||
* DRF_DEF:
|
||||
* Shifts a field constant's value to the correct field offset
|
||||
* DRF_DEF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE) == 0x30000000
|
||||
*
|
||||
* DRF_NUM:
|
||||
* Shifts a number to the location of a particular field
|
||||
* DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 3) == 0x30000000
|
||||
* NOTE: If the value passed in is wider than the field, the value's high bits will be truncated
|
||||
*
|
||||
* DRF_SIZE:
|
||||
* Provides the width of the field in bits
|
||||
* DRF_SIZE(NV_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA) == 4
|
||||
*
|
||||
* DRF_VAL:
|
||||
* Provides the value of an input within the field specified
|
||||
* DRF_VAL(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xABCD1234) == 0xA
|
||||
* This is sort of like the inverse of DRF_NUM
|
||||
*
|
||||
* DRF_IDX...:
|
||||
* These macros are similar to the above but for fields that accept an index argumment
|
||||
*
|
||||
* FLD_SET_DRF:
|
||||
* Set the field bits in a given value with the given field constant
|
||||
* NvU32 x = 0x00001234;
|
||||
* x = FLD_SET_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, x);
|
||||
* x == 0x30001234;
|
||||
*
|
||||
* FLD_SET_DRF_NUM:
|
||||
* Same as FLD_SET_DRF but instead of using a field constant a literal/variable is passed in
|
||||
* NvU32 x = 0x00001234;
|
||||
* x = FLD_SET_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0xF, x);
|
||||
* x == 0xF0001234;
|
||||
*
|
||||
* FLD_IDX...:
|
||||
* These macros are similar to the above but for fields that accept an index argumment
|
||||
*
|
||||
* FLD_TEST_DRF:
|
||||
* Test if location specified by drf in 'v' has the same value as NV_drfc
|
||||
* FLD_TEST_DRF(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE
|
||||
*
|
||||
* FLD_TEST_DRF_NUM:
|
||||
* Test if locations specified by drf in 'v' have the same value as n
|
||||
* FLD_TEST_DRF_NUM(_DEVICE_OMEGA, _REGISTER_ALPHA, _FIELD_ZETA, 0x3, 0x3000ABCD) == NV_TRUE
|
||||
*
|
||||
* REF_DEF:
|
||||
* Like DRF_DEF but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
|
||||
* REF_DEF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE) == 0x30000000
|
||||
*
|
||||
* REF_VAL:
|
||||
* Like DRF_VAL but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
|
||||
* REF_VAL(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xABCD1234) == 0xA
|
||||
*
|
||||
* REF_NUM:
|
||||
* Like DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
|
||||
* REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xA) == 0xA00000000
|
||||
*
|
||||
* FLD_SET_REF_NUM:
|
||||
* Like FLD_SET_DRF_NUM but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
|
||||
* NvU32 x = 0x00001234;
|
||||
* x = FLD_SET_REF_NUM(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, 0xF, x);
|
||||
* x == 0xF0001234;
|
||||
*
|
||||
* FLD_TEST_REF:
|
||||
* Like FLD_TEST_DRF but maintains full symbol name (use in cases where "NV" is not prefixed to the field)
|
||||
* FLD_TEST_REF(SOME_OTHER_PREFIX_DEVICE_OMEGA_REGISTER_ALPHA_FIELD_ZETA, _THREE, 0x3000ABCD) == NV_TRUE
|
||||
*
|
||||
* Other macros:
|
||||
* There a plethora of other macros below that extend the above (notably Multi-Word (MW), 64-bit, and some
|
||||
* reg read/write variations). I hope these are self explanatory. If you have a need to use them, you
|
||||
* probably have some knowledge of how they work.
|
||||
*/
|
||||
|
||||
// tegra mobile uses nvmisc_macros.h and can't access nvmisc.h... and sometimes both get included.
|
||||
#ifndef _NVMISC_MACROS_H
|
||||
// Use Coverity Annotation to mark issues as false positives/ignore when using single bit defines.
|
||||
#define DRF_ISBIT(bitval,drf) \
|
||||
( /* coverity[identical_branches] */ \
|
||||
(bitval != 0) ? drf )
|
||||
#define DEVICE_BASE(d) (0?d) // what's up with this name? totally non-parallel to the macros below
|
||||
#define DEVICE_EXTENT(d) (1?d) // what's up with this name? totally non-parallel to the macros below
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
#ifdef MISRA_14_3
|
||||
#define DRF_BASE(drf) (drf##_LOW_FIELD)
|
||||
#define DRF_EXTENT(drf) (drf##_HIGH_FIELD)
|
||||
#define DRF_SHIFT(drf) ((drf##_LOW_FIELD) % 32U)
|
||||
#define DRF_SHIFT_RT(drf) ((drf##_HIGH_FIELD) % 32U)
|
||||
#define DRF_MASK(drf) (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U)))
|
||||
#else
|
||||
#define DRF_BASE(drf) (NV_FALSE?drf) // much better
|
||||
#define DRF_EXTENT(drf) (NV_TRUE?drf) // much better
|
||||
#define DRF_SHIFT(drf) (((NvU32)DRF_BASE(drf)) % 32U)
|
||||
#define DRF_SHIFT_RT(drf) (((NvU32)DRF_EXTENT(drf)) % 32U)
|
||||
#define DRF_MASK(drf) (0xFFFFFFFFU>>(31U - DRF_SHIFT_RT(drf) + DRF_SHIFT(drf)))
|
||||
#endif
|
||||
#define DRF_DEF(d,r,f,c) (((NvU32)(NV ## d ## r ## f ## c))<<DRF_SHIFT(NV ## d ## r ## f))
|
||||
#define DRF_NUM(d,r,f,n) ((((NvU32)(n))&DRF_MASK(NV ## d ## r ## f))<<DRF_SHIFT(NV ## d ## r ## f))
|
||||
#else
|
||||
#define DRF_BASE(drf) (0?drf) // much better
|
||||
#define DRF_EXTENT(drf) (1?drf) // much better
|
||||
#define DRF_SHIFT(drf) ((DRF_ISBIT(0,drf)) % 32)
|
||||
#define DRF_SHIFT_RT(drf) ((DRF_ISBIT(1,drf)) % 32)
|
||||
#define DRF_MASK(drf) (0xFFFFFFFFU>>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32)))
|
||||
#define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV ## d ## r ## f))
|
||||
#define DRF_NUM(d,r,f,n) (((n)&DRF_MASK(NV ## d ## r ## f))<<DRF_SHIFT(NV ## d ## r ## f))
|
||||
#endif
|
||||
#define DRF_SHIFTMASK(drf) (DRF_MASK(drf)<<(DRF_SHIFT(drf)))
|
||||
#define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1U)
|
||||
|
||||
#define DRF_VAL(d,r,f,v) (((v)>>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f))
|
||||
#endif
|
||||
|
||||
// Signed version of DRF_VAL, which takes care of extending sign bit.
|
||||
#define DRF_VAL_SIGNED(d,r,f,v) (((DRF_VAL(d,r,f,(v)) ^ (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U)))) - (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1U)))
|
||||
#define DRF_IDX_DEF(d,r,f,i,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV##d##r##f(i)))
|
||||
#define DRF_IDX_OFFSET_DEF(d,r,f,i,o,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV##d##r##f(i,o)))
|
||||
#define DRF_IDX_NUM(d,r,f,i,n) (((n)&DRF_MASK(NV##d##r##f(i)))<<DRF_SHIFT(NV##d##r##f(i)))
|
||||
#define DRF_IDX_VAL(d,r,f,i,v) (((v)>>DRF_SHIFT(NV##d##r##f(i)))&DRF_MASK(NV##d##r##f(i)))
|
||||
#define DRF_IDX_OFFSET_VAL(d,r,f,i,o,v) (((v)>>DRF_SHIFT(NV##d##r##f(i,o)))&DRF_MASK(NV##d##r##f(i,o)))
|
||||
// Fractional version of DRF_VAL which reads Fx.y fixed point number (x.y)*z
|
||||
#define DRF_VAL_FRAC(d,r,x,y,v,z) ((DRF_VAL(d,r,x,(v))*z) + ((DRF_VAL(d,r,y,v)*z) / (1<<DRF_SIZE(NV##d##r##y))))
|
||||
|
||||
//
|
||||
// 64 Bit Versions
|
||||
//
|
||||
#define DRF_SHIFT64(drf) ((DRF_ISBIT(0,drf)) % 64)
|
||||
#define DRF_MASK64(drf) (NV_U64_MAX>>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64)))
|
||||
#define DRF_SHIFTMASK64(drf) (DRF_MASK64(drf)<<(DRF_SHIFT64(drf)))
|
||||
|
||||
#define DRF_DEF64(d,r,f,c) (((NvU64)(NV ## d ## r ## f ## c))<<DRF_SHIFT64(NV ## d ## r ## f))
|
||||
#define DRF_NUM64(d,r,f,n) ((((NvU64)(n))&DRF_MASK64(NV ## d ## r ## f))<<DRF_SHIFT64(NV ## d ## r ## f))
|
||||
#define DRF_VAL64(d,r,f,v) ((((NvU64)(v))>>DRF_SHIFT64(NV ## d ## r ## f))&DRF_MASK64(NV ## d ## r ## f))
|
||||
|
||||
#define DRF_VAL_SIGNED64(d,r,f,v) (((DRF_VAL64(d,r,f,(v)) ^ (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))) - (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))
|
||||
#define DRF_IDX_DEF64(d,r,f,i,c) (((NvU64)(NV ## d ## r ## f ## c))<<DRF_SHIFT64(NV##d##r##f(i)))
|
||||
#define DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c) ((NvU64)(NV ## d ## r ## f ## c)<<DRF_SHIFT64(NV##d##r##f(i,o)))
|
||||
#define DRF_IDX_NUM64(d,r,f,i,n) ((((NvU64)(n))&DRF_MASK64(NV##d##r##f(i)))<<DRF_SHIFT64(NV##d##r##f(i)))
|
||||
#define DRF_IDX_VAL64(d,r,f,i,v) ((((NvU64)(v))>>DRF_SHIFT64(NV##d##r##f(i)))&DRF_MASK64(NV##d##r##f(i)))
|
||||
#define DRF_IDX_OFFSET_VAL64(d,r,f,i,o,v) (((NvU64)(v)>>DRF_SHIFT64(NV##d##r##f(i,o)))&DRF_MASK64(NV##d##r##f(i,o)))
|
||||
|
||||
#define FLD_SET_DRF64(d,r,f,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c))
|
||||
#define FLD_SET_DRF_NUM64(d,r,f,n,v) ((((NvU64)(v)) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_NUM64(d,r,f,n))
|
||||
#define FLD_IDX_SET_DRF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c))
|
||||
#define FLD_IDX_OFFSET_SET_DRF64(d,r,f,i,o,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c))
|
||||
#define FLD_IDX_SET_DRF_DEF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c))
|
||||
#define FLD_IDX_SET_DRF_NUM64(d,r,f,i,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_NUM64(d,r,f,i,n))
|
||||
#define FLD_SET_DRF_IDX64(d,r,f,c,i,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c(i)))
|
||||
|
||||
#define FLD_TEST_DRF64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) == NV##d##r##f##c)
|
||||
#define FLD_TEST_DRF_AND64(d,r,f,c,v) (DRF_VAL64(d, r, f, (v)) & NV##d##r##f##c)
|
||||
#define FLD_TEST_DRF_NUM64(d,r,f,n,v) (DRF_VAL64(d, r, f, (v)) == (n))
|
||||
#define FLD_IDX_TEST_DRF64(d,r,f,i,c,v) (DRF_IDX_VAL64(d, r, f, i, (v)) == NV##d##r##f##c)
|
||||
#define FLD_IDX_OFFSET_TEST_DRF64(d,r,f,i,o,c,v) (DRF_IDX_OFFSET_VAL64(d, r, f, i, o, (v)) == NV##d##r##f##c)
|
||||
|
||||
#define REF_DEF64(drf,d) (((drf ## d)&DRF_MASK64(drf))<<DRF_SHIFT64(drf))
|
||||
#define REF_VAL64(drf,v) (((NvU64)(v)>>DRF_SHIFT64(drf))&DRF_MASK64(drf))
|
||||
#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3)
|
||||
#define REF_NUM64(drf,n) (((NvU64)(n)&(0xFFFFFFFFFFFFFFFFU>>(63U-((drf##_HIGH_FIELD) % 63U)+((drf##_LOW_FIELD) % 63U)))) << ((drf##_LOW_FIELD) % 63U))
|
||||
#else
|
||||
#define REF_NUM64(drf,n) (((NvU64)(n)&DRF_MASK64(drf))<<DRF_SHIFT64(drf))
|
||||
#endif
|
||||
#define FLD_TEST_REF64(drf,c,v) (REF_VAL64(drf, v) == drf##c)
|
||||
#define FLD_TEST_REF_AND64(drf,c,v) (REF_VAL64(drf, v) & drf##c)
|
||||
#define FLD_SET_REF_NUM64(drf,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(drf)) | REF_NUM64(drf,n))
|
||||
|
||||
//
|
||||
// 32 Bit Versions
|
||||
//
|
||||
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
#define FLD_SET_DRF(d,r,f,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c))
|
||||
#define FLD_SET_DRF_NUM(d,r,f,n,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_NUM(d,r,f,n))
|
||||
#define FLD_IDX_SET_DRF(d,r,f,i,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
|
||||
#define FLD_IDX_OFFSET_SET_DRF(d,r,f,i,o,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF(d,r,f,i,o,c))
|
||||
#define FLD_IDX_SET_DRF_DEF(d,r,f,i,c,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
|
||||
#define FLD_IDX_SET_DRF_NUM(d,r,f,i,n,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_NUM(d,r,f,i,n))
|
||||
#define FLD_SET_DRF_IDX(d,r,f,c,i,v) (((NvU32)(v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c(i)))
|
||||
|
||||
#define FLD_TEST_DRF(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) == (NvU32)(NV##d##r##f##c)))
|
||||
#define FLD_TEST_DRF_AND(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) & (NvU32)(NV##d##r##f##c)) != 0U)
|
||||
#define FLD_TEST_DRF_NUM(d,r,f,n,v) ((DRF_VAL(d, r, f, (v)) == (NvU32)(n)))
|
||||
#define FLD_IDX_TEST_DRF(d,r,f,i,c,v) ((DRF_IDX_VAL(d, r, f, i, (v)) == (NvU32)(NV##d##r##f##c)))
|
||||
#define FLD_IDX_OFFSET_TEST_DRF(d,r,f,i,o,c,v) ((DRF_IDX_OFFSET_VAL(d, r, f, i, o, (v)) == (NvU32)(NV##d##r##f##c)))
|
||||
#else
|
||||
#define FLD_SET_DRF(d,r,f,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c))
|
||||
#define FLD_SET_DRF_NUM(d,r,f,n,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_NUM(d,r,f,n))
|
||||
#define FLD_IDX_SET_DRF(d,r,f,i,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
|
||||
#define FLD_IDX_OFFSET_SET_DRF(d,r,f,i,o,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF(d,r,f,i,o,c))
|
||||
#define FLD_IDX_SET_DRF_DEF(d,r,f,i,c,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
|
||||
#define FLD_IDX_SET_DRF_NUM(d,r,f,i,n,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_NUM(d,r,f,i,n))
|
||||
#define FLD_SET_DRF_IDX(d,r,f,c,i,v) (((v) & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c(i)))
|
||||
|
||||
#define FLD_TEST_DRF(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) == NV##d##r##f##c))
|
||||
#define FLD_TEST_DRF_AND(d,r,f,c,v) ((DRF_VAL(d, r, f, (v)) & NV##d##r##f##c))
|
||||
#define FLD_TEST_DRF_NUM(d,r,f,n,v) ((DRF_VAL(d, r, f, (v)) == (n)))
|
||||
#define FLD_IDX_TEST_DRF(d,r,f,i,c,v) ((DRF_IDX_VAL(d, r, f, i, (v)) == NV##d##r##f##c))
|
||||
#define FLD_IDX_OFFSET_TEST_DRF(d,r,f,i,o,c,v) ((DRF_IDX_OFFSET_VAL(d, r, f, i, o, (v)) == NV##d##r##f##c))
|
||||
#endif
|
||||
|
||||
#define REF_DEF(drf,d) (((drf ## d)&DRF_MASK(drf))<<DRF_SHIFT(drf))
|
||||
#define REF_VAL(drf,v) (((v)>>DRF_SHIFT(drf))&DRF_MASK(drf))
|
||||
#if defined(NV_MISRA_COMPLIANCE_REQUIRED) && defined(MISRA_14_3)
|
||||
#define REF_NUM(drf,n) (((n)&(0xFFFFFFFFU>>(31U-((drf##_HIGH_FIELD) % 32U)+((drf##_LOW_FIELD) % 32U)))) << ((drf##_LOW_FIELD) % 32U))
|
||||
#else
|
||||
#define REF_NUM(drf,n) (((n)&DRF_MASK(drf))<<DRF_SHIFT(drf))
|
||||
#endif
|
||||
#define FLD_TEST_REF(drf,c,v) (REF_VAL(drf, (v)) == drf##c)
|
||||
#define FLD_TEST_REF_AND(drf,c,v) (REF_VAL(drf, (v)) & drf##c)
|
||||
#define FLD_SET_REF_NUM(drf,n,v) (((v) & ~DRF_SHIFTMASK(drf)) | REF_NUM(drf,n))
|
||||
|
||||
#define CR_DRF_DEF(d,r,f,c) ((CR ## d ## r ## f ## c)<<DRF_SHIFT(CR ## d ## r ## f))
|
||||
#define CR_DRF_NUM(d,r,f,n) (((n)&DRF_MASK(CR ## d ## r ## f))<<DRF_SHIFT(CR ## d ## r ## f))
|
||||
#define CR_DRF_VAL(d,r,f,v) (((v)>>DRF_SHIFT(CR ## d ## r ## f))&DRF_MASK(CR ## d ## r ## f))
|
||||
|
||||
// Multi-word (MW) field manipulations. For multi-word structures (e.g., Fermi SPH),
|
||||
// fields may have bit numbers beyond 32. To avoid errors using "classic" multi-word macros,
|
||||
// all the field extents are defined as "MW(X)". For example, MW(127:96) means
|
||||
// the field is in bits 0-31 of word number 3 of the structure.
|
||||
//
|
||||
// DRF_VAL_MW() macro is meant to be used for native endian 32-bit aligned 32-bit word data,
|
||||
// not for byte stream data.
|
||||
//
|
||||
// DRF_VAL_BS() macro is for byte stream data used in fbQueryBIOS_XXX().
|
||||
//
|
||||
#define DRF_EXPAND_MW(drf) drf // used to turn "MW(a:b)" into "a:b"
|
||||
#define DRF_PICK_MW(drf,v) ((v)? DRF_EXPAND_##drf) // picks low or high bits
|
||||
#define DRF_WORD_MW(drf) (DRF_PICK_MW(drf,0)/32) // which word in a multi-word array
|
||||
#define DRF_BASE_MW(drf) (DRF_PICK_MW(drf,0)%32) // which start bit in the selected word?
|
||||
#define DRF_EXTENT_MW(drf) (DRF_PICK_MW(drf,1)%32) // which end bit in the selected word
|
||||
#define DRF_SHIFT_MW(drf) (DRF_PICK_MW(drf,0)%32)
|
||||
#define DRF_MASK_MW(drf) (0xFFFFFFFFU>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32))
|
||||
#define DRF_SHIFTMASK_MW(drf) ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf)))
|
||||
#define DRF_SIZE_MW(drf) (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1)
|
||||
|
||||
#define DRF_DEF_MW(d,r,f,c) ((NV##d##r##f##c) << DRF_SHIFT_MW(NV##d##r##f))
|
||||
#define DRF_NUM_MW(d,r,f,n) (((n)&DRF_MASK_MW(NV##d##r##f))<<DRF_SHIFT_MW(NV##d##r##f))
|
||||
//
|
||||
// DRF_VAL_MW is the ONLY multi-word macro which supports spanning. No other MW macro supports spanning currently
|
||||
//
|
||||
#define DRF_VAL_MW_1WORD(d,r,f,v) ((((v)[DRF_WORD_MW(NV##d##r##f)])>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f))
|
||||
#define DRF_SPANS(drf) ((DRF_PICK_MW(drf,0)/32) != (DRF_PICK_MW(drf,1)/32))
|
||||
#define DRF_WORD_MW_LOW(drf) (DRF_PICK_MW(drf,0)/32)
|
||||
#define DRF_WORD_MW_HIGH(drf) (DRF_PICK_MW(drf,1)/32)
|
||||
#define DRF_MASK_MW_LOW(drf) (0xFFFFFFFFU)
|
||||
#define DRF_MASK_MW_HIGH(drf) (0xFFFFFFFFU>>(31-(DRF_EXTENT_MW(drf))))
|
||||
#define DRF_SHIFT_MW_LOW(drf) (DRF_PICK_MW(drf,0)%32)
|
||||
#define DRF_SHIFT_MW_HIGH(drf) (0)
|
||||
#define DRF_MERGE_SHIFT(drf) ((32-((DRF_PICK_MW(drf,0)%32)))%32)
|
||||
#define DRF_VAL_MW_2WORD(d,r,f,v) (((((v)[DRF_WORD_MW_LOW(NV##d##r##f)])>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \
|
||||
(((((v)[DRF_WORD_MW_HIGH(NV##d##r##f)])>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f)))
|
||||
#define DRF_VAL_MW(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_MW_2WORD(d,r,f,v) : DRF_VAL_MW_1WORD(d,r,f,v) )
|
||||
|
||||
#define DRF_IDX_DEF_MW(d,r,f,i,c) ((NV##d##r##f##c)<<DRF_SHIFT_MW(NV##d##r##f(i)))
|
||||
#define DRF_IDX_NUM_MW(d,r,f,i,n) (((n)&DRF_MASK_MW(NV##d##r##f(i)))<<DRF_SHIFT_MW(NV##d##r##f(i)))
|
||||
#define DRF_IDX_VAL_MW(d,r,f,i,v) ((((v)[DRF_WORD_MW(NV##d##r##f(i))])>>DRF_SHIFT_MW(NV##d##r##f(i)))&DRF_MASK_MW(NV##d##r##f(i)))
|
||||
|
||||
//
|
||||
// Logically OR all DRF_DEF constants indexed from zero to s (semiinclusive).
|
||||
// Caution: Target variable v must be pre-initialized.
|
||||
//
|
||||
#define FLD_IDX_OR_DRF_DEF(d,r,f,c,s,v) \
|
||||
do \
|
||||
{ NvU32 idx; \
|
||||
for (idx = 0; idx < (NV ## d ## r ## f ## s); ++idx)\
|
||||
{ \
|
||||
v |= DRF_IDX_DEF(d,r,f,idx,c); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
|
||||
#define FLD_MERGE_MW(drf,n,v) (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n)
|
||||
#define FLD_ASSIGN_MW(drf,n,v) ((v)[DRF_WORD_MW(drf)] = FLD_MERGE_MW(drf, n, v))
|
||||
#define FLD_IDX_MERGE_MW(drf,i,n,v) (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n)
|
||||
#define FLD_IDX_ASSIGN_MW(drf,i,n,v) ((v)[DRF_WORD_MW(drf(i))] = FLD_MERGE_MW(drf(i), n, v))
|
||||
|
||||
#define FLD_SET_DRF_MW(d,r,f,c,v) FLD_MERGE_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v)
|
||||
#define FLD_SET_DRF_NUM_MW(d,r,f,n,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_NUM_MW(d,r,f,n), v)
|
||||
#define FLD_SET_DRF_DEF_MW(d,r,f,c,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v)
|
||||
#define FLD_IDX_SET_DRF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v)
|
||||
#define FLD_IDX_SET_DRF_DEF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v)
|
||||
#define FLD_IDX_SET_DRF_NUM_MW(d,r,f,i,n,v) FLD_IDX_ASSIGN_MW(NV##d##r##f, i, DRF_IDX_NUM_MW(d,r,f,i,n), v)
|
||||
|
||||
#define FLD_TEST_DRF_MW(d,r,f,c,v) ((DRF_VAL_MW(d, r, f, (v)) == NV##d##r##f##c))
|
||||
#define FLD_TEST_DRF_NUM_MW(d,r,f,n,v) ((DRF_VAL_MW(d, r, f, (v)) == n))
|
||||
#define FLD_IDX_TEST_DRF_MW(d,r,f,i,c,v) ((DRF_IDX_VAL_MW(d, r, f, i, (v)) == NV##d##r##f##c))
|
||||
|
||||
#define DRF_VAL_BS(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_BS_2WORD(d,r,f,(v)) : DRF_VAL_BS_1WORD(d,r,f,(v)) )
|
||||
|
||||
//------------------------------------------------------------------------//
|
||||
// //
|
||||
// Common defines for engine register reference wrappers //
|
||||
// //
|
||||
// New engine addressing can be created like: //
|
||||
// \#define ENG_REG_PMC(o,d,r) NV##d##r //
|
||||
// \#define ENG_IDX_REG_CE(o,d,i,r) CE_MAP(o,r,i) //
|
||||
// //
|
||||
// See FB_FBPA* for more examples //
|
||||
//------------------------------------------------------------------------//
|
||||
|
||||
#define ENG_RD_REG(g,o,d,r) GPU_REG_RD32(g, ENG_REG##d(o,d,r))
|
||||
#define ENG_WR_REG(g,o,d,r,v) GPU_REG_WR32(g, ENG_REG##d(o,d,r), (v))
|
||||
#define ENG_RD_DRF(g,o,d,r,f) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
|
||||
#define ENG_WR_DRF_DEF(g,o,d,r,f,c) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<<GPU_DRF_SHIFT(NV##d##r##f)))|GPU_DRF_DEF(d,r,f,c))
|
||||
#define ENG_WR_DRF_NUM(g,o,d,r,f,n) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<<GPU_DRF_SHIFT(NV##d##r##f)))|GPU_DRF_NUM(d,r,f,n))
|
||||
#define ENG_TEST_DRF_DEF(g,o,d,r,f,c) (ENG_RD_DRF(g, o, d, r, f) == NV##d##r##f##c)
|
||||
|
||||
#define ENG_RD_IDX_DRF(g,o,d,r,f,i) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
|
||||
#define ENG_TEST_IDX_DRF_DEF(g,o,d,r,f,c,i) (ENG_RD_IDX_DRF(g, o, d, r, f, (i)) == NV##d##r##f##c)
|
||||
|
||||
#define ENG_IDX_RD_REG(g,o,d,i,r) GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))
|
||||
#define ENG_IDX_WR_REG(g,o,d,i,r,v) GPU_REG_WR32(g, ENG_IDX_REG##d(o,d,i,r), (v))
|
||||
|
||||
#define ENG_IDX_RD_DRF(g,o,d,i,r,f) ((GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
|
||||
|
||||
//
|
||||
// DRF_READ_1WORD_BS() and DRF_READ_1WORD_BS_HIGH() do not read beyond the bytes that contain
|
||||
// the requested value. Reading beyond the actual data causes a page fault panic when the
|
||||
// immediately following page happened to be protected or not mapped.
|
||||
//
|
||||
#define DRF_VAL_BS_1WORD(d,r,f,v) ((DRF_READ_1WORD_BS(d,r,f,v)>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f))
|
||||
#define DRF_VAL_BS_2WORD(d,r,f,v) (((DRF_READ_4BYTE_BS(NV##d##r##f,v)>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \
|
||||
(((DRF_READ_1WORD_BS_HIGH(d,r,f,v)>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f)))
|
||||
|
||||
#define DRF_READ_1BYTE_BS(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4]))
|
||||
#define DRF_READ_2BYTE_BS(drf,v) (DRF_READ_1BYTE_BS(drf,v)| \
|
||||
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+1])<<8))
|
||||
#define DRF_READ_3BYTE_BS(drf,v) (DRF_READ_2BYTE_BS(drf,v)| \
|
||||
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+2])<<16))
|
||||
#define DRF_READ_4BYTE_BS(drf,v) (DRF_READ_3BYTE_BS(drf,v)| \
|
||||
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+3])<<24))
|
||||
|
||||
#define DRF_READ_1BYTE_BS_HIGH(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4]))
|
||||
#define DRF_READ_2BYTE_BS_HIGH(drf,v) (DRF_READ_1BYTE_BS_HIGH(drf,v)| \
|
||||
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+1])<<8))
|
||||
#define DRF_READ_3BYTE_BS_HIGH(drf,v) (DRF_READ_2BYTE_BS_HIGH(drf,v)| \
|
||||
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+2])<<16))
|
||||
#define DRF_READ_4BYTE_BS_HIGH(drf,v) (DRF_READ_3BYTE_BS_HIGH(drf,v)| \
|
||||
((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+3])<<24))
|
||||
|
||||
// Calculate 2^n - 1 and avoid shift counter overflow
|
||||
//
|
||||
// On Windows amd64, 64 << 64 => 1
|
||||
//
|
||||
#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1)
|
||||
|
||||
#define DRF_READ_1WORD_BS(d,r,f,v) \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS(NV##d##r##f,(v)): \
|
||||
DRF_READ_4BYTE_BS(NV##d##r##f,(v)))))
|
||||
|
||||
#define DRF_READ_1WORD_BS_HIGH(d,r,f,v) \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS_HIGH(NV##d##r##f,(v)): \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS_HIGH(NV##d##r##f,(v)): \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS_HIGH(NV##d##r##f,(v)): \
|
||||
DRF_READ_4BYTE_BS_HIGH(NV##d##r##f,(v)))))
|
||||
|
||||
#define LOWESTBIT(x) ( (x) & (((x) - 1U) ^ (x)) )
|
||||
// Destructive operation on n32
|
||||
#define HIGHESTBIT(n32) \
|
||||
{ \
|
||||
HIGHESTBITIDX_32(n32); \
|
||||
n32 = NVBIT(n32); \
|
||||
}
|
||||
#define ONEBITSET(x) ( ((x) != 0U) && (((x) & ((x) - 1U)) == 0U) )
|
||||
|
||||
// Destructive operation on n32
|
||||
#define NUMSETBITS_32(n32) \
|
||||
{ \
|
||||
n32 = n32 - ((n32 >> 1) & 0x55555555); \
|
||||
n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \
|
||||
n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \
|
||||
}
|
||||
|
||||
/*!
|
||||
* Calculate number of bits set in a 32-bit unsigned integer.
|
||||
* Pure typesafe alternative to @ref NUMSETBITS_32.
|
||||
*/
|
||||
static NV_FORCEINLINE NvU32
|
||||
nvPopCount32(const NvU32 x)
|
||||
{
|
||||
NvU32 temp = x;
|
||||
temp = temp - ((temp >> 1) & 0x55555555U);
|
||||
temp = (temp & 0x33333333U) + ((temp >> 2) & 0x33333333U);
|
||||
temp = (((temp + (temp >> 4)) & 0x0F0F0F0FU) * 0x01010101U) >> 24;
|
||||
return temp;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Calculate number of bits set in a 64-bit unsigned integer.
|
||||
*/
|
||||
static NV_FORCEINLINE NvU32
|
||||
nvPopCount64(const NvU64 x)
|
||||
{
|
||||
NvU64 temp = x;
|
||||
temp = temp - ((temp >> 1) & 0x5555555555555555ULL);
|
||||
temp = (temp & 0x3333333333333333ULL) + ((temp >> 2) & 0x3333333333333333ULL);
|
||||
temp = (temp + (temp >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
|
||||
temp = (temp * 0x0101010101010101ULL) >> 56;
|
||||
return (NvU32)temp;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Determine how many bits are set below a bit index within a mask.
|
||||
* This assigns a dense ordering to the set bits in the mask.
|
||||
*
|
||||
* For example the mask 0xCD contains 5 set bits:
|
||||
* nvMaskPos32(0xCD, 0) == 0
|
||||
* nvMaskPos32(0xCD, 2) == 1
|
||||
* nvMaskPos32(0xCD, 3) == 2
|
||||
* nvMaskPos32(0xCD, 6) == 3
|
||||
* nvMaskPos32(0xCD, 7) == 4
|
||||
*/
|
||||
static NV_FORCEINLINE NvU32
|
||||
nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
|
||||
{
|
||||
return nvPopCount32(mask & (NVBIT32(bitIdx) - 1U));
|
||||
}
|
||||
|
||||
// Destructive operation on n32
|
||||
#define LOWESTBITIDX_32(n32) \
|
||||
{ \
|
||||
n32 = BIT_IDX_32(LOWESTBIT(n32));\
|
||||
}
|
||||
|
||||
// Destructive operation on n32
|
||||
#define HIGHESTBITIDX_32(n32) \
|
||||
{ \
|
||||
NvU32 count = 0; \
|
||||
while (n32 >>= 1) \
|
||||
{ \
|
||||
count++; \
|
||||
} \
|
||||
n32 = count; \
|
||||
}
|
||||
|
||||
// Destructive operation on n32
|
||||
#define ROUNDUP_POW2(n32) \
|
||||
{ \
|
||||
n32--; \
|
||||
n32 |= n32 >> 1; \
|
||||
n32 |= n32 >> 2; \
|
||||
n32 |= n32 >> 4; \
|
||||
n32 |= n32 >> 8; \
|
||||
n32 |= n32 >> 16; \
|
||||
n32++; \
|
||||
}
|
||||
|
||||
/*!
|
||||
* Round up a 32-bit unsigned integer to the next power of 2.
|
||||
* Pure typesafe alternative to @ref ROUNDUP_POW2.
|
||||
*
|
||||
* param[in] x must be in range [0, 2^31] to avoid overflow.
|
||||
*/
|
||||
static NV_FORCEINLINE NvU32
|
||||
nvNextPow2_U32(const NvU32 x)
|
||||
{
|
||||
NvU32 y = x;
|
||||
y--;
|
||||
y |= y >> 1;
|
||||
y |= y >> 2;
|
||||
y |= y >> 4;
|
||||
y |= y >> 8;
|
||||
y |= y >> 16;
|
||||
y++;
|
||||
return y;
|
||||
}
|
||||
|
||||
|
||||
static NV_FORCEINLINE NvU32
|
||||
nvPrevPow2_U32(const NvU32 x )
|
||||
{
|
||||
NvU32 y = x;
|
||||
y |= (y >> 1);
|
||||
y |= (y >> 2);
|
||||
y |= (y >> 4);
|
||||
y |= (y >> 8);
|
||||
y |= (y >> 16);
|
||||
return y - (y >> 1);
|
||||
}
|
||||
|
||||
static NV_FORCEINLINE NvU64
|
||||
nvPrevPow2_U64(const NvU64 x )
|
||||
{
|
||||
NvU64 y = x;
|
||||
y |= (y >> 1);
|
||||
y |= (y >> 2);
|
||||
y |= (y >> 4);
|
||||
y |= (y >> 8);
|
||||
y |= (y >> 16);
|
||||
y |= (y >> 32);
|
||||
return y - (y >> 1);
|
||||
}
|
||||
|
||||
// Destructive operation on n64
|
||||
#define ROUNDUP_POW2_U64(n64) \
|
||||
{ \
|
||||
n64--; \
|
||||
n64 |= n64 >> 1; \
|
||||
n64 |= n64 >> 2; \
|
||||
n64 |= n64 >> 4; \
|
||||
n64 |= n64 >> 8; \
|
||||
n64 |= n64 >> 16; \
|
||||
n64 |= n64 >> 32; \
|
||||
n64++; \
|
||||
}
|
||||
|
||||
#define NV_SWAP_U8(a,b) \
|
||||
{ \
|
||||
NvU8 temp; \
|
||||
temp = a; \
|
||||
a = b; \
|
||||
b = temp; \
|
||||
}
|
||||
|
||||
#define NV_SWAP_U32(a,b) \
|
||||
{ \
|
||||
NvU32 temp; \
|
||||
temp = a; \
|
||||
a = b; \
|
||||
b = temp; \
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Macros allowing simple iteration over bits set in a given mask.
|
||||
*
|
||||
* @param[in] maskWidth bit-width of the mask (allowed: 8, 16, 32, 64)
|
||||
*
|
||||
* @param[in,out] index lvalue that is used as a bit index in the loop
|
||||
* (can be declared as any NvU* or NvS* variable)
|
||||
* @param[in] mask expression, loop will iterate over set bits only
|
||||
*/
|
||||
#define FOR_EACH_INDEX_IN_MASK(maskWidth,index,mask) \
|
||||
{ \
|
||||
NvU##maskWidth lclMsk = (NvU##maskWidth)(mask); \
|
||||
for ((index) = 0U; lclMsk != 0U; (index)++, lclMsk >>= 1U)\
|
||||
{ \
|
||||
if (((NvU##maskWidth)NVBIT64(0) & lclMsk) == 0U) \
|
||||
{ \
|
||||
continue; \
|
||||
}
|
||||
#define FOR_EACH_INDEX_IN_MASK_END \
|
||||
} \
|
||||
}
|
||||
|
||||
//
|
||||
// Size to use when declaring variable-sized arrays
|
||||
//
|
||||
#define NV_ANYSIZE_ARRAY 1
|
||||
|
||||
//
|
||||
// Returns ceil(a/b)
|
||||
//
|
||||
#define NV_CEIL(a,b) (((a)+(b)-1)/(b))
|
||||
|
||||
// Clearer name for NV_CEIL
|
||||
#ifndef NV_DIV_AND_CEIL
|
||||
#define NV_DIV_AND_CEIL(a, b) NV_CEIL(a,b)
|
||||
#endif
|
||||
|
||||
#ifndef NV_MIN
|
||||
#define NV_MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#ifndef NV_MAX
|
||||
#define NV_MAX(a, b) (((a) > (b)) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
//
|
||||
// Returns absolute value of provided integer expression
|
||||
//
|
||||
#define NV_ABS(a) ((a)>=0?(a):(-(a)))
|
||||
|
||||
//
|
||||
// Returns 1 if input number is positive, 0 if 0 and -1 if negative. Avoid
|
||||
// macro parameter as function call which will have side effects.
|
||||
//
|
||||
#define NV_SIGN(s) ((NvS8)(((s) > 0) - ((s) < 0)))
|
||||
|
||||
//
|
||||
// Returns 1 if input number is >= 0 or -1 otherwise. This assumes 0 has a
|
||||
// positive sign.
|
||||
//
|
||||
#define NV_ZERO_SIGN(s) ((NvS8)((((s) >= 0) * 2) - 1))
|
||||
|
||||
// Returns the offset (in bytes) of 'member' in struct 'type'.
|
||||
#ifndef NV_OFFSETOF
|
||||
#if defined(__GNUC__) && (__GNUC__ > 3)
|
||||
#define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member))
|
||||
#else
|
||||
#define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header.
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//
|
||||
// Performs a rounded division of b into a (unsigned). For SIGNED version of
|
||||
// NV_ROUNDED_DIV() macro check the comments in bug 769777.
|
||||
//
|
||||
#define NV_UNSIGNED_ROUNDED_DIV(a,b) (((a) + ((b) / 2U)) / (b))
|
||||
|
||||
/*!
|
||||
* Performs a ceiling division of b into a (unsigned). A "ceiling" division is
|
||||
* a division is one with rounds up result up if a % b != 0.
|
||||
*
|
||||
* @param[in] a Numerator
|
||||
* @param[in] b Denominator
|
||||
*
|
||||
* @return a / b + a % b != 0 ? 1 : 0.
|
||||
*/
|
||||
#define NV_UNSIGNED_DIV_CEIL(a, b) (((a) + (b - 1)) / (b))
|
||||
|
||||
/*!
|
||||
* Performs subtraction where a negative difference is raised to zero.
|
||||
* Can be used to avoid underflowing an unsigned subtraction.
|
||||
*
|
||||
* @param[in] a Minuend
|
||||
* @param[in] b Subtrahend
|
||||
*
|
||||
* @return a > b ? a - b : 0.
|
||||
*/
|
||||
#define NV_SUBTRACT_NO_UNDERFLOW(a, b) ((a)>(b) ? (a)-(b) : 0)
|
||||
|
||||
/*!
|
||||
* Performs a rounded right-shift of 32-bit unsigned value "a" by "shift" bits.
|
||||
* Will round result away from zero.
|
||||
*
|
||||
* @param[in] a 32-bit unsigned value to shift.
|
||||
* @param[in] shift Number of bits by which to shift.
|
||||
*
|
||||
* @return Resulting shifted value rounded away from zero.
|
||||
*/
|
||||
#define NV_RIGHT_SHIFT_ROUNDED(a, shift) \
|
||||
(((a) >> (shift)) + !!((NVBIT((shift) - 1) & (a)) == NVBIT((shift) - 1)))
|
||||
|
||||
//
|
||||
// Power of 2 alignment.
|
||||
// (Will give unexpected results if 'gran' is not a power of 2.)
|
||||
//
|
||||
#ifndef NV_ALIGN_DOWN
|
||||
//
|
||||
// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type.
|
||||
// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed.
|
||||
//
|
||||
#define NV_ALIGN_DOWN(v, gran) ((v) & ~((v) - (v) + (gran) - 1))
|
||||
#endif
|
||||
|
||||
#ifndef NV_ALIGN_UP
|
||||
//
|
||||
// Notably using v - v + gran ensures gran gets promoted to the same type as v if gran has a smaller type.
|
||||
// Otherwise, if aligning a NVU64 with NVU32 granularity, the top 4 bytes get zeroed.
|
||||
//
|
||||
#define NV_ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((v) - (v) + (gran) - 1))
|
||||
#endif
|
||||
|
||||
#ifndef NV_ALIGN_DOWN64
|
||||
#define NV_ALIGN_DOWN64(v, gran) ((v) & ~(((NvU64)gran) - 1))
|
||||
#endif
|
||||
|
||||
#ifndef NV_ALIGN_UP64
|
||||
#define NV_ALIGN_UP64(v, gran) (((v) + ((gran) - 1)) & ~(((NvU64)gran)-1))
|
||||
#endif
|
||||
|
||||
#ifndef NV_IS_ALIGNED
|
||||
#define NV_IS_ALIGNED(v, gran) (0U == ((v) & ((gran) - 1U)))
|
||||
#endif
|
||||
|
||||
#ifndef NV_IS_ALIGNED64
|
||||
#define NV_IS_ALIGNED64(v, gran) (0U == ((v) & (((NvU64)gran) - 1U)))
|
||||
#endif
|
||||
|
||||
#ifndef NVMISC_MEMSET
|
||||
static NV_FORCEINLINE void *NVMISC_MEMSET(void *s, NvU8 c, NvLength n)
|
||||
{
|
||||
NvU8 *b = (NvU8 *) s;
|
||||
NvLength i;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
{
|
||||
b[i] = c;
|
||||
}
|
||||
|
||||
return s;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef NVMISC_MEMCPY
|
||||
static NV_FORCEINLINE void *NVMISC_MEMCPY(void *dest, const void *src, NvLength n)
|
||||
{
|
||||
NvU8 *destByte = (NvU8 *) dest;
|
||||
const NvU8 *srcByte = (const NvU8 *) src;
|
||||
NvLength i;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
{
|
||||
destByte[i] = srcByte[i];
|
||||
}
|
||||
|
||||
return dest;
|
||||
}
|
||||
#endif
|
||||
|
||||
static NV_FORCEINLINE char *NVMISC_STRNCPY(char *dest, const char *src, NvLength n)
|
||||
{
|
||||
NvLength i;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
{
|
||||
dest[i] = src[i];
|
||||
if (src[i] == '\0')
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (; i < n; i++)
|
||||
{
|
||||
dest[i] = '\0';
|
||||
}
|
||||
|
||||
return dest;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Convert a void* to an NvUPtr. This is used when MISRA forbids us from doing a direct cast.
|
||||
*
|
||||
* @param[in] ptr Pointer to be converted
|
||||
*
|
||||
* @return Resulting NvUPtr
|
||||
*/
|
||||
static NV_FORCEINLINE NvUPtr NV_PTR_TO_NVUPTR(void *ptr)
|
||||
{
|
||||
union
|
||||
{
|
||||
NvUPtr v;
|
||||
void *p;
|
||||
} uAddr;
|
||||
|
||||
uAddr.p = ptr;
|
||||
return uAddr.v;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Convert an NvUPtr to a void*. This is used when MISRA forbids us from doing a direct cast.
|
||||
*
|
||||
* @param[in] ptr Pointer to be converted
|
||||
*
|
||||
* @return Resulting void *
|
||||
*/
|
||||
static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
|
||||
{
|
||||
union
|
||||
{
|
||||
NvUPtr v;
|
||||
void *p;
|
||||
} uAddr;
|
||||
|
||||
uAddr.v = address;
|
||||
return uAddr.p;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif //__cplusplus
|
||||
|
||||
#endif // __NV_MISC_H
|
||||
|
||||
123
nvdisplay/kernel-open/common/inc/nvstatus.h
Normal file
123
nvdisplay/kernel-open/common/inc/nvstatus.h
Normal file
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef SDK_NVSTATUS_H
|
||||
#define SDK_NVSTATUS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
typedef NvU32 NV_STATUS;
|
||||
|
||||
#define NV_STATUS_CODE( name, code, string ) name = (code),
|
||||
|
||||
enum
|
||||
{
|
||||
#include "nvstatuscodes.h"
|
||||
};
|
||||
|
||||
#undef NV_STATUS_CODE
|
||||
|
||||
/*!
|
||||
* @def NV_STATUS_LEVEL_OK
|
||||
* @see NV_STATUS_LEVEL
|
||||
* @brief Success: No error or special condition
|
||||
*/
|
||||
#define NV_STATUS_LEVEL_OK 0
|
||||
|
||||
/*!
|
||||
* @def NV_STATUS_LEVEL_WARN
|
||||
* @see NV_STATUS_LEVEL
|
||||
* @brief Success, but there is an special condition
|
||||
*
|
||||
* @details In general, NV_STATUS_LEVEL_WARN status codes are handled the
|
||||
* same as NV_STATUS_LEVEL_OK, but are usefil to indicate that
|
||||
* there is a condition that may be specially handled.
|
||||
*
|
||||
* Therefore, in most cases, client function should test for
|
||||
* status <= NV_STATUS_LEVEL_WARN or status > NV_STATUS_LEVEL_WARN
|
||||
* to determine success v. failure of a call.
|
||||
*/
|
||||
#define NV_STATUS_LEVEL_WARN 1
|
||||
|
||||
/*!
|
||||
* @def NV_STATUS_LEVEL_ERR
|
||||
* @see NV_STATUS_LEVEL
|
||||
* @brief Unrecoverable error condition
|
||||
*/
|
||||
#define NV_STATUS_LEVEL_ERR 3
|
||||
|
||||
/*!
|
||||
* @def NV_STATUS_LEVEL
|
||||
* @see NV_STATUS_LEVEL_OK
|
||||
* @see NV_STATUS_LEVEL_WARN
|
||||
* @see NV_STATUS_LEVEL_ERR
|
||||
* @brief Level of the status code
|
||||
*
|
||||
* @warning IMPORTANT: When comparing NV_STATUS_LEVEL(_S) against one of
|
||||
* these constants, it is important to use '<=' or '>' (rather
|
||||
* than '<' or '>=').
|
||||
*
|
||||
* For example. do:
|
||||
* if (NV_STATUS_LEVEL(status) <= NV_STATUS_LEVEL_WARN)
|
||||
* rather than:
|
||||
* if (NV_STATUS_LEVEL(status) < NV_STATUS_LEVEL_ERR)
|
||||
*
|
||||
* By being consistent in this manner, it is easier to systematically
|
||||
* add additional level constants. New levels are likely to lower
|
||||
* (rather than raise) the severity of _ERR codes. For example,
|
||||
* if we were to add NV_STATUS_LEVEL_RETRY to indicate hardware
|
||||
* failures that may be recoverable (e.g. RM_ERR_TIMEOUT_RETRY
|
||||
* or RM_ERR_BUSY_RETRY), it would be less severe than
|
||||
* NV_STATUS_LEVEL_ERR the level to which these status codes now
|
||||
* belong. Using '<=' and '>' ensures your code is not broken in
|
||||
* cases like this.
|
||||
*/
|
||||
#define NV_STATUS_LEVEL(_S) \
|
||||
((_S) == NV_OK? NV_STATUS_LEVEL_OK: \
|
||||
((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? NV_STATUS_LEVEL_WARN: \
|
||||
NV_STATUS_LEVEL_ERR))
|
||||
|
||||
/*!
|
||||
* @def NV_STATUS_LEVEL
|
||||
* @see NV_STATUS_LEVEL_OK
|
||||
* @see NV_STATUS_LEVEL_WARN
|
||||
* @see NV_STATUS_LEVEL_ERR
|
||||
* @brief Character representing status code level
|
||||
*/
|
||||
#define NV_STATUS_LEVEL_CHAR(_S) \
|
||||
((_S) == NV_OK? '0': \
|
||||
((_S) != NV_ERR_GENERIC && (_S) & 0x00010000? 'W': \
|
||||
'E'))
|
||||
|
||||
// Function definitions
|
||||
const char *nvstatusToString(NV_STATUS nvStatusIn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SDK_NVSTATUS_H */
|
||||
162
nvdisplay/kernel-open/common/inc/nvstatuscodes.h
Normal file
162
nvdisplay/kernel-open/common/inc/nvstatuscodes.h
Normal file
@@ -0,0 +1,162 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef SDK_NVSTATUSCODES_H
|
||||
#define SDK_NVSTATUSCODES_H
|
||||
|
||||
NV_STATUS_CODE(NV_OK, 0x00000000, "Success")
|
||||
NV_STATUS_CODE(NV_ERR_GENERIC, 0x0000FFFF, "Failure: Generic Error")
|
||||
|
||||
NV_STATUS_CODE(NV_ERR_BROKEN_FB, 0x00000001, "Frame-Buffer broken")
|
||||
NV_STATUS_CODE(NV_ERR_BUFFER_TOO_SMALL, 0x00000002, "Buffer passed in is too small")
|
||||
NV_STATUS_CODE(NV_ERR_BUSY_RETRY, 0x00000003, "System is busy, retry later")
|
||||
NV_STATUS_CODE(NV_ERR_CALLBACK_NOT_SCHEDULED, 0x00000004, "The requested callback API not scheduled")
|
||||
NV_STATUS_CODE(NV_ERR_CARD_NOT_PRESENT, 0x00000005, "Card not detected")
|
||||
NV_STATUS_CODE(NV_ERR_CYCLE_DETECTED, 0x00000006, "Call cycle detected")
|
||||
NV_STATUS_CODE(NV_ERR_DMA_IN_USE, 0x00000007, "Requested DMA is in use")
|
||||
NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_LOCKED, 0x00000008, "Requested DMA memory is not locked")
|
||||
NV_STATUS_CODE(NV_ERR_DMA_MEM_NOT_UNLOCKED, 0x00000009, "Requested DMA memory is not unlocked")
|
||||
NV_STATUS_CODE(NV_ERR_DUAL_LINK_INUSE, 0x0000000A, "Dual-Link is in use")
|
||||
NV_STATUS_CODE(NV_ERR_ECC_ERROR, 0x0000000B, "Generic ECC error")
|
||||
NV_STATUS_CODE(NV_ERR_FIFO_BAD_ACCESS, 0x0000000C, "FIFO: Invalid access")
|
||||
NV_STATUS_CODE(NV_ERR_FREQ_NOT_SUPPORTED, 0x0000000D, "Requested frequency is not supported")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_DMA_NOT_INITIALIZED, 0x0000000E, "Requested DMA not initialized")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_IS_LOST, 0x0000000F, "GPU lost from the bus")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_IN_FULLCHIP_RESET, 0x00000010, "GPU currently in full-chip reset")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_NOT_FULL_POWER, 0x00000011, "GPU not in full power")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_UUID_NOT_FOUND, 0x00000012, "GPU UUID not found")
|
||||
NV_STATUS_CODE(NV_ERR_HOT_SWITCH, 0x00000013, "System in hot switch")
|
||||
NV_STATUS_CODE(NV_ERR_I2C_ERROR, 0x00000014, "I2C Error")
|
||||
NV_STATUS_CODE(NV_ERR_I2C_SPEED_TOO_HIGH, 0x00000015, "I2C Error: Speed too high")
|
||||
NV_STATUS_CODE(NV_ERR_ILLEGAL_ACTION, 0x00000016, "Current action is not allowed")
|
||||
NV_STATUS_CODE(NV_ERR_IN_USE, 0x00000017, "Generic busy error")
|
||||
NV_STATUS_CODE(NV_ERR_INFLATE_COMPRESSED_DATA_FAILED, 0x00000018, "Failed to inflate compressed data")
|
||||
NV_STATUS_CODE(NV_ERR_INSERT_DUPLICATE_NAME, 0x00000019, "Found a duplicate entry in the requested btree")
|
||||
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_RESOURCES, 0x0000001A, "Ran out of a critical resource, other than memory")
|
||||
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_PERMISSIONS, 0x0000001B, "The requester does not have sufficient permissions")
|
||||
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_POWER, 0x0000001C, "Generic Error: Low power")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_ACCESS_TYPE, 0x0000001D, "This type of access is not allowed")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_ADDRESS, 0x0000001E, "Address not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_ARGUMENT, 0x0000001F, "Invalid argument to call")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_BASE, 0x00000020, "Invalid base")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_CHANNEL, 0x00000021, "Given channel-id not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_CLASS, 0x00000022, "Given class-id not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_CLIENT, 0x00000023, "Given client not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_COMMAND, 0x00000024, "Command passed is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_DATA, 0x00000025, "Invalid data passed")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_DEVICE, 0x00000026, "Current device is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_DMA_SPECIFIER, 0x00000027, "The requested DMA specifier is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_EVENT, 0x00000028, "Invalid event occurred")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_FLAGS, 0x00000029, "Invalid flags passed")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_FUNCTION, 0x0000002A, "Called function is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_HEAP, 0x0000002B, "Heap corrupted")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_INDEX, 0x0000002C, "Index invalid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_IRQ_LEVEL, 0x0000002D, "Requested IRQ level is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_LIMIT, 0x0000002E, "Generic Error: Invalid limit")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_LOCK_STATE, 0x0000002F, "Requested lock state not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_METHOD, 0x00000030, "Requested method not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT, 0x00000031, "Object not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_BUFFER, 0x00000032, "Object buffer passed is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_HANDLE, 0x00000033, "Object handle is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_NEW, 0x00000034, "New object is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_OLD, 0x00000035, "Old object is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OBJECT_PARENT, 0x00000036, "Object parent is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OFFSET, 0x00000037, "The offset passed is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OPERATION, 0x00000038, "Requested operation is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_OWNER, 0x00000039, "Owner not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_PARAM_STRUCT, 0x0000003A, "Invalid structure parameter")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_PARAMETER, 0x0000003B, "At least one of the parameters passed is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_PATH, 0x0000003C, "The requested path is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_POINTER, 0x0000003D, "Pointer not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_REGISTRY_KEY, 0x0000003E, "Found an invalid registry key")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_REQUEST, 0x0000003F, "Generic Error: Invalid request")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_STATE, 0x00000040, "Generic Error: Invalid state")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_STRING_LENGTH, 0x00000041, "The string length is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_READ, 0x00000042, "The requested read operation is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_WRITE, 0x00000043, "The requested write operation is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_XLATE, 0x00000044, "The requested translate operation is not valid")
|
||||
NV_STATUS_CODE(NV_ERR_IRQ_NOT_FIRING, 0x00000045, "Requested IRQ is not firing")
|
||||
NV_STATUS_CODE(NV_ERR_IRQ_EDGE_TRIGGERED, 0x00000046, "IRQ is edge triggered")
|
||||
NV_STATUS_CODE(NV_ERR_MEMORY_TRAINING_FAILED, 0x00000047, "Failed memory training sequence")
|
||||
NV_STATUS_CODE(NV_ERR_MISMATCHED_SLAVE, 0x00000048, "Slave mismatch")
|
||||
NV_STATUS_CODE(NV_ERR_MISMATCHED_TARGET, 0x00000049, "Target mismatch")
|
||||
NV_STATUS_CODE(NV_ERR_MISSING_TABLE_ENTRY, 0x0000004A, "Requested entry missing not found in the table")
|
||||
NV_STATUS_CODE(NV_ERR_MODULE_LOAD_FAILED, 0x0000004B, "Failed to load the requested module")
|
||||
NV_STATUS_CODE(NV_ERR_MORE_DATA_AVAILABLE, 0x0000004C, "There is more data available")
|
||||
NV_STATUS_CODE(NV_ERR_MORE_PROCESSING_REQUIRED, 0x0000004D, "More processing required for the given call")
|
||||
NV_STATUS_CODE(NV_ERR_MULTIPLE_MEMORY_TYPES, 0x0000004E, "Multiple memory types found")
|
||||
NV_STATUS_CODE(NV_ERR_NO_FREE_FIFOS, 0x0000004F, "No more free FIFOs found")
|
||||
NV_STATUS_CODE(NV_ERR_NO_INTR_PENDING, 0x00000050, "No interrupt pending")
|
||||
NV_STATUS_CODE(NV_ERR_NO_MEMORY, 0x00000051, "Out of memory")
|
||||
NV_STATUS_CODE(NV_ERR_NO_SUCH_DOMAIN, 0x00000052, "Requested domain does not exist")
|
||||
NV_STATUS_CODE(NV_ERR_NO_VALID_PATH, 0x00000053, "Caller did not specify a valid path")
|
||||
NV_STATUS_CODE(NV_ERR_NOT_COMPATIBLE, 0x00000054, "Generic Error: Incompatible types")
|
||||
NV_STATUS_CODE(NV_ERR_NOT_READY, 0x00000055, "Generic Error: Not ready")
|
||||
NV_STATUS_CODE(NV_ERR_NOT_SUPPORTED, 0x00000056, "Call not supported")
|
||||
NV_STATUS_CODE(NV_ERR_OBJECT_NOT_FOUND, 0x00000057, "Requested object not found")
|
||||
NV_STATUS_CODE(NV_ERR_OBJECT_TYPE_MISMATCH, 0x00000058, "Specified objects do not match")
|
||||
NV_STATUS_CODE(NV_ERR_OPERATING_SYSTEM, 0x00000059, "Generic operating system error")
|
||||
NV_STATUS_CODE(NV_ERR_OTHER_DEVICE_FOUND, 0x0000005A, "Found other device instead of the requested one")
|
||||
NV_STATUS_CODE(NV_ERR_OUT_OF_RANGE, 0x0000005B, "The specified value is out of bounds")
|
||||
NV_STATUS_CODE(NV_ERR_OVERLAPPING_UVM_COMMIT, 0x0000005C, "Overlapping unified virtual memory commit")
|
||||
NV_STATUS_CODE(NV_ERR_PAGE_TABLE_NOT_AVAIL, 0x0000005D, "Requested page table not available")
|
||||
NV_STATUS_CODE(NV_ERR_PID_NOT_FOUND, 0x0000005E, "Process-Id not found")
|
||||
NV_STATUS_CODE(NV_ERR_PROTECTION_FAULT, 0x0000005F, "Protection fault")
|
||||
NV_STATUS_CODE(NV_ERR_RC_ERROR, 0x00000060, "Generic RC error")
|
||||
NV_STATUS_CODE(NV_ERR_REJECTED_VBIOS, 0x00000061, "Given Video BIOS rejected/invalid")
|
||||
NV_STATUS_CODE(NV_ERR_RESET_REQUIRED, 0x00000062, "Reset required")
|
||||
NV_STATUS_CODE(NV_ERR_STATE_IN_USE, 0x00000063, "State in use")
|
||||
NV_STATUS_CODE(NV_ERR_SIGNAL_PENDING, 0x00000064, "Signal pending")
|
||||
NV_STATUS_CODE(NV_ERR_TIMEOUT, 0x00000065, "Call timed out")
|
||||
NV_STATUS_CODE(NV_ERR_TIMEOUT_RETRY, 0x00000066, "Call timed out, please retry later")
|
||||
NV_STATUS_CODE(NV_ERR_TOO_MANY_PRIMARIES, 0x00000067, "Too many primaries")
|
||||
NV_STATUS_CODE(NV_ERR_UVM_ADDRESS_IN_USE, 0x00000068, "Unified virtual memory requested address already in use")
|
||||
NV_STATUS_CODE(NV_ERR_MAX_SESSION_LIMIT_REACHED, 0x00000069, "Maximum number of sessions reached")
|
||||
NV_STATUS_CODE(NV_ERR_LIB_RM_VERSION_MISMATCH, 0x0000006A, "Library version doesn't match driver version") //Contained within the RMAPI library
|
||||
NV_STATUS_CODE(NV_ERR_PRIV_SEC_VIOLATION, 0x0000006B, "Priv security violation")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_IN_DEBUG_MODE, 0x0000006C, "GPU currently in debug mode")
|
||||
NV_STATUS_CODE(NV_ERR_FEATURE_NOT_ENABLED, 0x0000006D, "Requested Feature functionality is not enabled")
|
||||
NV_STATUS_CODE(NV_ERR_RESOURCE_LOST, 0x0000006E, "Requested resource has been destroyed")
|
||||
NV_STATUS_CODE(NV_ERR_PMU_NOT_READY, 0x0000006F, "PMU is not ready or has not yet been initialized")
|
||||
NV_STATUS_CODE(NV_ERR_FLCN_ERROR, 0x00000070, "Generic falcon assert or halt")
|
||||
NV_STATUS_CODE(NV_ERR_FATAL_ERROR, 0x00000071, "Fatal/unrecoverable error")
|
||||
NV_STATUS_CODE(NV_ERR_MEMORY_ERROR, 0x00000072, "Generic memory error")
|
||||
NV_STATUS_CODE(NV_ERR_INVALID_LICENSE, 0x00000073, "License provided is rejected or invalid")
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_INIT_ERROR, 0x00000074, "Nvlink Init Error")
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_MINION_ERROR, 0x00000075, "Nvlink Minion Error")
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_CLOCK_ERROR, 0x00000076, "Nvlink Clock Error")
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_TRAINING_ERROR, 0x00000077, "Nvlink Training Error")
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Configuration Error")
|
||||
NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt")
|
||||
|
||||
// Warnings:
|
||||
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")
|
||||
NV_STATUS_CODE(NV_WARN_INCORRECT_PERFMON_DATA, 0x00010002, "WARNING Incorrect performance monitor data")
|
||||
NV_STATUS_CODE(NV_WARN_MISMATCHED_SLAVE, 0x00010003, "WARNING Slave mismatch")
|
||||
NV_STATUS_CODE(NV_WARN_MISMATCHED_TARGET, 0x00010004, "WARNING Target mismatch")
|
||||
NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More processing required for the call")
|
||||
NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do")
|
||||
NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found")
|
||||
NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range")
|
||||
|
||||
#endif /* SDK_NVSTATUSCODES_H */
|
||||
662
nvdisplay/kernel-open/common/inc/nvtypes.h
Normal file
662
nvdisplay/kernel-open/common/inc/nvtypes.h
Normal file
@@ -0,0 +1,662 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef NVTYPES_INCLUDED
|
||||
#define NVTYPES_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "cpuopsys.h"
|
||||
|
||||
#ifndef NVTYPES_USE_STDINT
|
||||
#define NVTYPES_USE_STDINT 0
|
||||
#endif
|
||||
|
||||
#if NVTYPES_USE_STDINT
|
||||
#ifdef __cplusplus
|
||||
#include <cstdint>
|
||||
#include <cinttypes>
|
||||
#else
|
||||
#include <stdint.h>
|
||||
#include <inttypes.h>
|
||||
#endif // __cplusplus
|
||||
#endif // NVTYPES_USE_STDINT
|
||||
|
||||
#ifndef __cplusplus
|
||||
// Header includes to make sure wchar_t is defined for C-file compilation
|
||||
// (C++ is not affected as it is a fundamental type there)
|
||||
// _MSC_VER is a hack to avoid failures for old setup of UEFI builds which are
|
||||
// currently set to msvc100 but do not properly set the include paths
|
||||
#if defined(NV_WINDOWS) && (!defined(_MSC_VER) || (_MSC_VER > 1600))
|
||||
#include <stddef.h>
|
||||
#define NV_HAS_WCHAR_T_TYPEDEF 1
|
||||
#endif
|
||||
#endif // __cplusplus
|
||||
|
||||
#if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__)
|
||||
// ensure or force 8-bytes alignment of NV 64-bit types
|
||||
#define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8)))
|
||||
#else
|
||||
// nothing needed
|
||||
#define OPTIONAL_ALIGN8_ATTR
|
||||
#endif // MAKE_NV64TYPES_8BYTES_ALIGNED && i386
|
||||
|
||||
/***************************************************************************\
|
||||
|* Typedefs *|
|
||||
\***************************************************************************/
|
||||
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
//Typedefs for MISRA COMPLIANCE
|
||||
typedef unsigned long long UInt64;
|
||||
typedef signed long long Int64;
|
||||
typedef unsigned int UInt32;
|
||||
typedef signed int Int32;
|
||||
typedef unsigned short UInt16;
|
||||
typedef signed short Int16;
|
||||
typedef unsigned char UInt8 ;
|
||||
typedef signed char Int8 ;
|
||||
|
||||
typedef void Void;
|
||||
typedef float float32_t;
|
||||
typedef double float64_t;
|
||||
#endif
|
||||
|
||||
|
||||
// Floating point types
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
typedef float32_t NvF32; /* IEEE Single Precision (S1E8M23) */
|
||||
typedef float64_t NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */
|
||||
#else
|
||||
typedef float NvF32; /* IEEE Single Precision (S1E8M23) */
|
||||
typedef double NvF64 OPTIONAL_ALIGN8_ATTR; /* IEEE Double Precision (S1E11M52) */
|
||||
#endif
|
||||
|
||||
|
||||
// 8-bit: 'char' is the only 8-bit in the C89 standard and after.
|
||||
#if NVTYPES_USE_STDINT
|
||||
typedef uint8_t NvV8; /* "void": enumerated or multiple fields */
|
||||
typedef uint8_t NvU8; /* 0 to 255 */
|
||||
typedef int8_t NvS8; /* -128 to 127 */
|
||||
#else
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
typedef UInt8 NvV8; /* "void": enumerated or multiple fields */
|
||||
typedef UInt8 NvU8; /* 0 to 255 */
|
||||
typedef Int8 NvS8; /* -128 to 127 */
|
||||
#else
|
||||
typedef unsigned char NvV8; /* "void": enumerated or multiple fields */
|
||||
typedef unsigned char NvU8; /* 0 to 255 */
|
||||
typedef signed char NvS8; /* -128 to 127 */
|
||||
#endif
|
||||
#endif // NVTYPES_USE_STDINT
|
||||
|
||||
|
||||
#if NVTYPES_USE_STDINT
|
||||
typedef uint16_t NvV16; /* "void": enumerated or multiple fields */
|
||||
typedef uint16_t NvU16; /* 0 to 65535 */
|
||||
typedef int16_t NvS16; /* -32768 to 32767 */
|
||||
#else
|
||||
// 16-bit: If the compiler tells us what we can use, then use it.
|
||||
#ifdef __INT16_TYPE__
|
||||
typedef unsigned __INT16_TYPE__ NvV16; /* "void": enumerated or multiple fields */
|
||||
typedef unsigned __INT16_TYPE__ NvU16; /* 0 to 65535 */
|
||||
typedef signed __INT16_TYPE__ NvS16; /* -32768 to 32767 */
|
||||
|
||||
// The minimal standard for C89 and after
|
||||
#else // __INT16_TYPE__
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
typedef UInt16 NvV16; /* "void": enumerated or multiple fields */
|
||||
typedef UInt16 NvU16; /* 0 to 65535 */
|
||||
typedef Int16 NvS16; /* -32768 to 32767 */
|
||||
#else
|
||||
typedef unsigned short NvV16; /* "void": enumerated or multiple fields */
|
||||
typedef unsigned short NvU16; /* 0 to 65535 */
|
||||
typedef signed short NvS16; /* -32768 to 32767 */
|
||||
#endif
|
||||
#endif // __INT16_TYPE__
|
||||
#endif // NVTYPES_USE_STDINT
|
||||
|
||||
// wchar type (fixed size types consistent across Linux/Windows boundaries)
|
||||
#if defined(NV_HAS_WCHAR_T_TYPEDEF)
|
||||
typedef wchar_t NvWchar;
|
||||
#else
|
||||
typedef NvV16 NvWchar;
|
||||
#endif
|
||||
|
||||
// Macro to build an NvU32 from four bytes, listed from msb to lsb
|
||||
#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
|
||||
|
||||
#if NVTYPES_USE_STDINT
|
||||
typedef uint32_t NvV32; /* "void": enumerated or multiple fields */
|
||||
typedef uint32_t NvU32; /* 0 to 4294967295 */
|
||||
typedef int32_t NvS32; /* -2147483648 to 2147483647 */
|
||||
#else
|
||||
// 32-bit: If the compiler tells us what we can use, then use it.
|
||||
#ifdef __INT32_TYPE__
|
||||
typedef unsigned __INT32_TYPE__ NvV32; /* "void": enumerated or multiple fields */
|
||||
typedef unsigned __INT32_TYPE__ NvU32; /* 0 to 4294967295 */
|
||||
typedef signed __INT32_TYPE__ NvS32; /* -2147483648 to 2147483647 */
|
||||
|
||||
// Older compilers
|
||||
#else // __INT32_TYPE__
|
||||
|
||||
// For historical reasons, NvU32/NvV32 are defined to different base intrinsic
|
||||
// types than NvS32 on some platforms.
|
||||
// Mainly for 64-bit linux, where long is 64 bits and win9x, where int is 16 bit.
|
||||
#if (defined(NV_UNIX) || defined(vxworks) || defined(NV_WINDOWS_CE) || \
|
||||
defined(__arm) || defined(__IAR_SYSTEMS_ICC__) || defined(NV_QNX) || \
|
||||
defined(NV_INTEGRITY) || defined(NV_MODS) || \
|
||||
defined(__GNUC__) || defined(__clang__) || defined(NV_MACINTOSH_64)) && \
|
||||
(!defined(NV_MACINTOSH) || defined(NV_MACINTOSH_64))
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
typedef UInt32 NvV32; /* "void": enumerated or multiple fields */
|
||||
typedef UInt32 NvU32; /* 0 to 4294967295 */
|
||||
#else
|
||||
typedef unsigned int NvV32; /* "void": enumerated or multiple fields */
|
||||
typedef unsigned int NvU32; /* 0 to 4294967295 */
|
||||
#endif
|
||||
|
||||
// The minimal standard for C89 and after
|
||||
#else // (defined(NV_UNIX) || defined(vxworks) || ...
|
||||
typedef unsigned long NvV32; /* "void": enumerated or multiple fields */
|
||||
typedef unsigned long NvU32; /* 0 to 4294967295 */
|
||||
#endif // (defined(NV_UNIX) || defined(vxworks) || ...
|
||||
|
||||
// Mac OS 32-bit still needs this
|
||||
#if defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64)
|
||||
typedef signed long NvS32; /* -2147483648 to 2147483647 */
|
||||
#else
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
typedef Int32 NvS32; /* -2147483648 to 2147483647 */
|
||||
#else
|
||||
typedef signed int NvS32; /* -2147483648 to 2147483647 */
|
||||
#endif
|
||||
#endif // defined(NV_MACINTOSH) && !defined(NV_MACINTOSH_64)
|
||||
#endif // __INT32_TYPE__
|
||||
#endif // NVTYPES_USE_STDINT
|
||||
|
||||
|
||||
|
||||
#if NVTYPES_USE_STDINT
|
||||
typedef uint64_t NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
|
||||
typedef int64_t NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
|
||||
|
||||
#define NvU64_fmtX PRIX64
|
||||
#define NvU64_fmtx PRIx64
|
||||
#define NvU64_fmtu PRIu64
|
||||
#define NvU64_fmto PRIo64
|
||||
#define NvS64_fmtd PRId64
|
||||
#define NvS64_fmti PRIi64
|
||||
#else
|
||||
// 64-bit types for compilers that support them, plus some obsolete variants
|
||||
#if defined(__GNUC__) || defined(__clang__) || defined(__arm) || \
|
||||
defined(__IAR_SYSTEMS_ICC__) || defined(__ghs__) || defined(_WIN64) || \
|
||||
defined(__SUNPRO_C) || defined(__SUNPRO_CC) || defined (__xlC__)
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
typedef UInt64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
|
||||
typedef Int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
|
||||
#else
|
||||
typedef unsigned long long NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
|
||||
typedef long long NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
|
||||
#endif
|
||||
|
||||
#define NvU64_fmtX "llX"
|
||||
#define NvU64_fmtx "llx"
|
||||
#define NvU64_fmtu "llu"
|
||||
#define NvU64_fmto "llo"
|
||||
#define NvS64_fmtd "lld"
|
||||
#define NvS64_fmti "lli"
|
||||
|
||||
// Microsoft since 2003 -- https://msdn.microsoft.com/en-us/library/29dh1w7z.aspx
|
||||
#else
|
||||
typedef unsigned __int64 NvU64 OPTIONAL_ALIGN8_ATTR; /* 0 to 18446744073709551615 */
|
||||
typedef __int64 NvS64 OPTIONAL_ALIGN8_ATTR; /* -9223372036854775808 to 9223372036854775807 */
|
||||
|
||||
#define NvU64_fmtX "I64X"
|
||||
#define NvU64_fmtx "I64x"
|
||||
#define NvU64_fmtu "I64u"
|
||||
#define NvU64_fmto "I64o"
|
||||
#define NvS64_fmtd "I64d"
|
||||
#define NvS64_fmti "I64i"
|
||||
|
||||
#endif
|
||||
#endif // NVTYPES_USE_STDINT
|
||||
|
||||
#ifdef NV_TYPESAFE_HANDLES
|
||||
/*
|
||||
* Can't use opaque pointer as clients might be compiled with mismatched
|
||||
* pointer sizes. TYPESAFE check will eventually be removed once all clients
|
||||
* have transistioned safely to NvHandle.
|
||||
* The plan is to then eventually scale up the handle to be 64-bits.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
NvU32 val;
|
||||
} NvHandle;
|
||||
#else
|
||||
/*
|
||||
* For compatibility with modules that haven't moved typesafe handles.
|
||||
*/
|
||||
typedef NvU32 NvHandle;
|
||||
#endif // NV_TYPESAFE_HANDLES
|
||||
|
||||
/* Boolean type */
|
||||
typedef NvU8 NvBool;
|
||||
#define NV_TRUE ((NvBool)(0 == 0))
|
||||
#define NV_FALSE ((NvBool)(0 != 0))
|
||||
|
||||
/* Tristate type: NV_TRISTATE_FALSE, NV_TRISTATE_TRUE, NV_TRISTATE_INDETERMINATE */
|
||||
typedef NvU8 NvTristate;
|
||||
#define NV_TRISTATE_FALSE ((NvTristate) 0)
|
||||
#define NV_TRISTATE_TRUE ((NvTristate) 1)
|
||||
#define NV_TRISTATE_INDETERMINATE ((NvTristate) 2)
|
||||
|
||||
/* Macros to extract the low and high parts of a 64-bit unsigned integer */
|
||||
/* Also designed to work if someone happens to pass in a 32-bit integer */
|
||||
#ifdef NV_MISRA_COMPLIANCE_REQUIRED
|
||||
#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffffU))
|
||||
#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffffU))
|
||||
#else
|
||||
#define NvU64_HI32(n) ((NvU32)((((NvU64)(n)) >> 32) & 0xffffffff))
|
||||
#define NvU64_LO32(n) ((NvU32)(( (NvU64)(n)) & 0xffffffff))
|
||||
#endif
|
||||
#define NvU40_HI32(n) ((NvU32)((((NvU64)(n)) >> 8) & 0xffffffffU))
|
||||
#define NvU40_HI24of32(n) ((NvU32)( (NvU64)(n) & 0xffffff00U))
|
||||
|
||||
/* Macros to get the MSB and LSB of a 32 bit unsigned number */
|
||||
#define NvU32_HI16(n) ((NvU16)((((NvU32)(n)) >> 16) & 0xffffU))
|
||||
#define NvU32_LO16(n) ((NvU16)(( (NvU32)(n)) & 0xffffU))
|
||||
|
||||
/***************************************************************************\
|
||||
|* *|
|
||||
|* 64 bit type definitions for use in interface structures. *|
|
||||
|* *|
|
||||
\***************************************************************************/
|
||||
|
||||
#if defined(NV_64_BITS)
|
||||
|
||||
typedef void* NvP64; /* 64 bit void pointer */
|
||||
typedef NvU64 NvUPtr; /* pointer sized unsigned int */
|
||||
typedef NvS64 NvSPtr; /* pointer sized signed int */
|
||||
typedef NvU64 NvLength; /* length to agree with sizeof */
|
||||
|
||||
#define NvP64_VALUE(n) (n)
|
||||
#define NvP64_fmt "%p"
|
||||
|
||||
#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(v))
|
||||
#define NvP64_PLUS_OFFSET(p,o) (NvP64)((NvU64)(p) + (NvU64)(o))
|
||||
|
||||
#define NvUPtr_fmtX NvU64_fmtX
|
||||
#define NvUPtr_fmtx NvU64_fmtx
|
||||
#define NvUPtr_fmtu NvU64_fmtu
|
||||
#define NvUPtr_fmto NvU64_fmto
|
||||
#define NvSPtr_fmtd NvS64_fmtd
|
||||
#define NvSPtr_fmti NvS64_fmti
|
||||
|
||||
#else
|
||||
|
||||
typedef NvU64 NvP64; /* 64 bit void pointer */
|
||||
typedef NvU32 NvUPtr; /* pointer sized unsigned int */
|
||||
typedef NvS32 NvSPtr; /* pointer sized signed int */
|
||||
typedef NvU32 NvLength; /* length to agree with sizeof */
|
||||
|
||||
#define NvP64_VALUE(n) ((void *)(NvUPtr)(n))
|
||||
#define NvP64_fmt "0x%llx"
|
||||
|
||||
#define KERNEL_POINTER_FROM_NvP64(p,v) ((p)(NvUPtr)(v))
|
||||
#define NvP64_PLUS_OFFSET(p,o) ((p) + (NvU64)(o))
|
||||
|
||||
#define NvUPtr_fmtX "X"
|
||||
#define NvUPtr_fmtx "x"
|
||||
#define NvUPtr_fmtu "u"
|
||||
#define NvUPtr_fmto "o"
|
||||
#define NvSPtr_fmtd "d"
|
||||
#define NvSPtr_fmti "i"
|
||||
|
||||
#endif
|
||||
|
||||
#define NvP64_NULL (NvP64)0
|
||||
|
||||
/*!
|
||||
* Helper macro to pack an @ref NvU64_ALIGN32 structure from a @ref NvU64.
|
||||
*
|
||||
* @param[out] pDst Pointer to NvU64_ALIGN32 structure to pack
|
||||
* @param[in] pSrc Pointer to NvU64 with which to pack
|
||||
*/
|
||||
#define NvU64_ALIGN32_PACK(pDst, pSrc) \
|
||||
do { \
|
||||
(pDst)->lo = NvU64_LO32(*(pSrc)); \
|
||||
(pDst)->hi = NvU64_HI32(*(pSrc)); \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* Helper macro to unpack a @ref NvU64_ALIGN32 structure into a @ref NvU64.
|
||||
*
|
||||
* @param[out] pDst Pointer to NvU64 in which to unpack
|
||||
* @param[in] pSrc Pointer to NvU64_ALIGN32 structure from which to unpack
|
||||
*/
|
||||
#define NvU64_ALIGN32_UNPACK(pDst, pSrc) \
|
||||
do { \
|
||||
(*(pDst)) = NvU64_ALIGN32_VAL(pSrc); \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* Helper macro to unpack a @ref NvU64_ALIGN32 structure as a @ref NvU64.
|
||||
*
|
||||
* @param[in] pSrc Pointer to NvU64_ALIGN32 structure to unpack
|
||||
*/
|
||||
#define NvU64_ALIGN32_VAL(pSrc) \
|
||||
((NvU64) ((NvU64)((pSrc)->lo) | (((NvU64)(pSrc)->hi) << 32U)))
|
||||
|
||||
/*!
|
||||
* Helper macro to check whether the 32 bit aligned 64 bit number is zero.
|
||||
*
|
||||
* @param[in] _pU64 Pointer to NvU64_ALIGN32 structure.
|
||||
*
|
||||
* @return
|
||||
* NV_TRUE _pU64 is zero.
|
||||
* NV_FALSE otherwise.
|
||||
*/
|
||||
#define NvU64_ALIGN32_IS_ZERO(_pU64) \
|
||||
(((_pU64)->lo == 0U) && ((_pU64)->hi == 0U))
|
||||
|
||||
/*!
|
||||
* Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor.
|
||||
*
|
||||
* @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure.
|
||||
* @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure.
|
||||
* @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure.
|
||||
*/
|
||||
#define NvU64_ALIGN32_ADD(pDst, pSrc1, pSrc2) \
|
||||
do { \
|
||||
NvU64 __dst, __src1, __scr2; \
|
||||
\
|
||||
NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \
|
||||
NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \
|
||||
__dst = __src1 + __scr2; \
|
||||
NvU64_ALIGN32_PACK((pDst), &__dst); \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* Helper macro to sub two 32 aligned 64 bit numbers on 64 bit processor.
|
||||
*
|
||||
* @param[in] pSrc1 Pointer to NvU64_ALIGN32 source 1 structure.
|
||||
* @param[in] pSrc2 Pointer to NvU64_ALIGN32 source 2 structure.
|
||||
* @param[in/out] pDst Pointer to NvU64_ALIGN32 dest. structure.
|
||||
*/
|
||||
#define NvU64_ALIGN32_SUB(pDst, pSrc1, pSrc2) \
|
||||
do { \
|
||||
NvU64 __dst, __src1, __scr2; \
|
||||
\
|
||||
NvU64_ALIGN32_UNPACK(&__src1, (pSrc1)); \
|
||||
NvU64_ALIGN32_UNPACK(&__scr2, (pSrc2)); \
|
||||
__dst = __src1 - __scr2; \
|
||||
NvU64_ALIGN32_PACK((pDst), &__dst); \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* Structure for representing 32 bit aligned NvU64 (64-bit unsigned integer)
|
||||
* structures. This structure must be used because the 32 bit processor and
|
||||
* 64 bit processor compilers will pack/align NvU64 differently.
|
||||
*
|
||||
* One use case is RM being 64 bit proc whereas PMU being 32 bit proc, this
|
||||
* alignment difference will result in corrupted transactions between the RM
|
||||
* and PMU.
|
||||
*
|
||||
* See the @ref NvU64_ALIGN32_PACK and @ref NvU64_ALIGN32_UNPACK macros for
|
||||
* packing and unpacking these structures.
|
||||
*
|
||||
* @note The intention of this structure is to provide a datatype which will
|
||||
* packed/aligned consistently and efficiently across all platforms.
|
||||
* We don't want to use "NV_DECLARE_ALIGNED(NvU64, 8)" because that
|
||||
* leads to memory waste on our 32-bit uprocessors (e.g. FALCONs) where
|
||||
* DMEM efficiency is vital.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/*!
|
||||
* Low 32 bits.
|
||||
*/
|
||||
NvU32 lo;
|
||||
/*!
|
||||
* High 32 bits.
|
||||
*/
|
||||
NvU32 hi;
|
||||
} NvU64_ALIGN32;
|
||||
|
||||
/* Useful macro to hide required double cast */
|
||||
#define NV_PTR_TO_NvP64(n) (NvP64)(NvUPtr)(n)
|
||||
#define NV_SIGN_EXT_PTR_TO_NvP64(p) ((NvP64)(NvS64)(NvSPtr)(p))
|
||||
#define KERNEL_POINTER_TO_NvP64(p) ((NvP64)(uintptr_t)(p))
|
||||
|
||||
/***************************************************************************\
|
||||
|* *|
|
||||
|* Limits for common types. *|
|
||||
|* *|
|
||||
\***************************************************************************/
|
||||
|
||||
/* Explanation of the current form of these limits:
|
||||
*
|
||||
* - Decimal is used, as hex values are by default positive.
|
||||
* - Casts are not used, as usage in the preprocessor itself (#if) ends poorly.
|
||||
* - The subtraction of 1 for some MIN values is used to get around the fact
|
||||
* that the C syntax actually treats -x as NEGATE(x) instead of a distinct
|
||||
* number. Since 214748648 isn't a valid positive 32-bit signed value, we
|
||||
* take the largest valid positive signed number, negate it, and subtract 1.
|
||||
*/
|
||||
#define NV_S8_MIN (-128)
|
||||
#define NV_S8_MAX (+127)
|
||||
#define NV_U8_MIN (0U)
|
||||
#define NV_U8_MAX (+255U)
|
||||
#define NV_S16_MIN (-32768)
|
||||
#define NV_S16_MAX (+32767)
|
||||
#define NV_U16_MIN (0U)
|
||||
#define NV_U16_MAX (+65535U)
|
||||
#define NV_S32_MIN (-2147483647 - 1)
|
||||
#define NV_S32_MAX (+2147483647)
|
||||
#define NV_U32_MIN (0U)
|
||||
#define NV_U32_MAX (+4294967295U)
|
||||
#define NV_S64_MIN (-9223372036854775807LL - 1LL)
|
||||
#define NV_S64_MAX (+9223372036854775807LL)
|
||||
#define NV_U64_MIN (0ULL)
|
||||
#define NV_U64_MAX (+18446744073709551615ULL)
|
||||
|
||||
/* Aligns fields in structs so they match up between 32 and 64 bit builds */
|
||||
#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX)
|
||||
#define NV_ALIGN_BYTES(size) __attribute__ ((aligned (size)))
|
||||
#elif defined(__arm)
|
||||
#define NV_ALIGN_BYTES(size) __align(ALIGN)
|
||||
#else
|
||||
// XXX This is dangerously nonportable! We really shouldn't provide a default
|
||||
// version of this that doesn't do anything.
|
||||
#define NV_ALIGN_BYTES(size)
|
||||
#endif
|
||||
|
||||
// NV_DECLARE_ALIGNED() can be used on all platforms.
|
||||
// This macro form accounts for the fact that __declspec on Windows is required
|
||||
// before the variable type,
|
||||
// and NV_ALIGN_BYTES is required after the variable name.
|
||||
#if defined(__GNUC__) || defined(__clang__) || defined(NV_QNX)
|
||||
#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) TYPE_VAR __attribute__ ((aligned (ALIGN)))
|
||||
#elif defined(_MSC_VER)
|
||||
#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __declspec(align(ALIGN)) TYPE_VAR
|
||||
#elif defined(__arm)
|
||||
#define NV_DECLARE_ALIGNED(TYPE_VAR, ALIGN) __align(ALIGN) TYPE_VAR
|
||||
#endif
|
||||
|
||||
/***************************************************************************\
|
||||
|* Function Declaration Types *|
|
||||
\***************************************************************************/
|
||||
|
||||
// stretching the meaning of "nvtypes", but this seems to least offensive
|
||||
// place to re-locate these from nvos.h which cannot be included by a number
|
||||
// of builds that need them
|
||||
|
||||
#if defined(_MSC_VER)
|
||||
|
||||
#if _MSC_VER >= 1310
|
||||
#define NV_NOINLINE __declspec(noinline)
|
||||
#else
|
||||
#define NV_NOINLINE
|
||||
#endif
|
||||
|
||||
#define NV_INLINE __inline
|
||||
|
||||
#if _MSC_VER >= 1200
|
||||
#define NV_FORCEINLINE __forceinline
|
||||
#else
|
||||
#define NV_FORCEINLINE __inline
|
||||
#endif
|
||||
|
||||
#define NV_APIENTRY __stdcall
|
||||
#define NV_FASTCALL __fastcall
|
||||
#define NV_CDECLCALL __cdecl
|
||||
#define NV_STDCALL __stdcall
|
||||
|
||||
#define NV_FORCERESULTCHECK
|
||||
|
||||
#define NV_ATTRIBUTE_UNUSED
|
||||
|
||||
#define NV_FORMAT_PRINTF(_f, _a)
|
||||
|
||||
#else // ! defined(_MSC_VER)
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#if (__GNUC__ > 3) || \
|
||||
((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1) && (__GNUC_PATCHLEVEL__ >= 1))
|
||||
#define NV_NOINLINE __attribute__((__noinline__))
|
||||
#endif
|
||||
#elif defined(__clang__)
|
||||
#if __has_attribute(noinline)
|
||||
#define NV_NOINLINE __attribute__((__noinline__))
|
||||
#endif
|
||||
#elif defined(__arm) && (__ARMCC_VERSION >= 300000)
|
||||
#define NV_NOINLINE __attribute__((__noinline__))
|
||||
#elif (defined(__SUNPRO_C) && (__SUNPRO_C >= 0x590)) ||\
|
||||
(defined(__SUNPRO_CC) && (__SUNPRO_CC >= 0x590))
|
||||
#define NV_NOINLINE __attribute__((__noinline__))
|
||||
#elif defined (__INTEL_COMPILER)
|
||||
#define NV_NOINLINE __attribute__((__noinline__))
|
||||
#endif
|
||||
|
||||
#if !defined(NV_NOINLINE)
|
||||
#define NV_NOINLINE
|
||||
#endif
|
||||
|
||||
/* GreenHills compiler defines __GNUC__, but doesn't support
|
||||
* __inline__ keyword. */
|
||||
#if defined(__ghs__)
|
||||
#define NV_INLINE inline
|
||||
#elif defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
|
||||
#define NV_INLINE __inline__
|
||||
#elif defined (macintosh) || defined(__SUNPRO_C) || defined(__SUNPRO_CC)
|
||||
#define NV_INLINE inline
|
||||
#elif defined(__arm)
|
||||
#define NV_INLINE __inline
|
||||
#else
|
||||
#define NV_INLINE
|
||||
#endif
|
||||
|
||||
/* Don't force inline on DEBUG builds -- it's annoying for debuggers. */
|
||||
#if !defined(DEBUG)
|
||||
/* GreenHills compiler defines __GNUC__, but doesn't support
|
||||
* __attribute__ or __inline__ keyword. */
|
||||
#if defined(__ghs__)
|
||||
#define NV_FORCEINLINE inline
|
||||
#elif defined(__GNUC__)
|
||||
// GCC 3.1 and beyond support the always_inline function attribute.
|
||||
#if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 1))
|
||||
#define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__
|
||||
#else
|
||||
#define NV_FORCEINLINE __inline__
|
||||
#endif
|
||||
#elif defined(__clang__)
|
||||
#if __has_attribute(always_inline)
|
||||
#define NV_FORCEINLINE __attribute__((__always_inline__)) __inline__
|
||||
#else
|
||||
#define NV_FORCEINLINE __inline__
|
||||
#endif
|
||||
#elif defined(__arm) && (__ARMCC_VERSION >= 220000)
|
||||
// RVDS 2.2 also supports forceinline, but ADS 1.2 does not
|
||||
#define NV_FORCEINLINE __forceinline
|
||||
#else /* defined(__GNUC__) */
|
||||
#define NV_FORCEINLINE NV_INLINE
|
||||
#endif
|
||||
#else
|
||||
#define NV_FORCEINLINE NV_INLINE
|
||||
#endif
|
||||
|
||||
#define NV_APIENTRY
|
||||
#define NV_FASTCALL
|
||||
#define NV_CDECLCALL
|
||||
#define NV_STDCALL
|
||||
|
||||
/*
|
||||
* The 'warn_unused_result' function attribute prompts GCC to issue a
|
||||
* warning if the result of a function tagged with this attribute
|
||||
* is ignored by a caller. In combination with '-Werror', it can be
|
||||
* used to enforce result checking in RM code; at this point, this
|
||||
* is only done on UNIX.
|
||||
*/
|
||||
#if defined(__GNUC__) && defined(NV_UNIX)
|
||||
#if (__GNUC__ > 3) || ((__GNUC__ == 3) && (__GNUC_MINOR__ >= 4))
|
||||
#define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__))
|
||||
#else
|
||||
#define NV_FORCERESULTCHECK
|
||||
#endif
|
||||
#elif defined(__clang__)
|
||||
#if __has_attribute(warn_unused_result)
|
||||
#define NV_FORCERESULTCHECK __attribute__((__warn_unused_result__))
|
||||
#else
|
||||
#define NV_FORCERESULTCHECK
|
||||
#endif
|
||||
#else /* defined(__GNUC__) */
|
||||
#define NV_FORCERESULTCHECK
|
||||
#endif
|
||||
|
||||
#if defined(__GNUC__) || defined(__clang__) || defined(__INTEL_COMPILER)
|
||||
#define NV_ATTRIBUTE_UNUSED __attribute__((__unused__))
|
||||
#else
|
||||
#define NV_ATTRIBUTE_UNUSED
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Functions decorated with NV_FORMAT_PRINTF(f, a) have a format string at
|
||||
* parameter number 'f' and variadic arguments start at parameter number 'a'.
|
||||
* (Note that for C++ methods, there is an implicit 'this' parameter so
|
||||
* explicit parameters are numbered from 2.)
|
||||
*/
|
||||
#if defined(__GNUC__)
|
||||
#define NV_FORMAT_PRINTF(_f, _a) __attribute__((format(printf, _f, _a)))
|
||||
#else
|
||||
#define NV_FORMAT_PRINTF(_f, _a)
|
||||
#endif
|
||||
|
||||
#endif // defined(_MSC_VER)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* NVTYPES_INCLUDED */
|
||||
257
nvdisplay/kernel-open/common/inc/os-interface.h
Normal file
257
nvdisplay/kernel-open/common/inc/os-interface.h
Normal file
@@ -0,0 +1,257 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Os interface definitions needed by os-interface.c
|
||||
*/
|
||||
|
||||
#ifndef OS_INTERFACE_H
|
||||
#define OS_INTERFACE_H
|
||||
|
||||
/******************* Operating System Interface Routines *******************\
|
||||
* *
|
||||
* Operating system wrapper functions used to abstract the OS. *
|
||||
* *
|
||||
\***************************************************************************/
|
||||
|
||||
#include <nvtypes.h>
|
||||
#include <nvstatus.h>
|
||||
#include "nv_stdarg.h"
|
||||
#include <nv-kernel-interface-api.h>
|
||||
#include <os/nv_memory_type.h>
|
||||
#include <nv-caps.h>
|
||||
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 os_major_version;
|
||||
NvU32 os_minor_version;
|
||||
NvU32 os_build_number;
|
||||
const char * os_build_version_str;
|
||||
const char * os_build_date_plus_str;
|
||||
}os_version_info;
|
||||
|
||||
/* Each OS defines its own version of this opaque type */
|
||||
struct os_work_queue;
|
||||
|
||||
/* Each OS defines its own version of this opaque type */
|
||||
typedef struct os_wait_queue os_wait_queue;
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
*
|
||||
* Function prototypes for OS interface.
|
||||
*
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
NvU64 NV_API_CALL os_get_num_phys_pages (void);
|
||||
NV_STATUS NV_API_CALL os_alloc_mem (void **, NvU64);
|
||||
void NV_API_CALL os_free_mem (void *);
|
||||
NV_STATUS NV_API_CALL os_get_current_time (NvU32 *, NvU32 *);
|
||||
NvU64 NV_API_CALL os_get_current_tick (void);
|
||||
NvU64 NV_API_CALL os_get_current_tick_hr (void);
|
||||
NvU64 NV_API_CALL os_get_tick_resolution (void);
|
||||
NV_STATUS NV_API_CALL os_delay (NvU32);
|
||||
NV_STATUS NV_API_CALL os_delay_us (NvU32);
|
||||
NvU64 NV_API_CALL os_get_cpu_frequency (void);
|
||||
NvU32 NV_API_CALL os_get_current_process (void);
|
||||
void NV_API_CALL os_get_current_process_name (char *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_get_current_thread (NvU64 *);
|
||||
char* NV_API_CALL os_string_copy (char *, const char *);
|
||||
NvU32 NV_API_CALL os_string_length (const char *);
|
||||
NvU32 NV_API_CALL os_strtoul (const char *, char **, NvU32);
|
||||
NvS32 NV_API_CALL os_string_compare (const char *, const char *);
|
||||
NvS32 NV_API_CALL os_snprintf (char *, NvU32, const char *, ...);
|
||||
NvS32 NV_API_CALL os_vsnprintf (char *, NvU32, const char *, va_list);
|
||||
void NV_API_CALL os_log_error (const char *, va_list);
|
||||
void* NV_API_CALL os_mem_copy (void *, const void *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_memcpy_from_user (void *, const void *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_memcpy_to_user (void *, const void *, NvU32);
|
||||
void* NV_API_CALL os_mem_set (void *, NvU8, NvU32);
|
||||
NvS32 NV_API_CALL os_mem_cmp (const NvU8 *, const NvU8 *, NvU32);
|
||||
void* NV_API_CALL os_pci_init_handle (NvU32, NvU8, NvU8, NvU8, NvU16 *, NvU16 *);
|
||||
NV_STATUS NV_API_CALL os_pci_read_byte (void *, NvU32, NvU8 *);
|
||||
NV_STATUS NV_API_CALL os_pci_read_word (void *, NvU32, NvU16 *);
|
||||
NV_STATUS NV_API_CALL os_pci_read_dword (void *, NvU32, NvU32 *);
|
||||
NV_STATUS NV_API_CALL os_pci_write_byte (void *, NvU32, NvU8);
|
||||
NV_STATUS NV_API_CALL os_pci_write_word (void *, NvU32, NvU16);
|
||||
NV_STATUS NV_API_CALL os_pci_write_dword (void *, NvU32, NvU32);
|
||||
NvBool NV_API_CALL os_pci_remove_supported (void);
|
||||
void NV_API_CALL os_pci_remove (void *);
|
||||
void* NV_API_CALL os_map_kernel_space (NvU64, NvU64, NvU32);
|
||||
void NV_API_CALL os_unmap_kernel_space (void *, NvU64);
|
||||
void* NV_API_CALL os_map_user_space (NvU64, NvU64, NvU32, NvU32, void **);
|
||||
void NV_API_CALL os_unmap_user_space (void *, NvU64, void *);
|
||||
NV_STATUS NV_API_CALL os_flush_cpu_cache (void);
|
||||
NV_STATUS NV_API_CALL os_flush_cpu_cache_all (void);
|
||||
NV_STATUS NV_API_CALL os_flush_user_cache (void);
|
||||
void NV_API_CALL os_flush_cpu_write_combine_buffer(void);
|
||||
NvU8 NV_API_CALL os_io_read_byte (NvU32);
|
||||
NvU16 NV_API_CALL os_io_read_word (NvU32);
|
||||
NvU32 NV_API_CALL os_io_read_dword (NvU32);
|
||||
void NV_API_CALL os_io_write_byte (NvU32, NvU8);
|
||||
void NV_API_CALL os_io_write_word (NvU32, NvU16);
|
||||
void NV_API_CALL os_io_write_dword (NvU32, NvU32);
|
||||
NvBool NV_API_CALL os_is_administrator (void);
|
||||
NvBool NV_API_CALL os_allow_priority_override (void);
|
||||
void NV_API_CALL os_dbg_init (void);
|
||||
void NV_API_CALL os_dbg_breakpoint (void);
|
||||
void NV_API_CALL os_dbg_set_level (NvU32);
|
||||
NvU32 NV_API_CALL os_get_cpu_count (void);
|
||||
NvU32 NV_API_CALL os_get_cpu_number (void);
|
||||
void NV_API_CALL os_disable_console_access (void);
|
||||
void NV_API_CALL os_enable_console_access (void);
|
||||
NV_STATUS NV_API_CALL os_registry_init (void);
|
||||
NV_STATUS NV_API_CALL os_schedule (void);
|
||||
NV_STATUS NV_API_CALL os_alloc_spinlock (void **);
|
||||
void NV_API_CALL os_free_spinlock (void *);
|
||||
NvU64 NV_API_CALL os_acquire_spinlock (void *);
|
||||
void NV_API_CALL os_release_spinlock (void *, NvU64);
|
||||
NV_STATUS NV_API_CALL os_queue_work_item (struct os_work_queue *, void *);
|
||||
NV_STATUS NV_API_CALL os_flush_work_queue (struct os_work_queue *);
|
||||
NV_STATUS NV_API_CALL os_alloc_mutex (void **);
|
||||
void NV_API_CALL os_free_mutex (void *);
|
||||
NV_STATUS NV_API_CALL os_acquire_mutex (void *);
|
||||
NV_STATUS NV_API_CALL os_cond_acquire_mutex (void *);
|
||||
void NV_API_CALL os_release_mutex (void *);
|
||||
void* NV_API_CALL os_alloc_semaphore (NvU32);
|
||||
void NV_API_CALL os_free_semaphore (void *);
|
||||
NV_STATUS NV_API_CALL os_acquire_semaphore (void *);
|
||||
NV_STATUS NV_API_CALL os_cond_acquire_semaphore (void *);
|
||||
NV_STATUS NV_API_CALL os_release_semaphore (void *);
|
||||
NvBool NV_API_CALL os_semaphore_may_sleep (void);
|
||||
NV_STATUS NV_API_CALL os_get_version_info (os_version_info*);
|
||||
NvBool NV_API_CALL os_is_isr (void);
|
||||
NvBool NV_API_CALL os_pat_supported (void);
|
||||
void NV_API_CALL os_dump_stack (void);
|
||||
NvBool NV_API_CALL os_is_efi_enabled (void);
|
||||
NvBool NV_API_CALL os_is_xen_dom0 (void);
|
||||
NvBool NV_API_CALL os_is_vgx_hyper (void);
|
||||
NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32);
|
||||
NvBool NV_API_CALL os_is_grid_supported (void);
|
||||
NvU32 NV_API_CALL os_get_grid_csp_support (void);
|
||||
void NV_API_CALL os_get_screen_info (NvU64 *, NvU16 *, NvU16 *, NvU16 *, NvU16 *, NvU64, NvU64);
|
||||
void NV_API_CALL os_bug_check (NvU32, const char *);
|
||||
NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32);
|
||||
NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**);
|
||||
NV_STATUS NV_API_CALL os_unlock_user_pages (NvU64, void *);
|
||||
NV_STATUS NV_API_CALL os_match_mmap_offset (void *, NvU64, NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_get_euid (NvU32 *);
|
||||
NV_STATUS NV_API_CALL os_get_smbios_header (NvU64 *pSmbsAddr);
|
||||
NV_STATUS NV_API_CALL os_get_acpi_rsdp_from_uefi (NvU32 *);
|
||||
void NV_API_CALL os_add_record_for_crashLog (void *, NvU32);
|
||||
void NV_API_CALL os_delete_record_for_crashLog (void *);
|
||||
NV_STATUS NV_API_CALL os_call_vgpu_vfio (void *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_numa_memblock_size (NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_alloc_pages_node (NvS32, NvU32, NvU32, NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_get_page (NvU64 address);
|
||||
NV_STATUS NV_API_CALL os_put_page (NvU64 address);
|
||||
NvU32 NV_API_CALL os_get_page_refcount (NvU64 address);
|
||||
NvU32 NV_API_CALL os_count_tail_pages (NvU64 address);
|
||||
void NV_API_CALL os_free_pages_phys (NvU64, NvU32);
|
||||
NV_STATUS NV_API_CALL os_call_nv_vmbus (NvU32, void *);
|
||||
NV_STATUS NV_API_CALL os_open_temporary_file (void **);
|
||||
void NV_API_CALL os_close_file (void *);
|
||||
NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64);
|
||||
NV_STATUS NV_API_CALL os_read_file (void *, NvU8 *, NvU64, NvU64);
|
||||
NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **);
|
||||
NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64);
|
||||
NvBool NV_API_CALL os_is_nvswitch_present (void);
|
||||
void NV_API_CALL os_get_random_bytes (NvU8 *, NvU16);
|
||||
NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **);
|
||||
void NV_API_CALL os_free_wait_queue (os_wait_queue *);
|
||||
void NV_API_CALL os_wait_uninterruptible (os_wait_queue *);
|
||||
void NV_API_CALL os_wait_interruptible (os_wait_queue *);
|
||||
void NV_API_CALL os_wake_up (os_wait_queue *);
|
||||
nv_cap_t* NV_API_CALL os_nv_cap_init (const char *);
|
||||
nv_cap_t* NV_API_CALL os_nv_cap_create_dir_entry (nv_cap_t *, const char *, int);
|
||||
nv_cap_t* NV_API_CALL os_nv_cap_create_file_entry (nv_cap_t *, const char *, int);
|
||||
void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *);
|
||||
int NV_API_CALL os_nv_cap_validate_and_dup_fd(const nv_cap_t *, int);
|
||||
void NV_API_CALL os_nv_cap_close_fd (int);
|
||||
|
||||
|
||||
NV_STATUS NV_API_CALL os_get_tegra_platform (NvU32 *);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
extern NvU32 os_page_size;
|
||||
extern NvU64 os_page_mask;
|
||||
extern NvU8 os_page_shift;
|
||||
extern NvU32 os_sev_status;
|
||||
extern NvBool os_sev_enabled;
|
||||
extern NvBool os_dma_buf_enabled;
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
*
|
||||
* Debug macros.
|
||||
*
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define NV_DBG_INFO 0x0
|
||||
#define NV_DBG_SETUP 0x1
|
||||
#define NV_DBG_USERERRORS 0x2
|
||||
#define NV_DBG_WARNINGS 0x3
|
||||
#define NV_DBG_ERRORS 0x4
|
||||
|
||||
|
||||
void NV_API_CALL out_string(const char *str);
|
||||
int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...);
|
||||
|
||||
#define NV_DEV_PRINTF(debuglevel, nv, format, ... ) \
|
||||
nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format, NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__)
|
||||
|
||||
#define NV_DEV_PRINTF_STATUS(debuglevel, nv, status, format, ... ) \
|
||||
nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format " (0x%x)\n", NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__, status)
|
||||
|
||||
/*
|
||||
* Fields for os_lock_user_pages flags parameter
|
||||
*/
|
||||
#define NV_LOCK_USER_PAGES_FLAGS_WRITE 0:0
|
||||
#define NV_LOCK_USER_PAGES_FLAGS_WRITE_NO 0x00000000
|
||||
#define NV_LOCK_USER_PAGES_FLAGS_WRITE_YES 0x00000001
|
||||
|
||||
|
||||
// NV OS Tegra platform type defines
|
||||
#define NV_OS_TEGRA_PLATFORM_SIM 0
|
||||
#define NV_OS_TEGRA_PLATFORM_FPGA 1
|
||||
#define NV_OS_TEGRA_PLATFORM_SILICON 2
|
||||
|
||||
|
||||
#endif /* OS_INTERFACE_H */
|
||||
41
nvdisplay/kernel-open/common/inc/os/nv_memory_type.h
Normal file
41
nvdisplay/kernel-open/common/inc/os/nv_memory_type.h
Normal file
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef NV_MEMORY_TYPE_H
|
||||
#define NV_MEMORY_TYPE_H
|
||||
|
||||
#define NV_MEMORY_NONCONTIGUOUS 0
|
||||
#define NV_MEMORY_CONTIGUOUS 1
|
||||
|
||||
#define NV_MEMORY_CACHED 0
|
||||
#define NV_MEMORY_UNCACHED 1
|
||||
#define NV_MEMORY_WRITECOMBINED 2
|
||||
#define NV_MEMORY_WRITEBACK 5
|
||||
#define NV_MEMORY_DEFAULT 6
|
||||
#define NV_MEMORY_UNCACHED_WEAK 7
|
||||
|
||||
#define NV_PROTECT_READABLE 1
|
||||
#define NV_PROTECT_WRITEABLE 2
|
||||
#define NV_PROTECT_READ_WRITE (NV_PROTECT_READABLE | NV_PROTECT_WRITEABLE)
|
||||
|
||||
#endif /* NV_MEMORY_TYPE_H */
|
||||
364
nvdisplay/kernel-open/common/inc/os_dsi_panel_props.h
Normal file
364
nvdisplay/kernel-open/common/inc/os_dsi_panel_props.h
Normal file
@@ -0,0 +1,364 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _OS_DSI_PANEL_PARAMS_H_
|
||||
#define _OS_DSI_PANEL_PARAMS_H_
|
||||
|
||||
#define DSI_GENERIC_LONG_WRITE 0x29
|
||||
#define DSI_DCS_LONG_WRITE 0x39
|
||||
#define DSI_GENERIC_SHORT_WRITE_1_PARAMS 0x13
|
||||
#define DSI_GENERIC_SHORT_WRITE_2_PARAMS 0x23
|
||||
#define DSI_DCS_WRITE_0_PARAM 0x05
|
||||
#define DSI_DCS_WRITE_1_PARAM 0x15
|
||||
#define DSI_DCS_READ_PARAM 0x06
|
||||
#define DSI_DCS_COMPRESSION_MODE 0x07
|
||||
#define DSI_DCS_PPS_LONG_WRITE 0x0A
|
||||
|
||||
#define DSI_DCS_SET_ADDR_MODE 0x36
|
||||
#define DSI_DCS_EXIT_SLEEP_MODE 0x11
|
||||
#define DSI_DCS_ENTER_SLEEP_MODE 0x10
|
||||
#define DSI_DCS_SET_DISPLAY_ON 0x29
|
||||
#define DSI_DCS_SET_DISPLAY_OFF 0x28
|
||||
#define DSI_DCS_SET_TEARING_EFFECT_OFF 0x34
|
||||
#define DSI_DCS_SET_TEARING_EFFECT_ON 0x35
|
||||
#define DSI_DCS_NO_OP 0x0
|
||||
#define DSI_NULL_PKT_NO_DATA 0x9
|
||||
#define DSI_BLANKING_PKT_NO_DATA 0x19
|
||||
#define DSI_DCS_SET_COMPRESSION_METHOD 0xC0
|
||||
|
||||
/* DCS commands for command mode */
|
||||
#define DSI_ENTER_PARTIAL_MODE 0x12
|
||||
#define DSI_SET_PIXEL_FORMAT 0x3A
|
||||
#define DSI_AREA_COLOR_MODE 0x4C
|
||||
#define DSI_SET_PARTIAL_AREA 0x30
|
||||
#define DSI_SET_PAGE_ADDRESS 0x2B
|
||||
#define DSI_SET_ADDRESS_MODE 0x36
|
||||
#define DSI_SET_COLUMN_ADDRESS 0x2A
|
||||
#define DSI_WRITE_MEMORY_START 0x2C
|
||||
#define DSI_WRITE_MEMORY_CONTINUE 0x3C
|
||||
|
||||
#define PKT_ID0(id) ((((id) & 0x3f) << 3) | \
|
||||
(((DSI_ENABLE) & 0x1) << 9))
|
||||
#define PKT_LEN0(len) (((len) & 0x7) << 0)
|
||||
#define PKT_ID1(id) ((((id) & 0x3f) << 13) | \
|
||||
(((DSI_ENABLE) & 0x1) << 19))
|
||||
#define PKT_LEN1(len) (((len) & 0x7) << 10)
|
||||
#define PKT_ID2(id) ((((id) & 0x3f) << 23) | \
|
||||
(((DSI_ENABLE) & 0x1) << 29))
|
||||
#define PKT_LEN2(len) (((len) & 0x7) << 20)
|
||||
#define PKT_ID3(id) ((((id) & 0x3f) << 3) | \
|
||||
(((DSI_ENABLE) & 0x1) << 9))
|
||||
#define PKT_LEN3(len) (((len) & 0x7) << 0)
|
||||
#define PKT_ID4(id) ((((id) & 0x3f) << 13) | \
|
||||
(((DSI_ENABLE) & 0x1) << 19))
|
||||
#define PKT_LEN4(len) (((len) & 0x7) << 10)
|
||||
#define PKT_ID5(id) ((((id) & 0x3f) << 23) | \
|
||||
(((DSI_ENABLE) & 0x1) << 29))
|
||||
#define PKT_LEN5(len) (((len) & 0x7) << 20)
|
||||
#define PKT_LP (((DSI_ENABLE) & 0x1) << 30)
|
||||
#define NUMOF_PKT_SEQ 12
|
||||
|
||||
/* DSI pixel data format, enum values should match with dt-bindings in tegra-panel.h */
|
||||
typedef enum
|
||||
{
|
||||
DSI_PIXEL_FORMAT_16BIT_P,
|
||||
DSI_PIXEL_FORMAT_18BIT_P,
|
||||
DSI_PIXEL_FORMAT_18BIT_NP,
|
||||
DSI_PIXEL_FORMAT_24BIT_P,
|
||||
DSI_PIXEL_FORMAT_8BIT_DSC,
|
||||
DSI_PIXEL_FORMAT_12BIT_DSC,
|
||||
DSI_PIXEL_FORMAT_16BIT_DSC,
|
||||
DSI_PIXEL_FORMAT_10BIT_DSC,
|
||||
DSI_PIXEL_FORMAT_30BIT_P,
|
||||
DSI_PIXEL_FORMAT_36BIT_P,
|
||||
} DSIPIXELFORMAT;
|
||||
|
||||
/* DSI virtual channel number */
|
||||
typedef enum
|
||||
{
|
||||
DSI_VIRTUAL_CHANNEL_0,
|
||||
DSI_VIRTUAL_CHANNEL_1,
|
||||
DSI_VIRTUAL_CHANNEL_2,
|
||||
DSI_VIRTUAL_CHANNEL_3,
|
||||
} DSIVIRTUALCHANNEL;
|
||||
|
||||
/* DSI transmit method for video data */
|
||||
typedef enum
|
||||
{
|
||||
DSI_VIDEO_TYPE_VIDEO_MODE,
|
||||
DSI_VIDEO_TYPE_COMMAND_MODE,
|
||||
} DSIVIDEODATAMODE;
|
||||
|
||||
/* DSI HS clock mode */
|
||||
typedef enum
|
||||
{
|
||||
DSI_VIDEO_CLOCK_CONTINUOUS,
|
||||
DSI_VIDEO_CLOCK_TX_ONLY,
|
||||
} DSICLOCKMODE;
|
||||
|
||||
/* DSI burst mode setting in video mode. Each mode is assigned with a
|
||||
* fixed value. The rationale behind this is to avoid change of these
|
||||
* values, since the calculation of dsi clock depends on them. */
|
||||
typedef enum
|
||||
{
|
||||
DSI_VIDEO_NON_BURST_MODE = 0,
|
||||
DSI_VIDEO_NON_BURST_MODE_WITH_SYNC_END = 1,
|
||||
DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
|
||||
DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
|
||||
DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
|
||||
DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
|
||||
DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
|
||||
} DSIVIDEOBURSTMODE;
|
||||
|
||||
/* DSI Ganged Mode */
|
||||
typedef enum
|
||||
{
|
||||
DSI_GANGED_SYMMETRIC_LEFT_RIGHT = 1,
|
||||
DSI_GANGED_SYMMETRIC_EVEN_ODD = 2,
|
||||
DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP = 3,
|
||||
} DSIGANGEDTYPE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DSI_LINK0,
|
||||
DSI_LINK1,
|
||||
} DSILINKNUM;
|
||||
|
||||
/* DSI Command Packet type */
|
||||
typedef enum
|
||||
{
|
||||
DSI_PACKET_CMD,
|
||||
DSI_DELAY_MS,
|
||||
DSI_GPIO_SET,
|
||||
DSI_SEND_FRAME,
|
||||
DSI_PACKET_VIDEO_VBLANK_CMD,
|
||||
DSI_DELAY_US,
|
||||
} DSICMDPKTTYPE;
|
||||
|
||||
/* DSI Phy type */
|
||||
typedef enum
|
||||
{
|
||||
DSI_DPHY,
|
||||
DSI_CPHY,
|
||||
} DSIPHYTYPE;
|
||||
|
||||
enum {
|
||||
DSI_GPIO_LCD_RESET,
|
||||
DSI_GPIO_PANEL_EN,
|
||||
DSI_GPIO_PANEL_EN_1,
|
||||
DSI_GPIO_BL_ENABLE,
|
||||
DSI_GPIO_BL_PWM,
|
||||
DSI_GPIO_AVDD_AVEE_EN,
|
||||
DSI_GPIO_VDD_1V8_LCD_EN,
|
||||
DSI_GPIO_TE,
|
||||
DSI_GPIO_BRIDGE_EN_0,
|
||||
DSI_GPIO_BRIDGE_EN_1,
|
||||
DSI_GPIO_BRIDGE_REFCLK_EN,
|
||||
DSI_N_GPIO_PANEL, /* add new gpio above this entry */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
DSI_DISABLE,
|
||||
DSI_ENABLE,
|
||||
};
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU8 cmd_type;
|
||||
NvU8 data_id;
|
||||
union
|
||||
{
|
||||
NvU16 data_len;
|
||||
NvU16 delay_ms;
|
||||
NvU16 delay_us;
|
||||
NvU32 gpio;
|
||||
NvU16 frame_cnt;
|
||||
struct
|
||||
{
|
||||
NvU8 data0;
|
||||
NvU8 data1;
|
||||
} sp;
|
||||
} sp_len_dly;
|
||||
NvU32 *pdata;
|
||||
NvU8 link_id;
|
||||
NvBool club_cmd;
|
||||
} DSI_CMD, *PDSICMD;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU16 t_hsdexit_ns;
|
||||
NvU16 t_hstrail_ns;
|
||||
NvU16 t_datzero_ns;
|
||||
NvU16 t_hsprepare_ns;
|
||||
NvU16 t_hsprebegin_ns;
|
||||
NvU16 t_hspost_ns;
|
||||
|
||||
NvU16 t_clktrail_ns;
|
||||
NvU16 t_clkpost_ns;
|
||||
NvU16 t_clkzero_ns;
|
||||
NvU16 t_tlpx_ns;
|
||||
|
||||
NvU16 t_clkprepare_ns;
|
||||
NvU16 t_clkpre_ns;
|
||||
NvU16 t_wakeup_ns;
|
||||
|
||||
NvU16 t_taget_ns;
|
||||
NvU16 t_tasure_ns;
|
||||
NvU16 t_tago_ns;
|
||||
} DSI_PHY_TIMING_IN_NS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 hActive;
|
||||
NvU32 vActive;
|
||||
NvU32 hFrontPorch;
|
||||
NvU32 vFrontPorch;
|
||||
NvU32 hBackPorch;
|
||||
NvU32 vBackPorch;
|
||||
NvU32 hSyncWidth;
|
||||
NvU32 vSyncWidth;
|
||||
NvU32 hPulsePolarity;
|
||||
NvU32 vPulsePolarity;
|
||||
NvU32 pixelClkRate;
|
||||
} DSITIMINGS, *PDSITIMINGS;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU8 n_data_lanes; /* required */
|
||||
NvU8 pixel_format; /* required */
|
||||
NvU8 refresh_rate; /* required */
|
||||
NvU8 rated_refresh_rate;
|
||||
NvU8 panel_reset; /* required */
|
||||
NvU8 virtual_channel; /* required */
|
||||
NvU8 dsi_instance;
|
||||
NvU16 dsi_panel_rst_gpio;
|
||||
NvU16 dsi_panel_bl_en_gpio;
|
||||
NvU16 dsi_panel_bl_pwm_gpio;
|
||||
NvU16 even_odd_split_width;
|
||||
NvU8 controller_vs;
|
||||
|
||||
NvBool panel_has_frame_buffer; /* required*/
|
||||
|
||||
/* Deprecated. Use DSI_SEND_FRAME panel command instead. */
|
||||
NvBool panel_send_dc_frames;
|
||||
|
||||
DSI_CMD *dsi_init_cmd; /* required */
|
||||
NvU16 n_init_cmd; /* required */
|
||||
NvBool sendInitCmdsEarly;
|
||||
|
||||
DSI_CMD *dsi_early_suspend_cmd;
|
||||
NvU16 n_early_suspend_cmd;
|
||||
|
||||
DSI_CMD *dsi_late_resume_cmd;
|
||||
NvU16 n_late_resume_cmd;
|
||||
|
||||
DSI_CMD *dsi_postvideo_cmd;
|
||||
NvU16 n_postvideo_cmd;
|
||||
|
||||
DSI_CMD *dsi_suspend_cmd; /* required */
|
||||
NvU16 n_suspend_cmd; /* required */
|
||||
|
||||
NvU8 video_data_type; /* required */
|
||||
NvU8 video_clock_mode;
|
||||
NvU8 video_burst_mode;
|
||||
NvU8 ganged_type;
|
||||
NvU16 ganged_overlap;
|
||||
NvBool ganged_swap_links;
|
||||
NvBool ganged_write_to_all_links;
|
||||
NvU8 split_link_type;
|
||||
|
||||
NvU8 suspend_aggr;
|
||||
|
||||
NvU16 panel_buffer_size_byte;
|
||||
NvU16 panel_reset_timeout_msec;
|
||||
|
||||
NvBool hs_cmd_mode_supported;
|
||||
NvBool hs_cmd_mode_on_blank_supported;
|
||||
NvBool enable_hs_clock_on_lp_cmd_mode;
|
||||
NvBool no_pkt_seq_eot; /* 1st generation panel may not
|
||||
* support eot. Don't set it for
|
||||
* most panels.*/
|
||||
const NvU32 *pktSeq;
|
||||
NvBool skip_dsi_pkt_header;
|
||||
NvBool power_saving_suspend;
|
||||
NvBool suspend_stop_stream_late;
|
||||
NvBool dsi2lvds_bridge_enable;
|
||||
NvBool dsi2edp_bridge_enable;
|
||||
|
||||
NvU32 max_panel_freq_khz;
|
||||
NvU32 lp_cmd_mode_freq_khz;
|
||||
NvU32 lp_read_cmd_mode_freq_khz;
|
||||
NvU32 hs_clk_in_lp_cmd_mode_freq_khz;
|
||||
NvU32 burst_mode_freq_khz;
|
||||
NvU32 fpga_freq_khz;
|
||||
|
||||
NvU32 te_gpio;
|
||||
NvBool te_polarity_low;
|
||||
NvBool dsiEnVRR;
|
||||
NvBool dsiVrrPanelSupportsTe;
|
||||
NvBool dsiForceSetTePin;
|
||||
|
||||
int panel_gpio[DSI_N_GPIO_PANEL];
|
||||
NvBool panel_gpio_populated;
|
||||
|
||||
NvU32 dpd_dsi_pads;
|
||||
|
||||
DSI_PHY_TIMING_IN_NS phyTimingNs;
|
||||
|
||||
NvU8 *bl_name;
|
||||
|
||||
NvBool lp00_pre_panel_wakeup;
|
||||
NvBool ulpm_not_supported;
|
||||
NvBool use_video_host_fifo_for_cmd;
|
||||
NvBool dsi_csi_loopback;
|
||||
NvBool set_max_timeout;
|
||||
NvBool use_legacy_dphy_core;
|
||||
// Swap P/N pins polarity of all data lanes
|
||||
NvBool swap_data_lane_polarity;
|
||||
// Swap P/N pins polarity of clock lane
|
||||
NvBool swap_clock_lane_polarity;
|
||||
// Reverse clock polarity for partition A/B. 1st SOT bit goes on negedge of Clock lane
|
||||
NvBool reverse_clock_polarity;
|
||||
// DSI Lane Crossbar. Allocating xbar array for max number of lanes
|
||||
NvBool lane_xbar_exists;
|
||||
NvU32 lane_xbar_ctrl[8];
|
||||
NvU32 refresh_rate_adj;
|
||||
|
||||
NvU8 dsiPhyType;
|
||||
|
||||
DSITIMINGS dsiTimings;
|
||||
|
||||
// DSC Parameters
|
||||
NvBool dsiDscEnable;
|
||||
NvU32 dsiDscBpp;
|
||||
NvU32 dsiDscNumSlices;
|
||||
NvU32 dsiDscSliceWidth;
|
||||
NvU32 dsiDscSliceHeight;
|
||||
NvBool dsiDscEnBlockPrediction;
|
||||
NvBool dsiDscEnDualDsc;
|
||||
NvU32 dsiDscDecoderMajorVersion;
|
||||
NvU32 dsiDscDecoderMinorVersion;
|
||||
} DSI_PANEL_INFO;
|
||||
|
||||
#endif
|
||||
32
nvdisplay/kernel-open/common/inc/os_gpio.h
Normal file
32
nvdisplay/kernel-open/common/inc/os_gpio.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _OS_GPIO_H_
|
||||
#define _OS_GPIO_H_
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NV_OS_GPIO_FUNC_HOTPLUG_A,
|
||||
NV_OS_GPIO_FUNC_HOTPLUG_B,
|
||||
} NV_OS_GPIO_FUNC_NAMES;
|
||||
|
||||
#endif
|
||||
110
nvdisplay/kernel-open/common/inc/rm-gpu-ops.h
Normal file
110
nvdisplay/kernel-open/common/inc/rm-gpu-ops.h
Normal file
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RM_GPU_OPS_H_
|
||||
#define _RM_GPU_OPS_H_
|
||||
|
||||
|
||||
|
||||
#include <nvtypes.h>
|
||||
#include <nvCpuUuid.h>
|
||||
#include "nv_stdarg.h"
|
||||
#include <nv-ioctl.h>
|
||||
#include <nvmisc.h>
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_create_session (nvidia_stack_t *, nvgpuSessionHandle_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_destroy_session (nvidia_stack_t *, nvgpuSessionHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_device_create (nvidia_stack_t *, nvgpuSessionHandle_t, const nvgpuInfo_t *, const NvProcessorUuid *, nvgpuDeviceHandle_t *, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_device_destroy (nvidia_stack_t *, nvgpuDeviceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create(nvidia_stack_t *, nvgpuDeviceHandle_t, unsigned long long, unsigned long long, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_dup_address_space(nvidia_stack_t *, nvgpuDeviceHandle_t, NvHandle, NvHandle, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_address_space_destroy(nvidia_stack_t *, nvgpuAddressSpaceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_fb(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvLength, NvU64 *, nvgpuAllocInfo_t);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages(nvidia_stack_t *, void *, NvLength, NvU32 , nvgpuPmaAllocationOptions_t, NvU64 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_free_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_pma_object(nvidia_stack_t *, nvgpuDeviceHandle_t, void **, const nvgpuPmaStatistics_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_register_callbacks(nvidia_stack_t *sp, void *, nvPmaEvictPagesCallback, nvPmaEvictRangeCallback, void *);
|
||||
void NV_API_CALL rm_gpu_ops_pma_unregister_callbacks(nvidia_stack_t *sp, void *);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_sys(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvLength, NvU64 *, nvgpuAllocInfo_t);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_p2p_caps(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuDeviceHandle_t, nvgpuP2PCapsParams_t);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_map(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, NvLength, void **, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_memory_cpu_ummap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, void*);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_channel_allocate(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, const nvgpuChannelAllocParams_t *, nvgpuChannelHandle_t *, nvgpuChannelInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_channel_destroy(nvidia_stack_t *, nvgpuChannelHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_memory_free(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_query_caps(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuCaps_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_query_ces_caps(nvidia_stack_t *sp, nvgpuDeviceHandle_t, nvgpuCesCaps_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_gpu_info(nvidia_stack_t *, const NvProcessorUuid *pUuid, const nvgpuClientInfo_t *, nvgpuInfo_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_service_device_interrupts_rm(nvidia_stack_t *, nvgpuDeviceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_dup_allocation(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuAddressSpaceHandle_t, NvU64, NvU64 *);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_dup_memory (nvidia_stack_t *, nvgpuDeviceHandle_t, NvHandle, NvHandle, NvHandle *, nvgpuMemoryInfo_t);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_free_duped_handle(nvidia_stack_t *, nvgpuDeviceHandle_t, NvHandle);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_fb_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFbInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_ecc_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuEccInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_own_page_fault_intr(nvidia_stack_t *, nvgpuDeviceHandle_t, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_init_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, void *, NvU32 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_own_access_cntr_intr(nvidia_stack_t *, nvgpuSessionHandle_t, nvgpuAccessCntrInfo_t, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, nvgpuAccessCntrConfig_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_disable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_unset_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_p2p_object_create(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuDeviceHandle_t, NvHandle *);
|
||||
void NV_API_CALL rm_gpu_ops_p2p_object_destroy(nvidia_stack_t *, nvgpuSessionHandle_t, NvHandle);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_external_alloc_ptes(nvidia_stack_t*, nvgpuAddressSpaceHandle_t, NvHandle, NvU64, NvU64, nvgpuExternalMappingInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_retain_channel(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvHandle, NvHandle, void **, nvgpuChannelInstanceInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_bind_channel_resources(nvidia_stack_t *, void *, nvgpuChannelResourceBindParams_t);
|
||||
void NV_API_CALL rm_gpu_ops_release_channel(nvidia_stack_t *, void *);
|
||||
void NV_API_CALL rm_gpu_ops_stop_channel(nvidia_stack_t *, void *, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_channel_resource_ptes(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvP64, NvU64, NvU64, nvgpuExternalMappingInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_report_non_replayable_fault(nvidia_stack_t *, nvgpuDeviceHandle_t, const void *);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_allocate(nvidia_stack_t *, nvgpuDeviceHandle_t, const nvgpuPagingChannelAllocParams_t *, nvgpuPagingChannelHandle_t *, nvgpuPagingChannelInfo_t);
|
||||
void NV_API_CALL rm_gpu_ops_paging_channel_destroy(nvidia_stack_t *, nvgpuPagingChannelHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_paging_channels_map(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t, NvU64 *);
|
||||
void NV_API_CALL rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *, nvgpuPagingChannelHandle_t, char *, NvU32);
|
||||
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *, struct ccslContext_t **, nvgpuChannelHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *, struct ccslContext_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_log_device_encryption(nvidia_stack_t *, struct ccslContext_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *, NvU8 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *, NvU8 const *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *);
|
||||
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user