/*
 * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef __TEGRA_SE_CCC_H__
#define __TEGRA_SE_CCC_H__

#include <tegra_driver_se.h>

#define TEGRA_SE_CCC_AES_ENGINE			ENGINE_SE0_AES0

typedef int status_t;
typedef enum optee_tegra_se_cdev_id_e {
	OPTEE_TEGRA_SE_CDEV_SE0  = 0, /**< SE0 device [0] */
	OPTEE_TEGRA_SE_CDEV_PKA1 = 1, /**< PKA device [1] */
	OPTEE_TEGRA_SE_CDEV_RNG1 = 2, /**< RNG1 device [2] */
} optee_tegra_se_cdev_id_t;

#define TEGRA_INIT_CRYPTO_PROTO_DECLARED /* Prevent redundant declaration warning */
status_t tegra_init_crypto_devices(void);

status_t tegra_se_map_device(optee_tegra_se_cdev_id_t device_id, void **base_va);

#endif /* __TEGRA_SE_CCC_H__ */

