/*
 * SPDX-License-Identifier: BSD-2-Clause
 *
 * SPDX-FileCopyrightText: Copyright (c) 2020-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 */

#include <console.h>
#include <tegra_common.h>
#include <drivers/hfic.h>
#include <kernel/boot.h>

#ifdef CFG_TEGRA_TCU
#include <drivers/tegra_combined_uart.h>
#endif

#ifdef CFG_TEGRA_UTC
#include <drivers/tegra_utc.h>
#endif

#ifdef CFG_TEGRA_TCU
register_phys_mem_pgdir(MEM_AREA_IO_SEC, TEGRA_COMBUART_BASE, TEGRA_COMBUART_SIZE);
static struct tegra_combined_uart_data tcud;
#endif

#ifdef CFG_TEGRA_UTC
register_phys_mem_pgdir(MEM_AREA_IO_SEC, TEGRA_UTC_TX_BASE, TEGRA_UTC_TX_SIZE);
static struct tegra_utc_data utcd;
#endif

#if defined(PLATFORM_FLAVOR_t234)
#define TEGRA234_QSPI0_BASE		0x3270000
#define TEGRA234_QSPI0_SIZE		0x10000
register_phys_mem_pgdir(MEM_AREA_IO_SEC, TEGRA234_QSPI0_BASE, TEGRA234_QSPI0_SIZE);
#endif

#if defined(PLATFORM_FLAVOR_t234)
#define TEGRA234_SCRATCH_BASE		0xc390000
#define TEGRA234_SCRATCH_SIZE		0x1000
register_phys_mem_pgdir(MEM_AREA_IO_SEC, TEGRA234_SCRATCH_BASE, TEGRA234_SCRATCH_SIZE);
#endif

void plat_console_init(void)
{
#ifdef CFG_TEGRA_TCU
	struct io_pa_va base = { .pa = TEGRA_COMBUART_BASE };
#endif

#ifdef CFG_TEGRA_UTC
	struct io_pa_va utc_base = { .pa = TEGRA_UTC_TX_BASE };
#endif

	/* Check if there is a platform-specific console.
	 * If so, skip the Tegra Combined UART initialization below.
	 */
	if(tegra_console_init() == TEE_SUCCESS)
		return;

#ifdef CFG_TEGRA_TCU
	tegra_combined_uart_init(&tcud, base, TEGRA_COMBUART_SIZE);
	register_serial_console(&tcud.chip);
#endif

#ifdef CFG_TEGRA_UTC
	tegra_utc_init(&utcd, utc_base, TEGRA_UTC_TX_SIZE);
	register_serial_console(&utcd.chip);
#endif
}

#ifdef CFG_CORE_HAFNIUM_INTC
void boot_primary_init_intc(void)
{
	hfic_init();
}
#endif
