/*
 * SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef __TEGRA_SE_CCC_AES_H__
#define __TEGRA_SE_CCC_AES_H__

status_t tegra_se_ccc_configure_se0(vaddr_t base);
status_t tegra_se_ccc_set_aes_keyslot(uint32_t keyslot, uint8_t *key,
				      uint32_t key_len, se_aes_op_mode mode);
status_t tegra_se_ccc_aes_encrypt(uint8_t *src, size_t src_len,
				  uint8_t *dst, size_t dst_len,
				  se_aes_op_mode mode,
				  uint32_t keyslot, uint32_t key_len,
				  uint8_t *iv);
status_t tegra_se_ccc_clear_aes_keyslot(uint32_t keyslot);

#if defined(CFG_TEGRA_SE_USE_TEST_KEYS)
status_t tegra_se_ccc_set_test_oem_keys(const uint8_t *oem_k1, const uint8_t *oem_k2);
#endif

#endif /* __TEGRA_SE_CCC_AES_H__ */
