// SPDX-License-Identifier: BSD-2-Clause
/*
 * SPDX-FileCopyrightText: Copyright (c) 2022-2025, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 */

#ifndef __TEGRA_DRIVER_SE_H__
#define __TEGRA_DRIVER_SE_H__

#include <tee_api_types.h>
#include <types_ext.h>

#if defined(PLATFORM_FLAVOR_t234)
#define TEGRA_SE_BASE   0x03b50000
#define TEGRA_SE_SIZE   0x30000
#endif

#if defined(PLATFORM_FLAVOR_t264)
#define TEGRA_SE_BASE   0x8189850000
#define TEGRA_SE_SIZE   0x30000
#endif

/* Security Engine Operation Modes */
typedef enum
{
	SE_AES_OP_MODE_CBC,     /* Cipher Block Chaining (CBC) mode */
	SE_AES_OP_MODE_CMAC,    /* Cipher-based MAC (CMAC) mode */
	SE_AES_OP_MODE_ECB,     /* Electronic Codebook (ECB) mode */
	SE_AES_OP_MODE_HMAC,    /* Hash-based MAC (HMAC) mode */
} se_aes_op_mode;

typedef enum
{
	/** Message digests **/
	/**
	* SHA digests calculated/supported by the Tegra HW engine.
	* CRYPTO_HASH
	*/
	TEGRA_ALG_SHA1,        /**< SHA-1 */
	TEGRA_ALG_SHA224,      /**< SHA-224 */
	TEGRA_ALG_SHA256,      /**< SHA-256 */
	TEGRA_ALG_SHA384,      /**< SHA-384 */
	TEGRA_ALG_SHA512,      /**< SHA-512 */
} tegra_crypto_algo_mode;

TEE_Result tegra_se_map_regs(vaddr_t *va);

#endif
