/*
 * SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: BSD-2-Clause
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/dts-v1/;

/ {
	compatible = "arm,ffa-manifest-1.0";

	ffa-version = <0x00010001>; /* v1.1 */
	uuid = <0xe0786148 0xe311f8e7 0x02005ebc 0x1bc5d5a5>;
	id = <1>;
	description = "op-tee";

	execution-ctx-count = <14>; /* Number of vCPUs */
	exception-level = <2>; /* S-EL1 */
	execution-state = <0>; /* AARCH64 */

	/* This address will be updated by MB2 at runtime */
	load-address = <0x0 0x89A00000>;
	entrypoint-offset = <0x0 0x00004000>;

	xlat-granule = <0>; /* 4KiB */

	boot-order = <0>;

	messaging-method = <0x3>; /* FFA_MSG_SEND_DIRECT REQ_ABI only */
	ns-interrupts-action = <1>; /* NS_ACTION_ME */
	notification-support;

	mem-size = <0x02000000>; /* 32 MiB */

	#address-cells = <2>;
	#size-cells = <2>;

	/* Boot protocol */
	gp-register-num = <0x0>;
	boot-info {
		compatible = "arm,ffa-manifest-boot-info";
		ffa_manifest;
	};

	secure-chosen {
		/* MB2 updates the random seed at runtime */
		kaslr-seed = <0x863a14ea 0x799c0d0c>;
		stdout-path = "stdout";
	};

	aliases {
		stdout = &console;
	};

	console: ffa-console {
		compatible = "arm,ffa-console";
	};

	device-regions {
		compatible = "arm,ffa-manifest-device-regions";

		/* efuse */
		efuse {
			base-address = <0x00000000 0x01000000>;
			pages-count = <16>;
			attributes = <0x1>; /* Read-Only */
		};
		/* se0 */
		se0 {
			base-address = <0x00000081 0x89850000>;
			pages-count = <48>;
			attributes = <0x3>; /* Read-Write*/
		};
		/* rng1 */
		rng1 {
			base-address = <0x00000081 0x89870000>;
			pages-count = <8>;
			attributes = <0x3>; /* Read-Write*/
		};
		misc_reg {
			base-address = <0x00000000 0x80100000>;
			pages-count = <128>;
			attributes = <0x3>; /* Read-Write */
		};

		seu1_se0_reg {
			base-address = <0x00000081 0x89850000>;
			pages-count = <48>;
			attributes = <0x3>; /* Read-Write */
		};
		mailbox: mailbox_ie_reg {
			base-address = <0x0 0x08800000>;
			pages-count = <1>;
			attributes = <0x3>;
			interrupts = <0x29d 0xd01>; /* Secure, Level, PPI */
		};
		mailbox_slot_reg {
			base-address = <0x0 0x08830000>;
			pages-count = <16>;
			attributes = <0x3>; /* Read-Write */
		};
	};

	/* MB2 fills in the address and size of EKB blob at runtime. */
	ekb-blob@0 {
		compatible = "jetson-ekb-blob";
		reg = <0 0 0 0>;
		status = "disabled";
		secure-status = "disabled";
	};

	efuse@01000000 {
		compatible = "nvidia,tegra264-efuse";
		reg = <0x0 0x01000000 0x0 0x10000>;
		status = "disabled";
		secure-status = "okay";
	};

	se0@8189850000 {
		compatible = "nvidia,tegra264-se0";
		reg = <0x00000081 0x89850000 0x0 0x30000>;
		status = "disabled";
		secure-status = "okay";
	};

	rng1@8189870000 {
		compatible = "nvidia,tegra264-rng1";
		reg = <0x00000081 0x89870000 0x0 0x8000>;
		status = "disabled";
		secure-status = "okay";
	};

	hsp_sec2@8800000 {
		compatible = "nvidia,tegra264-hsp-sec2";
		device = <&mailbox>;
		shared-id = <0xf>;
		rx-id = <0x4>;
		tx-id = <0x5>;
		secure-status = "okay";
        };
};
