diff --git a/osi/core/core_common.c b/osi/core/core_common.c
index aa9aef1..b9693dc 100644
--- a/osi/core/core_common.c
+++ b/osi/core/core_common.c
@@ -259,6 +259,34 @@ nve32_t hw_config_fw_err_pkts(struct osi_core_priv_data *osi_core,
 fail:
 	return ret;
 }
+
+nve32_t hw_config_rxcsum_offload(struct osi_core_priv_data *const osi_core,
+				nveu32_t enabled)
+{
+	void *addr = osi_core->base;
+	nveu32_t value;
+	nve32_t ret = 0;
+	const nveu32_t rxcsum_mode[2] = { EQOS_MAC_MCR, MGBE_MAC_RMCR};
+	const nveu32_t ipc_value[2] = { EQOS_MCR_IPC, MGBE_MAC_RMCR_IPC};
+
+	if (enabled != OSI_ENABLE && enabled != OSI_DISABLE) {
+		ret = -1;
+		goto fail;
+	}
+
+	value = osi_readla(osi_core, ((nveu8_t *)addr + rxcsum_mode[osi_core->mac]));
+	if (enabled == OSI_ENABLE) {
+		value |= ipc_value[osi_core->mac];
+	} else {
+		value &= ~ipc_value[osi_core->mac];
+	}
+
+	osi_writela(osi_core, value, ((nveu8_t *)addr + rxcsum_mode[osi_core->mac]));
+fail:
+	return ret;
+}
+
+
 /**
  * @brief hw_est_read - indirect read the GCL to Software own list
  * (SWOL)
diff --git a/osi/core/core_common.h b/osi/core/core_common.h
index b0b00e6..62df704 100644
--- a/osi/core/core_common.h
+++ b/osi/core/core_common.h
@@ -70,4 +70,7 @@ nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core,
 			       const nveu32_t qinx);
 nve32_t hw_config_fw_err_pkts(struct osi_core_priv_data *osi_core,
 			      const nveu32_t qinx, const nveu32_t enable_fw_err_pkts);
+nve32_t hw_config_rxcsum_offload(struct osi_core_priv_data *const osi_core,
+				nveu32_t enabled);
+
 #endif /* INCLUDED_CORE_COMMON_H */
diff --git a/osi/core/core_local.h b/osi/core/core_local.h
index 357d030..4bf7547 100644
--- a/osi/core/core_local.h
+++ b/osi/core/core_local.h
@@ -97,10 +97,6 @@ struct core_ops {
 	void (*handle_common_intr)(struct osi_core_priv_data *const osi_core);
 	/** Called to do pad caliberation */
 	nve32_t (*pad_calibrate)(struct osi_core_priv_data *const osi_core);
-	/** Called to configure Rx Checksum offload engine */
-	nve32_t (*config_rxcsum_offload)(
-				struct osi_core_priv_data *const osi_core,
-				const nveu32_t enabled);
 	/** Called to config mac packet filter */
 	nve32_t (*config_mac_pkt_filter_reg)(
 				struct osi_core_priv_data *const osi_core,
diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c
index 011e965..845d9bb 100644
--- a/osi/core/eqos_core.c
+++ b/osi/core/eqos_core.c
@@ -984,61 +984,6 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t qinx,
 }
 /** \endcond */
 
-/**
- * @brief eqos_config_rxcsum_offload - Enable/Disable rx checksum offload in HW
- *
- * @note
- * Algorithm:
- *  - VAlidate enabled param and return -1 if invalid.
- *  - Read the MAC configuration register.
- *  - Enable/disable the IP checksum offload engine COE in MAC receiver based on enabled.
- *  - Update the MAC configuration register.
- *  - Refer to OSI column of <<RM_17, (sequence diagram)>> for sequence
- * of execution.
- *  - TraceID:ETHERNET_NVETHERNETRM_017
- *
- * @param[in] osi_core: OSI core private data structure. Used param is base.
- * @param[in] enabled: Flag to indicate feature is to be enabled(OSI_ENABLE)/disabled(OSI_DISABLE).
- *
- * @pre MAC should be initialized and started. see osi_start_mac()
- *
- * @note
- * API Group:
- * - Initialization: Yes
- * - Run time: Yes
- * - De-initialization: No
- *
- * @retval 0 on success
- * @retval -1 on failure.
- */
-static nve32_t eqos_config_rxcsum_offload(
-				      struct osi_core_priv_data *const osi_core,
-				      const nveu32_t enabled)
-{
-	void *addr = osi_core->base;
-	nveu32_t mac_mcr;
-
-	if ((enabled != OSI_ENABLE) && (enabled != OSI_DISABLE)) {
-		OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID,
-			     "rxsum_offload: invalid input\n", 0ULL);
-		return -1;
-	}
-
-	mac_mcr = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_MCR);
-
-	if (enabled == OSI_ENABLE) {
-		mac_mcr |= EQOS_MCR_IPC;
-	} else {
-		mac_mcr &= ~EQOS_MCR_IPC;
-	}
-
-	eqos_core_safety_writel(osi_core, mac_mcr,
-				(nveu8_t *)addr + EQOS_MAC_MCR,
-				EQOS_MAC_MCR_IDX);
-
-	return 0;
-}
-
 /**
  * @brief eqos_config_frp - Enable/Disale RX Flexible Receive Parser in HW
  *
@@ -6478,7 +6423,6 @@ void eqos_init_core_ops(struct core_ops *ops)
 	ops->core_deinit = eqos_core_deinit;
 	ops->handle_common_intr = eqos_handle_common_intr;
 	ops->pad_calibrate = eqos_pad_calibrate;
-	ops->config_rxcsum_offload = eqos_config_rxcsum_offload;
 	ops->config_mac_pkt_filter_reg = eqos_config_mac_pkt_filter_reg;
 	ops->update_mac_addr_low_high_reg = eqos_update_mac_addr_low_high_reg;
 	ops->config_l3_l4_filter_enable = eqos_config_l3_l4_filter_enable;
diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index 9d8b114..a9e40af 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -1668,45 +1668,6 @@ static int mgbe_config_arp_offload(struct osi_core_priv_data *const osi_core,
 	return 0;
 }
 
-/**
- * @brief mgbe_config_rxcsum_offload - Enable/Disale rx checksum offload in HW
- *
- * Algorithm:
- *      1) Read the MAC configuration register.
- *      2) Enable the IP checksum offload engine COE in MAC receiver.
- *      3) Update the MAC configuration register.
- *
- * @param[in] addr: MGBE virtual base address.
- * @param[in] enabled: Flag to indicate feature is to be enabled/disabled.
- *
- * @note MAC should be init and started. see osi_start_mac()
- *
- * @retval 0 on success
- * @retval -1 on failure.
- */
-static nve32_t mgbe_config_rxcsum_offload(
-				struct osi_core_priv_data *const osi_core,
-				nveu32_t enabled)
-{
-	void *addr = osi_core->base;
-	unsigned int mac_rmcr;
-
-	if ((enabled != OSI_ENABLE) && (enabled != OSI_DISABLE)) {
-		return -1;
-	}
-
-	mac_rmcr = osi_readla(osi_core, (unsigned char *)addr + MGBE_MAC_RMCR);
-	if (enabled == OSI_ENABLE) {
-		mac_rmcr |= MGBE_MAC_RMCR_IPC;
-	} else {
-		mac_rmcr &= ~MGBE_MAC_RMCR_IPC;
-	}
-
-	osi_writela(osi_core, mac_rmcr, (unsigned char *)addr + MGBE_MAC_RMCR);
-
-	return 0;
-}
-
 /**
  * @brief mgbe_config_frp - Enable/Disale RX Flexible Receive Parser in HW
  *
@@ -5939,7 +5900,6 @@ void mgbe_init_core_ops(struct core_ops *ops)
 	ops->config_flow_control = mgbe_config_flow_control;
 	ops->config_arp_offload = mgbe_config_arp_offload;
 	ops->config_ptp_offload = mgbe_config_ptp_offload;
-	ops->config_rxcsum_offload = mgbe_config_rxcsum_offload;
 	ops->config_mac_pkt_filter_reg = mgbe_config_mac_pkt_filter_reg;
 	ops->update_mac_addr_low_high_reg = mgbe_update_mac_addr_low_high_reg;
 	ops->config_l3_l4_filter_enable = mgbe_config_l3_l4_filter_enable;
diff --git a/osi/core/osi_hal.c b/osi/core/osi_hal.c
index ee2bccf..44f3f65 100644
--- a/osi/core/osi_hal.c
+++ b/osi/core/osi_hal.c
@@ -629,7 +629,7 @@ nve32_t osi_config_rxcsum_offload(struct osi_core_priv_data *const osi_core,
 		return -1;
 	}
 
-	return l_core->ops_p->config_rxcsum_offload(osi_core, enable);
+	return hw_config_rxcsum_offload(osi_core, enable);
 }
 
 nve32_t osi_set_systime_to_mac(struct osi_core_priv_data *const osi_core,
@@ -1702,7 +1702,7 @@ static void cfg_l2_filter(struct core_local *l_core)
 
 static void cfg_rxcsum(struct core_local *l_core)
 {
-	(void)l_core->ops_p->config_rxcsum_offload((struct osi_core_priv_data *)(void *)l_core,
+	(void)hw_config_rxcsum_offload((struct osi_core_priv_data *)(void *)l_core,
 						    l_core->cfg.rxcsum);
 }
 
@@ -2006,7 +2006,7 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core,
 		break;
 
 	case OSI_CMD_RXCSUM_OFFLOAD:
-		ret = ops_p->config_rxcsum_offload(osi_core, data->arg1_u32);
+		ret = hw_config_rxcsum_offload(osi_core, data->arg1_u32);
 		if (ret == 0) {
 			l_core->cfg.rxcsum = data->arg1_u32;
 			l_core->cfg.flags |= DYNAMIC_CFG_RXCSUM;