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nvethernetrm: fix Misra-C 2.x, 5.9 and 8.9

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Fix MISRA C-2012 Rule 2.3
Fix MISRA C-2012 Rule 2.4
Fix MISRA C-2012 Rule 2.5
Fix MISRA C-2012 Rule 5.9
Fix MISRA C-2012 Rule 8.9

Bug 200682334

Change-Id: Ie95e2f9d346d952fac1cf28f241522f35648be38
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2455622
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2457306
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
rakesh goyal
2020-12-05 18:27:56 +05:30
committed by Bhadram Varka
parent 38aa49eb4e
commit 01dd86e594
14 changed files with 374 additions and 337 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
include/mmc.h
View File

@@ -555,27 +555,4 @@ struct osi_xtra_stat_counters {
/** link disconnect count */ /** link disconnect count */
nveu64_t link_disconnect_count; nveu64_t link_disconnect_count;
}; };
/**
* @brief osi_xtra_dma_stat_counters - OSI DMA extra stats counters
*/
struct osi_xtra_dma_stat_counters {
/** Per Q TX packet count */
nveu64_t q_tx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Per Q RX packet count */
nveu64_t q_rx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Per Q TX complete call count */
nveu64_t tx_clean_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Total number of tx packets count */
nveu64_t tx_pkt_n;
/** Total number of rx packet count */
nveu64_t rx_pkt_n;
/** Total number of VLAN RX packet count */
nveu64_t rx_vlan_pkt_n;
/** Total number of VLAN TX packet count */
nveu64_t tx_vlan_pkt_n;
/** Total number of TSO packet count */
nveu64_t tx_tso_pkt_n;
};
#endif #endif

132
include/osi_common.h
View File

@@ -32,26 +32,22 @@
*/ */
#define OSI_UNLOCKED 0x0U #define OSI_UNLOCKED 0x0U
#define OSI_LOCKED 0x1U #define OSI_LOCKED 0x1U
#define TEN_POWER_9 0x3B9ACA00U
#define TWO_POWER_32 0x100000000ULL
#define TWO_POWER_31 0x80000000U
#define OSI_NSEC_PER_SEC 1000000000ULL #define OSI_NSEC_PER_SEC 1000000000ULL
#define OSI_INVALID_VALUE 0xFFFFFFFFU
#define OSI_PTP_REQ_CLK_FREQ 250000000U #ifndef OSI_STRIPPED_LIB
#define OSI_ONE_MEGA_HZ 1000000U
#define OSI_MAX_RX_COALESCE_USEC 1020U #define OSI_MAX_RX_COALESCE_USEC 1020U
#define OSI_MIN_RX_COALESCE_USEC 3U #define OSI_MIN_RX_COALESCE_USEC 3U
#define OSI_MIN_RX_COALESCE_FRAMES 1U #define OSI_MIN_RX_COALESCE_FRAMES 1U
#define OSI_MAX_TX_COALESCE_USEC 1020U #define OSI_MAX_TX_COALESCE_USEC 1020U
#define OSI_MIN_TX_COALESCE_USEC 32U #define OSI_MIN_TX_COALESCE_USEC 32U
#define OSI_MIN_TX_COALESCE_FRAMES 1U #define OSI_MIN_TX_COALESCE_FRAMES 1U
#endif /* !OSI_STRIPPED_LIB */
/* Compiler hints for branch prediction */ /* Compiler hints for branch prediction */
#define osi_likely(x) __builtin_expect(!!(x), 1)
#define osi_unlikely(x) __builtin_expect(!!(x), 0) #define osi_unlikely(x) __builtin_expect(!!(x), 0)
/** @} */ /** @} */
#ifndef OSI_STRIPPED_LIB
/** /**
* @addtogroup - LPI-Timers LPI configuration macros * @addtogroup - LPI-Timers LPI configuration macros
* *
@@ -96,8 +92,8 @@
*/ */
#define OSI_LPI_1US_TIC_COUNTER_DEFAULT 0xCBU #define OSI_LPI_1US_TIC_COUNTER_DEFAULT 0xCBU
#define OSI_LPI_1US_TIC_COUNTER_MASK 0xFFFU #define OSI_LPI_1US_TIC_COUNTER_MASK 0xFFFU
/** @} */ /** @} */
#endif /* !OSI_STRIPPED_LIB */
/** /**
* @addtogroup Helper Helper MACROS * @addtogroup Helper Helper MACROS
@@ -105,15 +101,15 @@
* @brief EQOS generic helper MACROS. * @brief EQOS generic helper MACROS.
* @{ * @{
*/ */
#ifndef OSI_STRIPPED_LIB
#define OSI_PAUSE_FRAMES_ENABLE 0U #define OSI_PAUSE_FRAMES_ENABLE 0U
#define OSI_PAUSE_FRAMES_DISABLE 1U #define OSI_PTP_REQ_CLK_FREQ 250000000U
#define OSI_FLOW_CTRL_TX OSI_BIT(0)
#define OSI_FLOW_CTRL_RX OSI_BIT(1)
#define OSI_FLOW_CTRL_DISABLE 0U #define OSI_FLOW_CTRL_DISABLE 0U
#define OSI_ADDRESS_32BIT 0 #define OSI_ADDRESS_32BIT 0
#define OSI_ADDRESS_40BIT 1 #define OSI_ADDRESS_40BIT 1
#define OSI_ADDRESS_48BIT 2 #define OSI_ADDRESS_48BIT 2
#endif /* !OSI_STRIPPED_LIB */
#ifndef UINT_MAX #ifndef UINT_MAX
#define UINT_MAX (~0U) #define UINT_MAX (~0U)
@@ -123,27 +119,6 @@
#endif #endif
/** @} */ /** @} */
/**
* @addtogroup EQOS_PTP PTP Helper MACROS
*
* @brief EQOS PTP MAC Time stamp control reg bit fields
* @{
*/
#define OSI_MAC_TCR_TSENA OSI_BIT(0)
#define OSI_MAC_TCR_TSCFUPDT OSI_BIT(1)
#define OSI_MAC_TCR_TSENALL OSI_BIT(8)
#define OSI_MAC_TCR_TSCTRLSSR OSI_BIT(9)
#define OSI_MAC_TCR_TSVER2ENA OSI_BIT(10)
#define OSI_MAC_TCR_TSIPENA OSI_BIT(11)
#define OSI_MAC_TCR_TSIPV6ENA OSI_BIT(12)
#define OSI_MAC_TCR_TSIPV4ENA OSI_BIT(13)
#define OSI_MAC_TCR_TSEVENTENA OSI_BIT(14)
#define OSI_MAC_TCR_TSMASTERENA OSI_BIT(15)
#define OSI_MAC_TCR_SNAPTYPSEL_1 OSI_BIT(16)
#define OSI_MAC_TCR_SNAPTYPSEL_2 OSI_BIT(17)
#define OSI_MAC_TCR_SNAPTYPSEL_3 (OSI_BIT(16) | OSI_BIT(17))
#define OSI_MAC_TCR_AV8021ASMEN OSI_BIT(28)
/** @} */
/** /**
* @addtogroup Helper Helper MACROS * @addtogroup Helper Helper MACROS
@@ -151,117 +126,60 @@
* @brief EQOS generic helper MACROS. * @brief EQOS generic helper MACROS.
* @{ * @{
*/ */
#define OSI_ULLONG_MAX (~0ULL)
#define OSI_UCHAR_MAX (0xFFU) #define OSI_UCHAR_MAX (0xFFU)
#define OSI_ULLONG_MAX (~0ULL)
/* Logging defines */ /* Logging defines */
/* log levels */ /* log levels */
#define OSI_LOG_INFO 1U
#define OSI_LOG_WARN 2U
#define OSI_LOG_ERR 3U #define OSI_LOG_ERR 3U
/* Error types */ /* Error types */
#define OSI_LOG_ARG_OUTOFBOUND 1U
#define OSI_LOG_ARG_INVALID 2U #define OSI_LOG_ARG_INVALID 2U
#ifndef OSI_STRIPPED_LIB
#define OSI_LOG_WARN 2U
#define OSI_LOG_ARG_OPNOTSUPP 3U #define OSI_LOG_ARG_OPNOTSUPP 3U
#define OSI_LOG_ARG_HW_FAIL 4U #endif /* !OSI_STRIPPED_LIB */
/* Default maximum Giant Packet Size Limit is 16K */ /* Default maximum Giant Packet Size Limit is 16K */
#define OSI_MAX_MTU_SIZE 16383U #define OSI_MAX_MTU_SIZE 16383U
#define OSI_MTU_SIZE_9000 9000U
#define OSI_DFLT_MTU_SIZE 1500U
#define EQOS_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x1160U) #define EQOS_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x1160U)
#define EQOS_DMA_CHX_IER(x) ((0x0080U * (x)) + 0x1134U)
/* FIXME add logic based on HW version */ /* FIXME add logic based on HW version */
#define EQOS_MAX_MAC_ADDRESS_FILTER 128U #define OSI_EQOS_MAX_NUM_CHANS 4U
#define EQOS_MAX_L3_L4_FILTER 8U #define OSI_EQOS_MAX_NUM_QUEUES 4U
#define EQOS_MAX_HTR_REGS 8U
#define OSI_EQOS_MAX_NUM_CHANS 8U
#define OSI_EQOS_MAX_NUM_QUEUES 8U
#define OSI_L2_FILTER_INDEX_ANY 127U
#define OSI_CHAN_ANY 0xFFU
/* HW supports 8 Hash table regs, but eqos_validate_core_regs only checks 4 */
#define OSI_EQOS_MAX_HASH_REGS 4U
/* L2 filter operations supported by OSI layer. These operation modes shall be
* set by OSD driver as input to update registers accordingly.
*/
#define OSI_OPER_EN_PROMISC OSI_BIT(0)
#define OSI_OPER_DIS_PROMISC OSI_BIT(1)
#define OSI_OPER_EN_ALLMULTI OSI_BIT(2)
#define OSI_OPER_DIS_ALLMULTI OSI_BIT(3)
#define OSI_OPER_EN_L2_DA_INV OSI_BIT(4)
#define OSI_OPER_DIS_L2_DA_INV OSI_BIT(5)
#define OSI_OPER_EN_PERFECT OSI_BIT(6)
#define OSI_OPER_DIS_PERFECT OSI_BIT(7)
#define OSI_OPER_ADDR_UPDATE OSI_BIT(8)
#define OSI_OPER_ADDR_DEL OSI_BIT(9)
#define MAC_VERSION 0x110 #define MAC_VERSION 0x110
#define MAC_VERSION_SNVER_MASK 0x7FU #define MAC_VERSION_SNVER_MASK 0x7FU
#define OSI_MAC_HW_EQOS 0U #define OSI_MAC_HW_EQOS 0U
#define OSI_ETH_ALEN 6U
#define OSI_MAX_VM_IRQS 5U
#define BOOLEAN_FALSE (0U != 0U)
#define OSI_NULL ((void *)0) #define OSI_NULL ((void *)0)
#define OSI_ENABLE 1U #define OSI_ENABLE 1U
#define OSI_NONE 0U #define OSI_NONE 0U
#define OSI_DISABLE 0U #define OSI_DISABLE 0U
#define OSI_AMASK_DISABLE 0U
#define OSI_HASH_FILTER_MODE 1U
#define OSI_PERFECT_FILTER_MODE 0U
#define OSI_IPV6_MATCH 1U
#define OSI_SOURCE_MATCH 0U
#define OSI_INV_MATCH 1U
#define OSI_PFT_MATCH 0U
#define OSI_SA_MATCH 1U
#define OSI_DA_MATCH 0U
#define OSI_L4_FILTER_TCP 0U
#define OSI_L4_FILTER_UDP 1U
#define OSI_IP4_FILTER 0U
#define OSI_IP6_FILTER 1U
#define CHECK_CHAN_BOUND(chan) \
{ \
if ((chan) >= OSI_EQOS_MAX_NUM_CHANS) { \
return; \
} \
} \
#define OSI_BIT(nr) ((nveu32_t)1 << (nr)) #define OSI_BIT(nr) ((nveu32_t)1 << (nr))
#define OSI_EQOS_MAC_4_10 0x41U #define OSI_EQOS_MAC_4_10 0x41U
#define OSI_EQOS_MAC_5_00 0x50U #define OSI_EQOS_MAC_5_00 0x50U
#define OSI_EQOS_MAC_5_10 0x51U #define OSI_EQOS_MAC_5_10 0x51U
#define OSI_MAX_VM_IRQS 5U
#define OSI_SPEED_10 10 #ifndef OSI_STRIPPED_LIB
#define OSI_SPEED_100 100 #define OSI_L2_FILTER_INDEX_ANY 127U
#define OSI_SPEED_1000 1000 #define OSI_HASH_FILTER_MODE 1U
#define OSI_L4_FILTER_TCP 0U
#define OSI_L4_FILTER_UDP 1U
#define OSI_PERFECT_FILTER_MODE 0U
#define OSI_FULL_DUPLEX 1
#define OSI_HALF_DUPLEX 0
#define NV_ETH_FRAME_LEN 1514U
#define NV_ETH_FCS_LEN 0x4U #define NV_ETH_FCS_LEN 0x4U
#define NV_VLAN_HLEN 0x4U #define NV_ETH_FRAME_LEN 1514U
#define OSI_ETH_HLEN 0xEU
#define OSI_NET_IP_ALIGN 0x2U
#define MAX_ETH_FRAME_LEN_DEFAULT \ #define MAX_ETH_FRAME_LEN_DEFAULT \
(NV_ETH_FRAME_LEN + NV_ETH_FCS_LEN + NV_VLAN_HLEN) (NV_ETH_FRAME_LEN + NV_ETH_FCS_LEN + NV_VLAN_HLEN)
#define L32(data) ((data) & 0xFFFFFFFFU)
#define H32(data) (((data) & 0xFFFFFFFF00000000UL) >> 32UL)
#define OSI_INVALID_CHAN_NUM 0xFFU #define OSI_INVALID_CHAN_NUM 0xFFU
#endif /* OSI_STRIPPED_LIB */
/** @} */ /** @} */
/** /**
@@ -302,7 +220,9 @@
#define EQOS_MAC_HFR1_TSOEN_MASK 0x1U #define EQOS_MAC_HFR1_TSOEN_MASK 0x1U
#define EQOS_MAC_HFR1_DMADEBUGEN_MASK 0x1U #define EQOS_MAC_HFR1_DMADEBUGEN_MASK 0x1U
#define EQOS_MAC_HFR1_AVSEL_MASK 0x1U #define EQOS_MAC_HFR1_AVSEL_MASK 0x1U
#ifndef OSI_STRIPPED_LIB
#define EQOS_MAC_HFR1_LPMODEEN_MASK 0x1U #define EQOS_MAC_HFR1_LPMODEEN_MASK 0x1U
#endif /* OSI_STRIPPED_LIB */
#define EQOS_MAC_HFR1_HASHTBLSZ_MASK 0x3U #define EQOS_MAC_HFR1_HASHTBLSZ_MASK 0x3U
#define EQOS_MAC_HFR1_L3L4FILTERNUM_MASK 0xfU #define EQOS_MAC_HFR1_L3L4FILTERNUM_MASK 0xfU
#define EQOS_MAC_HFR2_RXQCNT_MASK 0xfU #define EQOS_MAC_HFR2_RXQCNT_MASK 0xfU
@@ -313,6 +233,7 @@
#define EQOS_MAC_HFR2_AUXSNAPNUM_MASK 0x7U #define EQOS_MAC_HFR2_AUXSNAPNUM_MASK 0x7U
/** @} */ /** @} */
#ifndef OSI_STRIPPED_LIB
/** /**
* @addtogroup MTL queue operation mode * @addtogroup MTL queue operation mode
* *
@@ -334,6 +255,7 @@
#define OSI_MTL_TXQ_AVALG_CBS 1U #define OSI_MTL_TXQ_AVALG_CBS 1U
#define OSI_MTL_TXQ_AVALG_SP 0U #define OSI_MTL_TXQ_AVALG_SP 0U
/** @} */ /** @} */
#endif /* OSI_STRIPPED_LIB */
/** /**
* @brief struct osi_hw_features - MAC HW supported features. * @brief struct osi_hw_features - MAC HW supported features.

97
include/osi_core.h
View File

@@ -27,6 +27,16 @@
#include "mmc.h" #include "mmc.h"
#include "../osi/common/type.h" #include "../osi/common/type.h"
/* Following added to avoid misraC 4.6
* Here we are defining intermediate type
*/
typedef unsigned short my_uint16_t;
typedef long long my_lint_64;
/* Actual type used in code */
typedef my_uint16_t nveu16_t;
typedef my_lint_64 nvel64_t;
/** /**
* @addtogroup PTP related information * @addtogroup PTP related information
* *
@@ -35,6 +45,91 @@
*/ */
#define OSI_PTP_SSINC_16 16U #define OSI_PTP_SSINC_16 16U
#define OSI_PTP_SSINC_4 4U #define OSI_PTP_SSINC_4 4U
/** @} */
/**
* @addtogroup EQOS_PTP PTP Helper MACROS
*
* @brief EQOS PTP MAC Time stamp control reg bit fields
* @{
*/
#define OSI_MAC_TCR_TSENA OSI_BIT(0)
#define OSI_MAC_TCR_TSCFUPDT OSI_BIT(1)
#define OSI_MAC_TCR_TSENALL OSI_BIT(8)
#define OSI_MAC_TCR_TSCTRLSSR OSI_BIT(9)
#define OSI_MAC_TCR_TSVER2ENA OSI_BIT(10)
#define OSI_MAC_TCR_TSIPENA OSI_BIT(11)
#define OSI_MAC_TCR_TSIPV6ENA OSI_BIT(12)
#define OSI_MAC_TCR_TSIPV4ENA OSI_BIT(13)
#define OSI_MAC_TCR_TSEVENTENA OSI_BIT(14)
#define OSI_MAC_TCR_TSMASTERENA OSI_BIT(15)
#define OSI_MAC_TCR_SNAPTYPSEL_1 OSI_BIT(16)
#define OSI_MAC_TCR_SNAPTYPSEL_2 OSI_BIT(17)
#define OSI_MAC_TCR_SNAPTYPSEL_3 (OSI_BIT(16) | OSI_BIT(17))
#define OSI_MAC_TCR_AV8021ASMEN OSI_BIT(28)
/** @} */
/**
* @addtogroup Helper Helper MACROS
*
* @brief EQOS generic helper MACROS.
* @{
*/
#define EQOS_DMA_CHX_IER(x) ((0x0080U * (x)) + 0x1134U)
#define EQOS_MAX_MAC_ADDRESS_FILTER 128U
#define EQOS_MAX_L3_L4_FILTER 8U
#define EQOS_MAX_HTR_REGS 8U
#define OSI_DA_MATCH 0U
#define OSI_INV_MATCH 1U
#define OSI_AMASK_DISABLE 0U
#define OSI_CHAN_ANY 0xFFU
#define OSI_DFLT_MTU_SIZE 1500U
#define OSI_MTU_SIZE_9000 9000U
/* HW supports 8 Hash table regs, but eqos_validate_core_regs only checks 4 */
#define OSI_EQOS_MAX_HASH_REGS 4U
#define OSI_ETH_ALEN 6U
#define OSI_FLOW_CTRL_TX OSI_BIT(0)
#define OSI_FLOW_CTRL_RX OSI_BIT(1)
#define OSI_FULL_DUPLEX 1
#define OSI_HALF_DUPLEX 0
#define OSI_IP4_FILTER 0U
#define OSI_IP6_FILTER 1U
#define OSI_IPV6_MATCH 1U
#define OSI_LOG_INFO 1U
#define OSI_LOG_ARG_HW_FAIL 4U
#define OSI_LOG_ARG_OUTOFBOUND 1U
/* L2 filter operations supported by OSI layer. These operation modes shall be
* set by OSD driver as input to update registers accordingly.
*/
#define OSI_OPER_EN_PROMISC OSI_BIT(0)
#define OSI_OPER_DIS_PROMISC OSI_BIT(1)
#define OSI_OPER_EN_ALLMULTI OSI_BIT(2)
#define OSI_OPER_DIS_ALLMULTI OSI_BIT(3)
#define OSI_OPER_EN_L2_DA_INV OSI_BIT(4)
#define OSI_OPER_DIS_L2_DA_INV OSI_BIT(5)
#define OSI_OPER_EN_PERFECT OSI_BIT(6)
#define OSI_OPER_DIS_PERFECT OSI_BIT(7)
#define OSI_OPER_ADDR_UPDATE OSI_BIT(8)
#define OSI_OPER_ADDR_DEL OSI_BIT(9)
#define OSI_PAUSE_FRAMES_DISABLE 1U
#define OSI_PFT_MATCH 0U
#define OSI_SOURCE_MATCH 0U
#define OSI_SA_MATCH 1U
#define OSI_SPEED_10 10
#define OSI_SPEED_100 100
#define OSI_SPEED_1000 1000
#define TEN_POWER_9 0x3B9ACA00U
#define TWO_POWER_32 0x100000000ULL
#define TWO_POWER_31 0x80000000U
/** @} */ /** @} */
/* to avoid re definition when both core and dma headers are included */ /* to avoid re definition when both core and dma headers are included */
@@ -116,6 +211,7 @@ struct osi_l3_l4_filter {
nveu16_t port_no; nveu16_t port_no;
}; };
#ifndef OSI_STRIPPED_LIB
/** /**
* @brief Vlan filter Function dependent parameter * @brief Vlan filter Function dependent parameter
*/ */
@@ -138,7 +234,6 @@ struct osi_l2_da_filter {
nveu32_t perfect_inverse_match; nveu32_t perfect_inverse_match;
}; };
#ifndef OSI_STRIPPED_LIB
/** /**
* @brief OSI Core avb data structure per queue. * @brief OSI Core avb data structure per queue.
*/ */

47
include/osi_dma.h
View File

@@ -25,7 +25,24 @@
#include "osi_common.h" #include "osi_common.h"
#include "osi_dma_txrx.h" #include "osi_dma_txrx.h"
#include "mmc.h"
/**
* @addtogroup Helper Helper MACROS
*
* @brief EQOS generic helper MACROS.
* @{
*/
#define OSI_NET_IP_ALIGN 0x2U
#define NV_VLAN_HLEN 0x4U
#define OSI_ETH_HLEN 0xEU
#define OSI_INVALID_VALUE 0xFFFFFFFFU
#define OSI_ONE_MEGA_HZ 1000000U
/* Compiler hints for branch prediction */
#define osi_likely(x) __builtin_expect(!!(x), 1)
/** @} */
/* to avoid re definition when both core and dma headers are included */ /* to avoid re definition when both core and dma headers are included */
#undef OSI_ERR #undef OSI_ERR
@@ -93,8 +110,10 @@
* @brief These flags are used for DMA channel Slot context configuration * @brief These flags are used for DMA channel Slot context configuration
* @{ * @{
*/ */
#ifndef OSI_STRIPPED_LIB
#define OSI_SLOT_INTVL_DEFAULT 125U #define OSI_SLOT_INTVL_DEFAULT 125U
#define OSI_SLOT_INTVL_MAX 4095U #define OSI_SLOT_INTVL_MAX 4095U
#endif /* !OSI_STRIPPED_LIB */
#define OSI_SLOT_NUM_MAX 16U #define OSI_SLOT_NUM_MAX 16U
/** @} */ /** @} */
@@ -121,14 +140,18 @@
* *
* @brief Flag to indicate the result from checksum offload engine * @brief Flag to indicate the result from checksum offload engine
* to SW network stack in receive path. * to SW network stack in receive path.
#ifndef OSI_STRIPPED_LIB
* OSI_CHECKSUM_NONE indicates that HW checksum offload * OSI_CHECKSUM_NONE indicates that HW checksum offload
* engine did not verify the checksum, SW network stack has to do it. * engine did not verify the checksum, SW network stack has to do it.
#endif
* OSI_CHECKSUM_UNNECESSARY indicates that HW validated the * OSI_CHECKSUM_UNNECESSARY indicates that HW validated the
* checksum already, network stack can skip validation. * checksum already, network stack can skip validation.
* @{ * @{
*/ */
/* Checksum offload result flags */ /* Checksum offload result flags */
#ifndef OSI_STRIPPED_LIB
#define OSI_CHECKSUM_NONE 0x0U #define OSI_CHECKSUM_NONE 0x0U
#endif /* OSI_STRIPPED_LIB */
/* TCP header/payload */ /* TCP header/payload */
#define OSI_CHECKSUM_TCPv4 OSI_BIT(0) #define OSI_CHECKSUM_TCPv4 OSI_BIT(0)
/* UDP header/payload */ /* UDP header/payload */
@@ -349,6 +372,28 @@ struct osi_tx_ring {
nveu32_t frame_cnt; nveu32_t frame_cnt;
}; };
/**
* @brief osi_xtra_dma_stat_counters - OSI DMA extra stats counters
*/
struct osi_xtra_dma_stat_counters {
/** Per Q TX packet count */
nveu64_t q_tx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Per Q RX packet count */
nveu64_t q_rx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Per Q TX complete call count */
nveu64_t tx_clean_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Total number of tx packets count */
nveu64_t tx_pkt_n;
/** Total number of rx packet count */
nveu64_t rx_pkt_n;
/** Total number of VLAN RX packet count */
nveu64_t rx_vlan_pkt_n;
/** Total number of VLAN TX packet count */
nveu64_t tx_vlan_pkt_n;
/** Total number of TSO packet count */
nveu64_t tx_tso_pkt_n;
};
struct osi_dma_priv_data; struct osi_dma_priv_data;
/** /**

6
include/osi_dma_txrx.h
View File

@@ -44,12 +44,14 @@
*/ */
/** Increment the tx descriptor index */ /** Increment the tx descriptor index */
#define INCR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (TX_DESC_CNT - 1U)) #define INCR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (TX_DESC_CNT - 1U))
/** Decrement the tx descriptor index */
#define DECR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (TX_DESC_CNT - 1U))
/** Increment the rx descriptor index */ /** Increment the rx descriptor index */
#define INCR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (RX_DESC_CNT - 1U)) #define INCR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (RX_DESC_CNT - 1U))
#ifndef OSI_STRIPPED_LIB
/** Decrement the tx descriptor index */
#define DECR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (TX_DESC_CNT - 1U))
/** Decrement the rx descriptor index */ /** Decrement the rx descriptor index */
#define DECR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (RX_DESC_CNT - 1U)) #define DECR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (RX_DESC_CNT - 1U))
#endif /* !OSI_STRIPPED_LIB */
/** @} */ /** @} */
/** /**

26
osi/common/include/local_common.h
View File

@@ -26,6 +26,32 @@
#include <osi_common.h> #include <osi_common.h>
#include "../osi/common/type.h" #include "../osi/common/type.h"
/**
*@brief div_u64_rem - updates remainder and returns Quotient
*
* @note
* Algorithm:
* - Dividend will be divided by divisor and stores the
* remainder value and returns quotient
*
* @param[in] dividend: Dividend value
* @param[in] divisor: Divisor value
* @param[out] remain: Remainder
*
* @pre MAC IP should be out of reset and need to be initialized as the
* requirements
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval Quotient
*/
nveu64_t div_u64_rem(nveu64_t dividend, nveu64_t divisor,
nveu64_t *remain);
/** /**
* @brief common_get_systime_from_mac - Get system time * @brief common_get_systime_from_mac - Get system time
* *

51
osi/common/osi_common.c
View File

@@ -22,6 +22,7 @@
#include <osd.h> #include <osd.h>
#include "eqos_common.h" #include "eqos_common.h"
#include "local_common.h"
void common_get_hw_features(void *base, struct osi_hw_features *hw_feat) void common_get_hw_features(void *base, struct osi_hw_features *hw_feat)
{ {
@@ -141,42 +142,7 @@ void osi_memset(void *s, nveu32_t c, nveu64_t count)
} }
} }
/**
*@brief div_u64_rem - updates remainder and returns Quotient
*
* @note
* Algorithm:
* - Dividend will be divided by divisor and stores the
* remainder value and returns quotient
*
* @param[in] dividend: Dividend value
* @param[in] divisor: Divisor value
* @param[out] remain: Remainder
*
* @pre MAC IP should be out of reset and need to be initialized as the
* requirements
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval Quotient
*/
static inline nveu64_t div_u64_rem(nveu64_t dividend, nveu64_t divisor,
nveu64_t *remain)
{
nveu64_t ret = 0;
if (divisor != 0U) {
*remain = dividend % divisor;
ret = dividend / divisor;
} else {
ret = 0;
}
return ret;
}
void common_get_systime_from_mac(void *addr, nveu32_t mac, nveu32_t *sec, void common_get_systime_from_mac(void *addr, nveu32_t mac, nveu32_t *sec,
nveu32_t *nsec) nveu32_t *nsec)
@@ -214,3 +180,18 @@ nveu32_t common_is_mac_enabled(void *addr, nveu32_t mac)
return OSI_DISABLE; return OSI_DISABLE;
} }
} }
nveu64_t div_u64_rem(nveu64_t dividend, nveu64_t divisor,
nveu64_t *remain)
{
nveu64_t ret = 0;
if (divisor != 0U) {
*remain = dividend % divisor;
ret = dividend / divisor;
} else {
ret = 0;
}
return ret;
}

4
osi/common/type.h
View File

@@ -30,9 +30,7 @@ typedef unsigned int my_uint32_t;
typedef int my_int32_t; typedef int my_int32_t;
typedef char my_int8_t; typedef char my_int8_t;
typedef unsigned char my_uint8_t; typedef unsigned char my_uint8_t;
typedef unsigned short my_uint16_t;
typedef unsigned long long my_ulint_64; typedef unsigned long long my_ulint_64;
typedef long long my_lint_64;
typedef unsigned long my_uint64_t; typedef unsigned long my_uint64_t;
/* Actual type used in code */ /* Actual type used in code */
@@ -40,8 +38,6 @@ typedef my_uint32_t nveu32_t;
typedef my_int32_t nve32_t; typedef my_int32_t nve32_t;
typedef my_int8_t nve8_t; typedef my_int8_t nve8_t;
typedef my_uint8_t nveu8_t; typedef my_uint8_t nveu8_t;
typedef my_uint16_t nveu16_t;
typedef my_ulint_64 nveul64_t; typedef my_ulint_64 nveul64_t;
typedef my_lint_64 nvel64_t;
typedef my_uint64_t nveu64_t; typedef my_uint64_t nveu64_t;
#endif #endif

107
osi/core/eqos_core.c
View File

@@ -1310,7 +1310,7 @@ static void eqos_configure_mac(struct osi_core_priv_data *const osi_core)
osi_writel(value, (nveu8_t *)osi_core->base + EQOS_MAC_VLANTIR); osi_writel(value, (nveu8_t *)osi_core->base + EQOS_MAC_VLANTIR);
/* Configure default flow control settings */ /* Configure default flow control settings */
if (osi_core->pause_frames == OSI_PAUSE_FRAMES_ENABLE) { if (osi_core->pause_frames != OSI_PAUSE_FRAMES_DISABLE) {
osi_core->flow_ctrl = (OSI_FLOW_CTRL_TX | OSI_FLOW_CTRL_RX); osi_core->flow_ctrl = (OSI_FLOW_CTRL_TX | OSI_FLOW_CTRL_RX);
if (eqos_config_flow_control(osi_core, osi_core->flow_ctrl) != if (eqos_config_flow_control(osi_core, osi_core->flow_ctrl) !=
0) { 0) {
@@ -1916,7 +1916,8 @@ static inline nve32_t eqos_update_mac_addr_helper(
(osi_core->dcs_en == OSI_ENABLE)) { (osi_core->dcs_en == OSI_ENABLE)) {
*value = ((dma_chan << EQOS_MAC_ADDRH_DCS_SHIFT) & *value = ((dma_chan << EQOS_MAC_ADDRH_DCS_SHIFT) &
EQOS_MAC_ADDRH_DCS); EQOS_MAC_ADDRH_DCS);
} else if (dma_chan > (OSI_EQOS_MAX_NUM_CHANS - 0x1U)) { } else if ((dma_chan == OSI_CHAN_ANY) ||
(dma_chan > (OSI_EQOS_MAX_NUM_CHANS - 0x1U))) {
OSI_ERR(osi_core->osd, OSI_LOG_ARG_OUTOFBOUND, OSI_ERR(osi_core->osd, OSI_LOG_ARG_OUTOFBOUND,
"invalid dma channel\n", "invalid dma channel\n",
(nveul64_t)dma_chan); (nveul64_t)dma_chan);
@@ -1928,7 +1929,8 @@ static inline nve32_t eqos_update_mac_addr_helper(
} }
/* Address mask is valid for address 1 to 31 index only */ /* Address mask is valid for address 1 to 31 index only */
if ((addr_mask <= EQOS_MAX_MASK_BYTE) && (addr_mask > 0U)) { if ((addr_mask <= EQOS_MAX_MASK_BYTE) &&
(addr_mask > OSI_AMASK_DISABLE)) {
if ((idx > 0U) && (idx < EQOS_MAX_MAC_ADDR_REG)) { if ((idx > 0U) && (idx < EQOS_MAX_MAC_ADDR_REG)) {
*value = (*value | *value = (*value |
((addr_mask << EQOS_MAC_ADDRH_MBC_SHIFT) & ((addr_mask << EQOS_MAC_ADDRH_MBC_SHIFT) &
@@ -4251,56 +4253,6 @@ static nve32_t eqos_config_mac_loopback(void *addr,
} }
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
/**
* @brief eqos_core_ops - EQOS MAC core operations
*/
static struct osi_core_ops eqos_core_ops = {
.poll_for_swr = eqos_poll_for_swr,
.core_init = eqos_core_init,
.core_deinit = eqos_core_deinit,
.start_mac = eqos_start_mac,
.stop_mac = eqos_stop_mac,
.handle_common_intr = eqos_handle_common_intr,
.set_mode = eqos_set_mode,
.set_speed = eqos_set_speed,
.pad_calibrate = eqos_pad_calibrate,
.config_fw_err_pkts = eqos_config_fw_err_pkts,
.config_rxcsum_offload = eqos_config_rxcsum_offload,
.config_mac_pkt_filter_reg = eqos_config_mac_pkt_filter_reg,
.update_mac_addr_low_high_reg = eqos_update_mac_addr_low_high_reg,
.config_l3_l4_filter_enable = eqos_config_l3_l4_filter_enable,
.config_l3_filters = eqos_config_l3_filters,
.update_ip4_addr = eqos_update_ip4_addr,
.update_ip6_addr = eqos_update_ip6_addr,
.config_l4_filters = eqos_config_l4_filters,
.update_l4_port_no = eqos_update_l4_port_no,
.set_systime_to_mac = eqos_set_systime_to_mac,
.config_addend = eqos_config_addend,
.adjust_mactime = eqos_adjust_mactime,
.config_tscr = eqos_config_tscr,
.config_ssir = eqos_config_ssir,
.read_mmc = eqos_read_mmc,
.write_phy_reg = eqos_write_phy_reg,
.read_phy_reg = eqos_read_phy_reg,
#ifndef OSI_STRIPPED_LIB
.config_tx_status = eqos_config_tx_status,
.config_rx_crc_check = eqos_config_rx_crc_check,
.config_flow_control = eqos_config_flow_control,
.config_arp_offload = eqos_config_arp_offload,
.validate_regs = eqos_validate_core_regs,
.flush_mtl_tx_queue = eqos_flush_mtl_tx_queue,
.set_avb_algorithm = eqos_set_avb_algorithm,
.get_avb_algorithm = eqos_get_avb_algorithm,
.config_vlan_filtering = eqos_config_vlan_filtering,
.update_vlan_id = eqos_update_vlan_id,
.reset_mmc = eqos_reset_mmc,
.configure_eee = eqos_configure_eee,
.save_registers = eqos_save_registers,
.restore_registers = eqos_restore_registers,
.set_mdc_clk_rate = eqos_set_mdc_clk_rate,
.config_mac_loopback = eqos_config_mac_loopback,
#endif /* !OSI_STRIPPED_LIB */
};
/** /**
* @brief eqos_get_core_safety_config - EQOS MAC safety configuration * @brief eqos_get_core_safety_config - EQOS MAC safety configuration
@@ -4327,5 +4279,54 @@ void *eqos_get_core_safety_config(void)
*/ */
struct osi_core_ops *eqos_get_hw_core_ops(void) struct osi_core_ops *eqos_get_hw_core_ops(void)
{ {
static struct osi_core_ops eqos_core_ops = {
.poll_for_swr = eqos_poll_for_swr,
.core_init = eqos_core_init,
.core_deinit = eqos_core_deinit,
.start_mac = eqos_start_mac,
.stop_mac = eqos_stop_mac,
.handle_common_intr = eqos_handle_common_intr,
.set_mode = eqos_set_mode,
.set_speed = eqos_set_speed,
.pad_calibrate = eqos_pad_calibrate,
.config_fw_err_pkts = eqos_config_fw_err_pkts,
.config_rxcsum_offload = eqos_config_rxcsum_offload,
.config_mac_pkt_filter_reg = eqos_config_mac_pkt_filter_reg,
.update_mac_addr_low_high_reg =
eqos_update_mac_addr_low_high_reg,
.config_l3_l4_filter_enable = eqos_config_l3_l4_filter_enable,
.config_l3_filters = eqos_config_l3_filters,
.update_ip4_addr = eqos_update_ip4_addr,
.update_ip6_addr = eqos_update_ip6_addr,
.config_l4_filters = eqos_config_l4_filters,
.update_l4_port_no = eqos_update_l4_port_no,
.set_systime_to_mac = eqos_set_systime_to_mac,
.config_addend = eqos_config_addend,
.adjust_mactime = eqos_adjust_mactime,
.config_tscr = eqos_config_tscr,
.config_ssir = eqos_config_ssir,
.read_mmc = eqos_read_mmc,
.write_phy_reg = eqos_write_phy_reg,
.read_phy_reg = eqos_read_phy_reg,
#ifndef OSI_STRIPPED_LIB
.config_tx_status = eqos_config_tx_status,
.config_rx_crc_check = eqos_config_rx_crc_check,
.config_flow_control = eqos_config_flow_control,
.config_arp_offload = eqos_config_arp_offload,
.validate_regs = eqos_validate_core_regs,
.flush_mtl_tx_queue = eqos_flush_mtl_tx_queue,
.set_avb_algorithm = eqos_set_avb_algorithm,
.get_avb_algorithm = eqos_get_avb_algorithm,
.config_vlan_filtering = eqos_config_vlan_filtering,
.update_vlan_id = eqos_update_vlan_id,
.reset_mmc = eqos_reset_mmc,
.configure_eee = eqos_configure_eee,
.save_registers = eqos_save_registers,
.restore_registers = eqos_restore_registers,
.set_mdc_clk_rate = eqos_set_mdc_clk_rate,
.config_mac_loopback = eqos_config_mac_loopback,
#endif /* !OSI_STRIPPED_LIB */
};
return &eqos_core_ops; return &eqos_core_ops;
} }

99
osi/core/eqos_core.h
View File

@@ -40,6 +40,7 @@
#define FULL_MINUS_16_K (nveu32_t)30 #define FULL_MINUS_16_K (nveu32_t)30
/** @} */ /** @} */
#ifndef OSI_STRIPPED_LIB
/** /**
* @addtogroup EQOS-MDC MDC Clock Selection defines * @addtogroup EQOS-MDC MDC Clock Selection defines
* *
@@ -55,7 +56,7 @@
#define EQOS_CSR_300_500M 0x6 /* MDC = clk_csr/204 */ #define EQOS_CSR_300_500M 0x6 /* MDC = clk_csr/204 */
#define EQOS_CSR_500_800M 0x7 /* MDC = clk_csr/324 */ #define EQOS_CSR_500_800M 0x7 /* MDC = clk_csr/324 */
/** @} */ /** @} */
#endif /* !OSI_STRIPPED_LIB */
/** /**
* @addtogroup EQOS-SIZE SIZE calculation helper Macros * @addtogroup EQOS-SIZE SIZE calculation helper Macros
* *
@@ -107,7 +108,9 @@
#define EQOS_MAC_LPI_CSR 0x00D0 #define EQOS_MAC_LPI_CSR 0x00D0
#define EQOS_MAC_LPI_TIMER_CTRL 0x00D4 #define EQOS_MAC_LPI_TIMER_CTRL 0x00D4
#define EQOS_MAC_LPI_EN_TIMER 0x00D8 #define EQOS_MAC_LPI_EN_TIMER 0x00D8
#ifndef OSI_STRIPPED_LIB
#define EQOS_MAC_1US_TIC_CNTR 0x00DC #define EQOS_MAC_1US_TIC_CNTR 0x00DC
#endif /* !OSI_STRIPPED_LIB */
#define EQOS_MAC_ANS 0x00E4 #define EQOS_MAC_ANS 0x00E4
#define EQOS_MAC_PCS 0x00F8 #define EQOS_MAC_PCS 0x00F8
#define EQOS_MAC_MDIO_ADDRESS 0x0200 #define EQOS_MAC_MDIO_ADDRESS 0x0200
@@ -184,7 +187,6 @@
#define EQOS_PAD_AUTO_CAL_CFG_START OSI_BIT(31) #define EQOS_PAD_AUTO_CAL_CFG_START OSI_BIT(31)
#define EQOS_PAD_AUTO_CAL_STAT_ACTIVE OSI_BIT(31) #define EQOS_PAD_AUTO_CAL_STAT_ACTIVE OSI_BIT(31)
#define EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD OSI_BIT(31) #define EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD OSI_BIT(31)
#define EQOS_MCR_ARPEN OSI_BIT(31)
#define EQOS_MCR_IPC OSI_BIT(27) #define EQOS_MCR_IPC OSI_BIT(27)
#define EQOS_MMC_CNTRL_CNTRST OSI_BIT(0) #define EQOS_MMC_CNTRL_CNTRST OSI_BIT(0)
#define EQOS_MMC_CNTRL_RSTONRD OSI_BIT(2) #define EQOS_MMC_CNTRL_RSTONRD OSI_BIT(2)
@@ -207,10 +209,6 @@
#define EQOS_MCR_CST OSI_BIT(21) #define EQOS_MCR_CST OSI_BIT(21)
#define EQOS_MCR_GPSLCE OSI_BIT(23) #define EQOS_MCR_GPSLCE OSI_BIT(23)
#define EQOS_IMR_RGSMIIIE OSI_BIT(0) #define EQOS_IMR_RGSMIIIE OSI_BIT(0)
#define EQOS_IMR_PCSLCHGIE OSI_BIT(1)
#define EQOS_IMR_PCSANCIE OSI_BIT(2)
#define EQOS_IMR_PMTIE OSI_BIT(4)
#define EQOS_IMR_LPIIE OSI_BIT(5)
#define EQOS_MAC_PCS_LNKSTS OSI_BIT(19) #define EQOS_MAC_PCS_LNKSTS OSI_BIT(19)
#define EQOS_MAC_PCS_LNKMOD OSI_BIT(16) #define EQOS_MAC_PCS_LNKMOD OSI_BIT(16)
#define EQOS_MAC_PCS_LNKSPEED (OSI_BIT(17) | OSI_BIT(18)) #define EQOS_MAC_PCS_LNKSPEED (OSI_BIT(17) | OSI_BIT(18))
@@ -222,9 +220,7 @@
#define EQOS_MAC_VLANTR_EVLRXS OSI_BIT(24) #define EQOS_MAC_VLANTR_EVLRXS OSI_BIT(24)
#define EQOS_MAC_VLANTR_DOVLTC OSI_BIT(20) #define EQOS_MAC_VLANTR_DOVLTC OSI_BIT(20)
#define EQOS_MAC_VLANTR_ERIVLT OSI_BIT(27) #define EQOS_MAC_VLANTR_ERIVLT OSI_BIT(27)
#define EQOS_MAC_VLANTIRR_VLTI OSI_BIT(20)
#define EQOS_MAC_VLANTIRR_CSVL OSI_BIT(19) #define EQOS_MAC_VLANTIRR_CSVL OSI_BIT(19)
#define EQOS_DMA_SBUS_BLEN4 OSI_BIT(1)
#define EQOS_DMA_SBUS_BLEN8 OSI_BIT(2) #define EQOS_DMA_SBUS_BLEN8 OSI_BIT(2)
#define EQOS_DMA_SBUS_BLEN16 OSI_BIT(3) #define EQOS_DMA_SBUS_BLEN16 OSI_BIT(3)
#define EQOS_DMA_SBUS_EAME OSI_BIT(11) #define EQOS_DMA_SBUS_EAME OSI_BIT(11)
@@ -235,33 +231,63 @@
#define EQOS_MTL_QTOMR_FTQ_LPOS OSI_BIT(0) #define EQOS_MTL_QTOMR_FTQ_LPOS OSI_BIT(0)
#define EQOS_DMA_ISR_MACIS OSI_BIT(17) #define EQOS_DMA_ISR_MACIS OSI_BIT(17)
#define EQOS_MAC_ISR_RGSMIIS OSI_BIT(0) #define EQOS_MAC_ISR_RGSMIIS OSI_BIT(0)
#define EQOS_MAC_ISR_LPIIS OSI_BIT(5)
#define EQOS_MAC_LPI_CSR_LPITE OSI_BIT(20)
#define EQOS_MAC_LPI_CSR_LPITXA OSI_BIT(19)
#define EQOS_MAC_LPI_CSR_PLS OSI_BIT(17)
#define EQOS_MAC_LPI_CSR_LPIEN OSI_BIT(16)
#define EQOS_MTL_TXQ_QW_ISCQW OSI_BIT(4) #define EQOS_MTL_TXQ_QW_ISCQW OSI_BIT(4)
#define EQOS_DMA_SBUS_RD_OSR_LMT 0x001F0000U #define EQOS_DMA_SBUS_RD_OSR_LMT 0x001F0000U
#define EQOS_DMA_SBUS_WR_OSR_LMT 0x1F000000U #define EQOS_DMA_SBUS_WR_OSR_LMT 0x1F000000U
#define EQOS_MTL_TXQ_SIZE_SHIFT 16U #define EQOS_MTL_TXQ_SIZE_SHIFT 16U
#define EQOS_MTL_RXQ_SIZE_SHIFT 20U #define EQOS_MTL_RXQ_SIZE_SHIFT 20U
#ifndef OSI_STRIPPED_LIB
#define EQOS_MAC_ENABLE_LM OSI_BIT(12) #define EQOS_MAC_ENABLE_LM OSI_BIT(12)
#define EQOS_MAC_VLANTIRR_VLTI OSI_BIT(20)
#define EQOS_DMA_SBUS_BLEN4 OSI_BIT(1)
#define EQOS_IMR_LPIIE OSI_BIT(5)
#define EQOS_IMR_PCSLCHGIE OSI_BIT(1)
#define EQOS_IMR_PCSANCIE OSI_BIT(2)
#define EQOS_IMR_PMTIE OSI_BIT(4)
#define EQOS_MAC_ISR_LPIIS OSI_BIT(5)
#define EQOS_MAC_LPI_CSR_LPITE OSI_BIT(20)
#define EQOS_MAC_LPI_CSR_LPITXA OSI_BIT(19)
#define EQOS_MAC_LPI_CSR_PLS OSI_BIT(17)
#define EQOS_MAC_LPI_CSR_LPIEN OSI_BIT(16)
#define EQOS_MCR_ARPEN OSI_BIT(31)
#define EQOS_RX_CLK_SEL OSI_BIT(8) #define EQOS_RX_CLK_SEL OSI_BIT(8)
#define EQOS_MTL_TXQ_ETS_SSCR_SSC_MASK 0x00003FFFU
#define EQOS_MTL_TXQ_ETS_QW_ISCQW_MASK 0x000FFFFFU
#define EQOS_MTL_TXQ_ETS_HCR_HC_MASK 0x1FFFFFFFU
#define EQOS_MTL_TXQ_ETS_LCR_LC_MASK 0x1FFFFFFFU
#define EQOS_MTL_TXQ_ETS_CR_SLC_MASK (OSI_BIT(6) | OSI_BIT(5) | \ #define EQOS_MTL_TXQ_ETS_CR_SLC_MASK (OSI_BIT(6) | OSI_BIT(5) | \
OSI_BIT(4)) OSI_BIT(4))
#define EQOS_MTL_TXQ_ETS_CR_CC OSI_BIT(3) #define EQOS_MTL_TXQ_ETS_CR_CC OSI_BIT(3)
#define EQOS_MTL_TXQ_ETS_CR_AVALG OSI_BIT(2) #define EQOS_MTL_TXQ_ETS_CR_AVALG OSI_BIT(2)
#define EQOS_MTL_TXQ_ETS_CR_CC_SHIFT 3U #define EQOS_MTL_TXQ_ETS_CR_CC_SHIFT 3U
#define EQOS_MTL_TXQ_ETS_CR_AVALG_SHIFT 2U #define EQOS_MTL_TXQ_ETS_CR_AVALG_SHIFT 2U
#define EQOS_MTL_TXQ_ETS_QW_ISCQW_MASK 0x000FFFFFU
#define EQOS_MTL_TXQ_ETS_SSCR_SSC_MASK 0x00003FFFU
#define EQOS_MTL_TXQ_ETS_HCR_HC_MASK 0x1FFFFFFFU
#define EQOS_MTL_TXQ_ETS_LCR_LC_MASK 0x1FFFFFFFU
#define EQOS_MTL_TXQEN_MASK (OSI_BIT(3) | OSI_BIT(2)) #define EQOS_MTL_TXQEN_MASK (OSI_BIT(3) | OSI_BIT(2))
#define EQOS_MTL_TXQEN_MASK_SHIFT 2U #define EQOS_MTL_TXQEN_MASK_SHIFT 2U
#define EQOS_MTL_RXQ_OP_MODE_FEP OSI_BIT(4)
#define EQOS_MTL_OP_MODE_DTXSTS OSI_BIT(1) #define EQOS_MTL_OP_MODE_DTXSTS OSI_BIT(1)
#define EQOS_MAC_VLAN_TR 0x0050U
#define EQOS_MAC_VLAN_TFR 0x0054U
#define EQOS_MAC_VLAN_HTR 0x0058U
#define EQOS_MAC_VLAN_TR_ETV OSI_BIT(16)
#define EQOS_MAC_VLAN_TR_VTIM OSI_BIT(17)
#define EQOS_MAC_VLAN_TR_VTIM_SHIFT 17
#define EQOS_MAC_VLAN_TR_VTHM OSI_BIT(25)
#define EQOS_MAC_VLAN_TR_VL 0xFFFFU
#define EQOS_MAC_VLAN_HTR_VLHT 0xFFFFU
#define EQOS_MAC_STNSR_TSSS_MASK 0x7FFFFFFFU
#define EQOS_MAC_VLAN_TR_ETV_SHIFT 16U
#define EQOS_MAC_PFR_HUC OSI_BIT(1)
#define EQOS_MAC_PFR_HMC OSI_BIT(2)
#define EQOS_MAC_MAX_HTR_REG_LEN 8U
#define EQOS_MAC_L3L4_CTR_L3HSBM0 (OSI_BIT(6) | OSI_BIT(7) | \
OSI_BIT(8) | OSI_BIT(9) | \
OSI_BIT(10))
#define EQOS_MAC_L3L4_CTR_L3HDBM0 (OSI_BIT(11) | OSI_BIT(12) | \
OSI_BIT(13) | OSI_BIT(14) | \
OSI_BIT(15))
#define EQOS_MAC_PFR_SHIFT 16
#define EQOS_MAC_EXTR_DCRCC OSI_BIT(16) #define EQOS_MAC_EXTR_DCRCC OSI_BIT(16)
#endif /* !OSI_STRIPPED_LIB */
#define EQOS_MTL_RXQ_OP_MODE_FEP OSI_BIT(4)
#define EQOS_MAC_QX_TX_FLW_CTRL_TFE OSI_BIT(1) #define EQOS_MAC_QX_TX_FLW_CTRL_TFE OSI_BIT(1)
#define EQOS_MAC_RX_FLW_CTRL_RFE OSI_BIT(0) #define EQOS_MAC_RX_FLW_CTRL_RFE OSI_BIT(0)
#define EQOS_MAC_PAUSE_TIME 0xFFFF0000U #define EQOS_MAC_PAUSE_TIME 0xFFFF0000U
@@ -272,8 +298,6 @@
#define EQOS_MTL_RXQ_OP_MODE_RFD_SHIFT 14U #define EQOS_MTL_RXQ_OP_MODE_RFD_SHIFT 14U
#define EQOS_MTL_RXQ_OP_MODE_RFD_MASK 0x000FC000U #define EQOS_MTL_RXQ_OP_MODE_RFD_MASK 0x000FC000U
#define EQOS_MAC_PFR_PR OSI_BIT(0) #define EQOS_MAC_PFR_PR OSI_BIT(0)
#define EQOS_MAC_PFR_HUC OSI_BIT(1)
#define EQOS_MAC_PFR_HMC OSI_BIT(2)
#define EQOS_MAC_PFR_DAIF OSI_BIT(3) #define EQOS_MAC_PFR_DAIF OSI_BIT(3)
#define EQOS_MAC_PFR_PM OSI_BIT(4) #define EQOS_MAC_PFR_PM OSI_BIT(4)
#define EQOS_MAC_PFR_DBF OSI_BIT(5) #define EQOS_MAC_PFR_DBF OSI_BIT(5)
@@ -282,7 +306,6 @@
#define EQOS_MAC_PFR_SAF OSI_BIT(9) #define EQOS_MAC_PFR_SAF OSI_BIT(9)
#define EQOS_MAC_PFR_HPF OSI_BIT(10) #define EQOS_MAC_PFR_HPF OSI_BIT(10)
#define EQOS_MAC_PFR_VTFE OSI_BIT(16) #define EQOS_MAC_PFR_VTFE OSI_BIT(16)
#define EQOS_MAC_PFR_SHIFT 16
#define EQOS_MAC_PFR_IPFE OSI_BIT(20) #define EQOS_MAC_PFR_IPFE OSI_BIT(20)
#define EQOS_MAC_PFR_DNTU OSI_BIT(21) #define EQOS_MAC_PFR_DNTU OSI_BIT(21)
#define EQOS_MAC_PFR_RA OSI_BIT(31) #define EQOS_MAC_PFR_RA OSI_BIT(31)
@@ -303,12 +326,6 @@
#define EQOS_MAC_L3L4_CTR_L3DAM0 OSI_BIT(4) #define EQOS_MAC_L3L4_CTR_L3DAM0 OSI_BIT(4)
#define EQOS_MAC_L3L4_CTR_L3DAIM0 OSI_BIT(5) #define EQOS_MAC_L3L4_CTR_L3DAIM0 OSI_BIT(5)
#define EQOS_MAC_L3L4_CTR_L3DAI_SHIFT 5 #define EQOS_MAC_L3L4_CTR_L3DAI_SHIFT 5
#define EQOS_MAC_L3L4_CTR_L3HSBM0 (OSI_BIT(6) | OSI_BIT(7) | \
OSI_BIT(8) | OSI_BIT(9) | \
OSI_BIT(10))
#define EQOS_MAC_L3L4_CTR_L3HDBM0 (OSI_BIT(11) | OSI_BIT(12) | \
OSI_BIT(13) | OSI_BIT(14) | \
OSI_BIT(15))
#define EQOS_MAC_L3L4_CTR_DMCHEN0 OSI_BIT(28) #define EQOS_MAC_L3L4_CTR_DMCHEN0 OSI_BIT(28)
#define EQOS_MAC_L3L4_CTR_DMCHEN0_SHIFT 28 #define EQOS_MAC_L3L4_CTR_DMCHEN0_SHIFT 28
#define EQOS_MAC_L3L4_CTR_DMCHN0 (OSI_BIT(24) | OSI_BIT(25) | \ #define EQOS_MAC_L3L4_CTR_DMCHN0 (OSI_BIT(24) | OSI_BIT(25) | \
@@ -355,19 +372,8 @@
#define EQOS_MAC_ADDRH_SA OSI_BIT(30) #define EQOS_MAC_ADDRH_SA OSI_BIT(30)
#define EQOS_MAC_ADDRH_SA_SHIFT 30 #define EQOS_MAC_ADDRH_SA_SHIFT 30
#define EQOS_MAC_ADDRH_AE OSI_BIT(31) #define EQOS_MAC_ADDRH_AE OSI_BIT(31)
#define EQOS_MAC_VLAN_TR 0x0050U
#define EQOS_MAC_VLAN_TFR 0x0054U
#define EQOS_MAC_VLAN_HTR 0x0058U
#define EQOS_MAC_VLAN_TR_ETV OSI_BIT(16)
#define EQOS_MAC_VLAN_TR_VTIM OSI_BIT(17)
#define EQOS_MAC_VLAN_TR_VTIM_SHIFT 17
#define EQOS_MAC_VLAN_TR_VTHM OSI_BIT(25)
#define EQOS_MAC_VLAN_TR_VL 0xFFFFU
#define EQOS_MAC_VLAN_HTR_VLHT 0xFFFFU
#define EQOS_MAC_RQC2_PSRQ_MASK ((nveu32_t)0xFF) #define EQOS_MAC_RQC2_PSRQ_MASK ((nveu32_t)0xFF)
#define EQOS_MAC_RQC2_PSRQ_SHIFT 8U #define EQOS_MAC_RQC2_PSRQ_SHIFT 8U
#define EQOS_MAC_VLAN_TR_ETV_SHIFT 16U
#define EQOS_MAC_MAX_HTR_REG_LEN 8U
#define EQOS_MAC_TCR_TSADDREG OSI_BIT(5) #define EQOS_MAC_TCR_TSADDREG OSI_BIT(5)
#define EQOS_MAC_TCR_TSINIT OSI_BIT(2) #define EQOS_MAC_TCR_TSINIT OSI_BIT(2)
#define EQOS_MAC_TCR_TSUPDT OSI_BIT(3) #define EQOS_MAC_TCR_TSUPDT OSI_BIT(3)
@@ -375,7 +381,6 @@
#define EQOS_MAC_TCR_TSCFUPDT OSI_BIT(1) #define EQOS_MAC_TCR_TSCFUPDT OSI_BIT(1)
#define EQOS_MAC_TCR_TSCTRLSSR OSI_BIT(9) #define EQOS_MAC_TCR_TSCTRLSSR OSI_BIT(9)
#define EQOS_MAC_SSIR_SSINC_SHIFT 16U #define EQOS_MAC_SSIR_SSINC_SHIFT 16U
#define EQOS_MAC_STNSR_TSSS_MASK 0x7FFFFFFFU
#define EQOS_MAC_GMIIDR_GD_WR_MASK 0xFFFF0000U #define EQOS_MAC_GMIIDR_GD_WR_MASK 0xFFFF0000U
#define EQOS_MAC_GMIIDR_GD_MASK 0xFFFFU #define EQOS_MAC_GMIIDR_GD_MASK 0xFFFFU
#define EQOS_MDIO_PHY_ADDR_SHIFT 21U #define EQOS_MDIO_PHY_ADDR_SHIFT 21U
@@ -452,9 +457,6 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value);
#define EQOS_MAC_MCR_IDX 0U #define EQOS_MAC_MCR_IDX 0U
#define EQOS_MAC_PFR_IDX 1U #define EQOS_MAC_PFR_IDX 1U
#define EQOS_MAC_HTR0_IDX 2U #define EQOS_MAC_HTR0_IDX 2U
#define EQOS_MAC_HTR1_IDX 3U
#define EQOS_MAC_HTR2_IDX 4U
#define EQOS_MAC_HTR3_IDX 5U
#define EQOS_MAC_Q0_TXFC_IDX 6U #define EQOS_MAC_Q0_TXFC_IDX 6U
#define EQOS_MAC_RQC0R_IDX 7U #define EQOS_MAC_RQC0R_IDX 7U
#define EQOS_MAC_RQC1R_IDX 8U #define EQOS_MAC_RQC1R_IDX 8U
@@ -468,17 +470,22 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value);
#define EQOS_PAD_AUTO_CAL_CFG_IDX 16U #define EQOS_PAD_AUTO_CAL_CFG_IDX 16U
#define EQOS_MTL_RXQ_DMA_MAP0_IDX 17U #define EQOS_MTL_RXQ_DMA_MAP0_IDX 17U
#define EQOS_MTL_CH0_TX_OP_MODE_IDX 18U #define EQOS_MTL_CH0_TX_OP_MODE_IDX 18U
#define EQOS_MTL_TXQ0_QW_IDX 22U
#ifndef OSI_STRIPPED_LIB
#define EQOS_MAC_HTR1_IDX 3U
#define EQOS_MAC_HTR2_IDX 4U
#define EQOS_MAC_HTR3_IDX 5U
#define EQOS_MTL_CH1_TX_OP_MODE_IDX 19U #define EQOS_MTL_CH1_TX_OP_MODE_IDX 19U
#define EQOS_MTL_CH2_TX_OP_MODE_IDX 20U #define EQOS_MTL_CH2_TX_OP_MODE_IDX 20U
#define EQOS_MTL_CH3_TX_OP_MODE_IDX 21U #define EQOS_MTL_CH3_TX_OP_MODE_IDX 21U
#define EQOS_MTL_TXQ0_QW_IDX 22U
#define EQOS_MTL_TXQ1_QW_IDX 23U #define EQOS_MTL_TXQ1_QW_IDX 23U
#define EQOS_MTL_TXQ2_QW_IDX 24U #define EQOS_MTL_TXQ2_QW_IDX 24U
#define EQOS_MTL_TXQ3_QW_IDX 25U #define EQOS_MTL_TXQ3_QW_IDX 25U
#define EQOS_MTL_CH0_RX_OP_MODE_IDX 26U
#define EQOS_MTL_CH1_RX_OP_MODE_IDX 27U #define EQOS_MTL_CH1_RX_OP_MODE_IDX 27U
#define EQOS_MTL_CH2_RX_OP_MODE_IDX 28U #define EQOS_MTL_CH2_RX_OP_MODE_IDX 28U
#define EQOS_MTL_CH3_RX_OP_MODE_IDX 29U #define EQOS_MTL_CH3_RX_OP_MODE_IDX 29U
#endif /* !OSI_STRIPPED_LIB */
#define EQOS_MTL_CH0_RX_OP_MODE_IDX 26U
#define EQOS_DMA_SBUS_IDX 30U #define EQOS_DMA_SBUS_IDX 30U
#define EQOS_MAX_CORE_SAFETY_REGS 31U #define EQOS_MAX_CORE_SAFETY_REGS 31U
/** @} */ /** @} */
@@ -610,7 +617,9 @@ struct core_func_safety {
/* To add new registers to backup during suspend, and restore during resume /* To add new registers to backup during suspend, and restore during resume
* add it before this line, and increment EQOS_MAC_BAK_IDX accordingly. * add it before this line, and increment EQOS_MAC_BAK_IDX accordingly.
*/ */
#define EQOS_MAX_BAK_IDX ((EQOS_PAD_AUTO_CAL_CFG_BAK_IDX + 1U))
#ifndef OSI_STRIPPED_LIB
#define EQOS_MAX_BAK_IDX ((EQOS_PAD_AUTO_CAL_CFG_BAK_IDX + 1U))
#endif /* !OSI_STRIPPED_LIB */
/** @} */ /** @} */
#endif #endif

38
osi/core/osi_core.c
View File

@@ -470,44 +470,6 @@ nve32_t osi_set_systime_to_mac(struct osi_core_priv_data *const osi_core,
return -1; return -1;
} }
/**
*@brief div_u64_rem - updates remainder and returns Quotient
*
* @note
* Algorithm:
* - Dividend will be divided by divisor and stores the
* remainder value and returns quotient
*
* @param[in] dividend: Dividend value
* @param[in] divisor: Divisor value
* @param[out] remain: Remainder
*
* @pre MAC IP should be out of reset and need to be initialized as the
* requirements
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @returns Quotient
*/
static inline nveu64_t div_u64_rem(nveu64_t dividend,
nveu64_t divisor,
nveu64_t *remain)
{
nveu64_t ret = 0;
if (divisor != 0U) {
*remain = dividend % divisor;
ret = dividend / divisor;
} else {
ret = 0;
}
return ret;
}
/** /**
* @brief div_u64 - Calls a function which returns quotient * @brief div_u64 - Calls a function which returns quotient
* *

48
osi/dma/eqos_dma.c
View File

@@ -986,30 +986,6 @@ static void eqos_clear_vm_rx_intr(void *addr, nveu32_t chan)
(nveu8_t *)addr + EQOS_VIRT_INTR_CHX_STATUS(chan)); (nveu8_t *)addr + EQOS_VIRT_INTR_CHX_STATUS(chan));
} }
static struct osi_dma_chan_ops eqos_dma_chan_ops = {
.set_tx_ring_len = eqos_set_tx_ring_len,
.set_rx_ring_len = eqos_set_rx_ring_len,
.set_tx_ring_start_addr = eqos_set_tx_ring_start_addr,
.set_rx_ring_start_addr = eqos_set_rx_ring_start_addr,
.update_tx_tailptr = eqos_update_tx_tailptr,
.update_rx_tailptr = eqos_update_rx_tailptr,
.disable_chan_tx_intr = eqos_disable_chan_tx_intr,
.enable_chan_tx_intr = eqos_enable_chan_tx_intr,
.disable_chan_rx_intr = eqos_disable_chan_rx_intr,
.enable_chan_rx_intr = eqos_enable_chan_rx_intr,
.start_dma = eqos_start_dma,
.stop_dma = eqos_stop_dma,
.init_dma_channel = eqos_init_dma_channel,
.set_rx_buf_len = eqos_set_rx_buf_len,
#ifndef OSI_STRIPPED_LIB
.validate_regs = eqos_validate_dma_regs,
.config_slot = eqos_config_slot,
#endif /* !OSI_STRIPPED_LIB */
.get_global_dma_status = eqos_get_global_dma_status,
.clear_vm_tx_intr = eqos_clear_vm_tx_intr,
.clear_vm_rx_intr = eqos_clear_vm_rx_intr,
};
/** /**
* @brief eqos_get_dma_safety_config - EQOS get DMA safety configuration * @brief eqos_get_dma_safety_config - EQOS get DMA safety configuration
*/ */
@@ -1023,5 +999,29 @@ void *eqos_get_dma_safety_config(void)
*/ */
struct osi_dma_chan_ops *eqos_get_dma_chan_ops(void) struct osi_dma_chan_ops *eqos_get_dma_chan_ops(void)
{ {
static struct osi_dma_chan_ops eqos_dma_chan_ops = {
.set_tx_ring_len = eqos_set_tx_ring_len,
.set_rx_ring_len = eqos_set_rx_ring_len,
.set_tx_ring_start_addr = eqos_set_tx_ring_start_addr,
.set_rx_ring_start_addr = eqos_set_rx_ring_start_addr,
.update_tx_tailptr = eqos_update_tx_tailptr,
.update_rx_tailptr = eqos_update_rx_tailptr,
.disable_chan_tx_intr = eqos_disable_chan_tx_intr,
.enable_chan_tx_intr = eqos_enable_chan_tx_intr,
.disable_chan_rx_intr = eqos_disable_chan_rx_intr,
.enable_chan_rx_intr = eqos_enable_chan_rx_intr,
.start_dma = eqos_start_dma,
.stop_dma = eqos_stop_dma,
.init_dma_channel = eqos_init_dma_channel,
.set_rx_buf_len = eqos_set_rx_buf_len,
#ifndef OSI_STRIPPED_LIB
.validate_regs = eqos_validate_dma_regs,
.config_slot = eqos_config_slot,
#endif /* !OSI_STRIPPED_LIB */
.get_global_dma_status = eqos_get_global_dma_status,
.clear_vm_tx_intr = eqos_clear_vm_tx_intr,
.clear_vm_rx_intr = eqos_clear_vm_rx_intr,
};
return &eqos_dma_chan_ops; return &eqos_dma_chan_ops;
} }

17
osi/dma/eqos_dma.h
View File

@@ -43,7 +43,9 @@
#define EQOS_DMA_CHX_RX_CTRL(x) ((0x0080U * (x)) + 0x1108U) #define EQOS_DMA_CHX_RX_CTRL(x) ((0x0080U * (x)) + 0x1108U)
#define EQOS_DMA_CHX_INTR_ENA(x) ((0x0080U * (x)) + 0x1134U) #define EQOS_DMA_CHX_INTR_ENA(x) ((0x0080U * (x)) + 0x1134U)
#define EQOS_DMA_CHX_RX_WDT(x) ((0x0080U * (x)) + 0x1138U) #define EQOS_DMA_CHX_RX_WDT(x) ((0x0080U * (x)) + 0x1138U)
#ifndef OSI_STRIPPED_LIB
#define EQOS_DMA_CHX_SLOT_CTRL(x) ((0x0080U * (x)) + 0x113CU) #define EQOS_DMA_CHX_SLOT_CTRL(x) ((0x0080U * (x)) + 0x113CU)
#endif /* !OSI_STRIPPED_LIB */
#define EQOS_DMA_CHX_RDTP(x) ((0x0080U * (x)) + 0x1128U) #define EQOS_DMA_CHX_RDTP(x) ((0x0080U * (x)) + 0x1128U)
#define EQOS_DMA_CHX_RDLH(x) ((0x0080U * (x)) + 0x1118U) #define EQOS_DMA_CHX_RDLH(x) ((0x0080U * (x)) + 0x1118U)
@@ -106,38 +108,41 @@
#define EQOS_DMA_CHX_TDRL_MASK 0x3FFU #define EQOS_DMA_CHX_TDRL_MASK 0x3FFU
#define EQOS_DMA_CHX_RDRL_MASK 0x3FFU #define EQOS_DMA_CHX_RDRL_MASK 0x3FFU
#define EQOS_DMA_CHX_INTR_ENA_MASK 0xFFC7U #define EQOS_DMA_CHX_INTR_ENA_MASK 0xFFC7U
#ifndef OSI_STRIPPED_LIB
#define EQOS_DMA_CHX_SLOT_SIV_MASK 0xFFFU #define EQOS_DMA_CHX_SLOT_SIV_MASK 0xFFFU
#define EQOS_DMA_CHX_SLOT_SIV_SHIFT 4U #define EQOS_DMA_CHX_SLOT_SIV_SHIFT 4U
#define EQOS_DMA_CHX_SLOT_ESC 0x1U #define EQOS_DMA_CHX_SLOT_ESC 0x1U
#endif /* !OSI_STRIPPED_LIB */
/* To add new registers to validate,append at end of below macro list and /* To add new registers to validate,append at end of below macro list and
* increment EQOS_MAX_DMA_SAFETY_REGS. * increment EQOS_MAX_DMA_SAFETY_REGS.
* Using macros instead of enum due to misra error. * Using macros instead of enum due to misra error.
*/ */
#define EQOS_DMA_CH0_CTRL_IDX 0U #define EQOS_DMA_CH0_CTRL_IDX 0U
#define EQOS_DMA_CH0_TX_CTRL_IDX 4U
#define EQOS_DMA_CH0_RX_CTRL_IDX 8U
#define EQOS_DMA_CH0_RDRL_IDX 16U
#define EQOS_DMA_CH0_TDRL_IDX 12U
#define EQOS_DMA_CH0_INTR_ENA_IDX 20U
#ifndef OSI_STRIPPED_LIB
#define EQOS_DMA_CH1_CTRL_IDX 1U #define EQOS_DMA_CH1_CTRL_IDX 1U
#define EQOS_DMA_CH2_CTRL_IDX 2U #define EQOS_DMA_CH2_CTRL_IDX 2U
#define EQOS_DMA_CH3_CTRL_IDX 3U #define EQOS_DMA_CH3_CTRL_IDX 3U
#define EQOS_DMA_CH0_TX_CTRL_IDX 4U
#define EQOS_DMA_CH1_TX_CTRL_IDX 5U #define EQOS_DMA_CH1_TX_CTRL_IDX 5U
#define EQOS_DMA_CH2_TX_CTRL_IDX 6U #define EQOS_DMA_CH2_TX_CTRL_IDX 6U
#define EQOS_DMA_CH3_TX_CTRL_IDX 7U #define EQOS_DMA_CH3_TX_CTRL_IDX 7U
#define EQOS_DMA_CH0_RX_CTRL_IDX 8U
#define EQOS_DMA_CH1_RX_CTRL_IDX 9U #define EQOS_DMA_CH1_RX_CTRL_IDX 9U
#define EQOS_DMA_CH2_RX_CTRL_IDX 10U #define EQOS_DMA_CH2_RX_CTRL_IDX 10U
#define EQOS_DMA_CH3_RX_CTRL_IDX 11U #define EQOS_DMA_CH3_RX_CTRL_IDX 11U
#define EQOS_DMA_CH0_TDRL_IDX 12U
#define EQOS_DMA_CH1_TDRL_IDX 13U #define EQOS_DMA_CH1_TDRL_IDX 13U
#define EQOS_DMA_CH2_TDRL_IDX 14U #define EQOS_DMA_CH2_TDRL_IDX 14U
#define EQOS_DMA_CH3_TDRL_IDX 15U #define EQOS_DMA_CH3_TDRL_IDX 15U
#define EQOS_DMA_CH0_RDRL_IDX 16U
#define EQOS_DMA_CH1_RDRL_IDX 17U #define EQOS_DMA_CH1_RDRL_IDX 17U
#define EQOS_DMA_CH2_RDRL_IDX 18U #define EQOS_DMA_CH2_RDRL_IDX 18U
#define EQOS_DMA_CH3_RDRL_IDX 19U #define EQOS_DMA_CH3_RDRL_IDX 19U
#define EQOS_DMA_CH0_INTR_ENA_IDX 20U
#define EQOS_DMA_CH1_INTR_ENA_IDX 21U #define EQOS_DMA_CH1_INTR_ENA_IDX 21U
#define EQOS_DMA_CH2_INTR_ENA_IDX 22U #define EQOS_DMA_CH2_INTR_ENA_IDX 22U
#define EQOS_DMA_CH3_INTR_ENA_IDX 23U #define EQOS_DMA_CH3_INTR_ENA_IDX 23U
#endif /* OSI_STRIPPED_LIB */
#define EQOS_MAX_DMA_SAFETY_REGS 24U #define EQOS_MAX_DMA_SAFETY_REGS 24U
#define EQOS_AXI_BUS_WIDTH 0x10U #define EQOS_AXI_BUS_WIDTH 0x10U
/** @} */ /** @} */

16
osi/dma/osi_dma_local.h
View File

@@ -49,4 +49,20 @@
* @retval -1 on failure. * @retval -1 on failure.
*/ */
nve32_t dma_desc_init(struct osi_dma_priv_data *osi_dma); nve32_t dma_desc_init(struct osi_dma_priv_data *osi_dma);
#define CHECK_CHAN_BOUND(chan) \
{ \
if ((chan) >= OSI_EQOS_MAX_NUM_CHANS) { \
return; \
} \
} \
/**
* @addtogroup Helper Helper MACROS
*
* @brief EQOS DMA generic helper MACROS.
* @{
*/
#define BOOLEAN_FALSE (0U != 0U)
#define L32(data) ((data) & 0xFFFFFFFFU)
#define H32(data) (((data) & 0xFFFFFFFF00000000UL) >> 32UL)
#endif /* OSI_DMA_LOCAL_H */ #endif /* OSI_DMA_LOCAL_H */