diff --git a/include/osi_core.h b/include/osi_core.h
index d2d920d..4bfd577 100644
--- a/include/osi_core.h
+++ b/include/osi_core.h
@@ -1145,6 +1145,8 @@ struct core_padctrl {
 struct osi_core_priv_data {
 	/** Memory mapped base address of MAC IP */
 	void *base;
+	/** Memory mapped base address of HV window */
+	void *hv_base;
 	/** Memory mapped base address of DMA window of MAC IP */
 	void *dma_base;
 	/** Memory mapped base address of XPCS IP */
@@ -1256,6 +1258,8 @@ struct osi_core_priv_data {
 	nveu32_t phy_iface_mode;
 	/** eqos pad control structure */
 	struct core_padctrl padctrl;
+	/** MGBE MAC instance ID's */
+	nveu32_t instance_id;
 };
 
 /**
diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c
index ce278c5..edfdb9e 100644
--- a/osi/core/eqos_core.c
+++ b/osi/core/eqos_core.c
@@ -2078,15 +2078,30 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core,
 	osi_writela(osi_core, EQOS_MMC_CNTRL_CNTRST,
 		    (nveu8_t *)osi_core->base + EQOS_MMC_CNTRL);
 
-	/* AXI ASID CTRL for channel 0 to 3 */
-	osi_writela(osi_core, EQOS_AXI_ASID_CTRL_VAL,
-		    (nveu8_t *)osi_core->base + EQOS_AXI_ASID_CTRL);
+	if (osi_core->use_virtualization == OSI_DISABLE) {
+		if (osi_core->hv_base != OSI_NULL) {
+			osi_writela(osi_core, EQOS_5_30_ASID_CTRL_VAL,
+				    (nveu8_t *)osi_core->hv_base +
+				    EQOS_AXI_ASID_CTRL);
 
-	/* AXI ASID1 CTRL for channel 4 to 7 */
-	if (osi_core->mac_ver > OSI_EQOS_MAC_5_00) {
-		osi_writela(osi_core, EQOS_AXI_ASID1_CTRL_VAL,
-			    (nveu8_t *)osi_core->base +
-			    EQOS_AXI_ASID1_CTRL);
+			osi_writela(osi_core, EQOS_5_30_ASID1_CTRL_VAL,
+				    (nveu8_t *)osi_core->hv_base +
+				    EQOS_AXI_ASID1_CTRL);
+		}
+
+		if (osi_core->mac_ver < OSI_EQOS_MAC_5_30) {
+			/* AXI ASID CTRL for channel 0 to 3 */
+			osi_writela(osi_core, EQOS_AXI_ASID_CTRL_VAL,
+				    (nveu8_t *)osi_core->base +
+				    EQOS_AXI_ASID_CTRL);
+
+			/* AXI ASID1 CTRL for channel 4 to 7 */
+			if (osi_core->mac_ver > OSI_EQOS_MAC_5_00) {
+				osi_writela(osi_core, EQOS_AXI_ASID1_CTRL_VAL,
+					    (nveu8_t *)osi_core->base +
+					    EQOS_AXI_ASID1_CTRL);
+			}
+		}
 	}
 
 	/* Mapping MTL Rx queue and DMA Rx channel */
diff --git a/osi/core/eqos_core.h b/osi/core/eqos_core.h
index 687b1a8..07fb3b3 100644
--- a/osi/core/eqos_core.h
+++ b/osi/core/eqos_core.h
@@ -496,6 +496,21 @@
 				 (TEGRA_SID_EQOS_CH6) |\
 				 (TEGRA_SID_EQOS_CH5) |\
 				 (TEGRA_SID_EQOS))
+#define EQOS_5_30_SID		0x3U
+#define EQOS_5_30_SID_CH3	((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_24)
+#define EQOS_5_30_SID_CH2	((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_16)
+#define EQOS_5_30_SID_CH1	((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_8)
+#define EQOS_5_30_ASID_CTRL_VAL	((EQOS_5_30_SID_CH3) |\
+				 (EQOS_5_30_SID_CH2) |\
+				 (EQOS_5_30_SID_CH1) |\
+				 (EQOS_5_30_SID))
+#define EQOS_5_30_SID_CH7	((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_24)
+#define EQOS_5_30_SID_CH6	((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_16)
+#define EQOS_5_30_SID_CH5	((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_8)
+#define EQOS_5_30_ASID1_CTRL_VAL ((EQOS_5_30_SID_CH7) |\
+				 (EQOS_5_30_SID_CH6) |\
+				 (EQOS_5_30_SID_CH5) |\
+				 (EQOS_5_30_SID))
 #define EQOS_MMC_INTR_DISABLE	0xFFFFFFFFU
 
 /* MAC FPE control/statusOSI_BITmap */
diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index 4e5689c..21fe7f0 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -2994,9 +2994,13 @@ static void mgbe_tsn_init(struct osi_core_priv_data *osi_core,
  *
  * @note OSD layer needs to update number of VM channels and
  *	DMA channel list in osi_vm_irq_data.
+ *
+ * @retval 0 on success
+ * @retval -1 on failure.
  */
-static void mgbe_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core)
+static nve32_t mgbe_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core)
 {
+	nveu32_t sid[4] = { MGBE0_SID, MGBE1_SID, MGBE2_SID, MGBE3_SID };
 	struct osi_vm_irq_data *irq_data;
 	nveu32_t i, j;
 	nveu32_t chan;
@@ -3017,7 +3021,29 @@ static void mgbe_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core)
 		}
 	}
 
-	osi_writel(0xD, (nveu8_t *)osi_core->base + 0x8400);
+	if ((osi_core->use_virtualization == OSI_DISABLE) &&
+	    (osi_core->hv_base != OSI_NULL)) {
+		if (osi_core->instance_id > 3U) {
+			OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+				     "Wrong MAC instance-ID\n",
+				     osi_core->instance_id);
+			return -1;
+		}
+
+		osi_writela(osi_core, MGBE_SID_VAL1(sid[osi_core->instance_id]),
+			    (nveu8_t *)osi_core->hv_base +
+			    MGBE_WRAP_AXI_ASID0_CTRL);
+
+		osi_writela(osi_core, MGBE_SID_VAL1(sid[osi_core->instance_id]),
+			    (nveu8_t *)osi_core->hv_base +
+			    MGBE_WRAP_AXI_ASID1_CTRL);
+
+		osi_writela(osi_core, MGBE_SID_VAL2(sid[osi_core->instance_id]),
+			    (nveu8_t *)osi_core->hv_base +
+			    MGBE_WRAP_AXI_ASID2_CTRL);
+	}
+
+	return 0;
 }
 
 
@@ -3127,9 +3153,7 @@ static nve32_t mgbe_core_init(struct osi_core_priv_data *osi_core,
 			      osi_core->hw_feature->fpe_sel);
 	}
 
-	mgbe_dma_chan_to_vmirq_map(osi_core);
-
-	return 0;
+	return mgbe_dma_chan_to_vmirq_map(osi_core);
 }
 
 /**
diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h
index 9ffc291..0719c41 100644
--- a/osi/core/mgbe_core.h
+++ b/osi/core/mgbe_core.h
@@ -122,6 +122,9 @@
  * @brief MGBE Wrapper register offsets
  * @{
  */
+#define MGBE_WRAP_AXI_ASID0_CTRL	0x8400
+#define MGBE_WRAP_AXI_ASID1_CTRL	0x8404
+#define MGBE_WRAP_AXI_ASID2_CTRL	0x8408
 #define MGBE_WRAP_COMMON_INTR_ENABLE	0x8704
 #define MGBE_WRAP_COMMON_INTR_STATUS	0x8708
 #define MGBE_VIRT_INTR_APB_CHX_CNTRL(x)	(0x8200U + ((x) * 4U))
@@ -671,6 +674,16 @@
 #define MGBE_MAC_EXT_CNF_EIPG_MASK		0x7FU
 /* TX timestamp */
 #define MGBE_MAC_TSS_TXTSC			OSI_BIT(15)
+#define MGBE0_SID				((nveu32_t)0x6U)
+#define MGBE1_SID				((nveu32_t)0x49U)
+#define MGBE2_SID				((nveu32_t)0x4AU)
+#define MGBE3_SID				((nveu32_t)0x4BU)
+#define MGBE_SID_VAL1(x)			(((x) << 24U) |\
+						 ((x) << 16U) |\
+						 ((x) << 8U) |\
+						 (x))
+#define MGBE_SID_VAL2(x)			(((x) << 8U) |\
+						 (x))
 /** @} */
 
 /**