osi: l3l4: disable IPFE when wildcard enabled

- Having IPFE set causes MAC to drop all packets which
  do not match with configured l3l4 filters. Hence
  disable IPFE related code using a compile switch.

Bug 3576506

Change-Id: Ibf6c0e724141c9f7dc16a41de476057fc8eb7835
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2834367
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Hareesh Kesireddy
2022-12-28 10:39:51 +05:30
committed by mobile promotions
parent cdc06a45d3
commit 086e4f09fc
6 changed files with 23 additions and 3 deletions

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@@ -1357,9 +1357,11 @@ struct osi_core_priv_data {
nveu32_t mdc_cr; nveu32_t mdc_cr;
/** VLAN tag stripping enable(1) or disable(0) */ /** VLAN tag stripping enable(1) or disable(0) */
nveu32_t strip_vlan_tag; nveu32_t strip_vlan_tag;
#if !defined(L3L4_WILDCARD_FILTER)
/** L3L4 filter bit bask, set index corresponding bit for /** L3L4 filter bit bask, set index corresponding bit for
* filter if filter enabled */ * filter if filter enabled */
nveu32_t l3l4_filter_bitmask; nveu32_t l3l4_filter_bitmask;
#endif /* !L3L4_WILDCARD_FILTER */
/** Flag which decides virtualization is enabled(1) or disabled(0) */ /** Flag which decides virtualization is enabled(1) or disabled(0) */
nveu32_t use_virtualization; nveu32_t use_virtualization;
/** HW supported feature list */ /** HW supported feature list */

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@@ -585,6 +585,7 @@ nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
return ret; return ret;
} }
#if !defined(L3L4_WILDCARD_FILTER)
nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core, nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core,
const nveu32_t filter_enb_dis) const nveu32_t filter_enb_dis)
{ {
@@ -608,6 +609,7 @@ nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core,
fail: fail:
return ret; return ret;
} }
#endif /* !L3L4_WILDCARD_FILTER */
/** /**
* @brief hw_est_read - indirect read the GCL to Software own list * @brief hw_est_read - indirect read the GCL to Software own list

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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -85,7 +85,9 @@
#define MAC_PFR_HPF OSI_BIT(10) #define MAC_PFR_HPF OSI_BIT(10)
#define MAC_PFR_VTFE OSI_BIT(16) #define MAC_PFR_VTFE OSI_BIT(16)
#define MAC_PFR_IPFE OSI_BIT(20) #define MAC_PFR_IPFE OSI_BIT(20)
#if !defined(L3L4_WILDCARD_FILTER)
#define MAC_PFR_IPFE_SHIFT 20U #define MAC_PFR_IPFE_SHIFT 20U
#endif /* !L3L4_WILDCARD_FILTER */
#define MAC_PFR_DNTU OSI_BIT(21) #define MAC_PFR_DNTU OSI_BIT(21)
#define MAC_PFR_RA OSI_BIT(31) #define MAC_PFR_RA OSI_BIT(31)
@@ -154,8 +156,10 @@ nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core,
struct osi_core_ptp_tsc_data *data); struct osi_core_ptp_tsc_data *data);
nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core, nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter); const struct osi_filter *filter);
#if !defined(L3L4_WILDCARD_FILTER)
nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core, nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core,
const nveu32_t filter_enb_dis); const nveu32_t filter_enb_dis);
#endif /* !L3L4_WILDCARD_FILTER */
nve32_t hw_config_est(struct osi_core_priv_data *const osi_core, nve32_t hw_config_est(struct osi_core_priv_data *const osi_core,
struct osi_est_config *const est); struct osi_est_config *const est);
nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core, nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core,

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@@ -1241,8 +1241,7 @@ static void eqos_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core)
* - TraceID:ETHERNET_NVETHERNETRM_006 * - TraceID:ETHERNET_NVETHERNETRM_006
* *
* @param[in] osi_core: OSI core private data structure. Used params are * @param[in] osi_core: OSI core private data structure. Used params are
* - base, dcs_en, num_mtl_queues, mtl_queues, mtu, stip_vlan_tag, pause_frames, * - base, dcs_en, num_mtl_queues, mtl_queues, mtu, stip_vlan_tag, pause_frames.
* l3l4_filter_bitmask
* *
* @pre * @pre
* - MAC should be out of reset. See osi_poll_for_mac_reset_complete() * - MAC should be out of reset. See osi_poll_for_mac_reset_complete()
@@ -1363,8 +1362,10 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core)
osi_core->hw_feature->fpe_sel); osi_core->hw_feature->fpe_sel);
} }
#if !defined(L3L4_WILDCARD_FILTER)
/* initialize L3L4 Filters variable */ /* initialize L3L4 Filters variable */
osi_core->l3l4_filter_bitmask = OSI_NONE; osi_core->l3l4_filter_bitmask = OSI_NONE;
#endif /* !L3L4_WILDCARD_FILTER */
if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) { if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) {
eqos_dma_chan_to_vmirq_map(osi_core); eqos_dma_chan_to_vmirq_map(osi_core);

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@@ -2083,6 +2083,11 @@ static nve32_t mgbe_core_init(struct osi_core_priv_data *const osi_core)
osi_core->hw_feature->fpe_sel); osi_core->hw_feature->fpe_sel);
} }
#if !defined(L3L4_WILDCARD_FILTER)
/* initialize L3L4 Filters variable */
osi_core->l3l4_filter_bitmask = OSI_NONE;
#endif /* !L3L4_WILDCARD_FILTER */
ret = mgbe_dma_chan_to_vmirq_map(osi_core); ret = mgbe_dma_chan_to_vmirq_map(osi_core);
fail: fail:
return ret; return ret;

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@@ -934,8 +934,10 @@ static nve32_t configure_l3l4_filter_helper(struct osi_core_priv_data *const osi
OSI_CORE_INFO((osi_core->osd), (OSI_LOG_ARG_OUTOFBOUND), OSI_CORE_INFO((osi_core->osd), (OSI_LOG_ARG_OUTOFBOUND),
("L3L4: ADD: "), (filter_no)); ("L3L4: ADD: "), (filter_no));
#if !defined(L3L4_WILDCARD_FILTER)
/* update filter mask bit */ /* update filter mask bit */
osi_core->l3l4_filter_bitmask |= ((nveu32_t)1U << (filter_no & 0x1FU)); osi_core->l3l4_filter_bitmask |= ((nveu32_t)1U << (filter_no & 0x1FU));
#endif /* !L3L4_WILDCARD_FILTER */
} else { } else {
/* Clear the filter data. /* Clear the filter data.
* osi_memset is an internal function and it cannot fail, hence * osi_memset is an internal function and it cannot fail, hence
@@ -945,10 +947,13 @@ static nve32_t configure_l3l4_filter_helper(struct osi_core_priv_data *const osi
OSI_CORE_INFO((osi_core->osd), (OSI_LOG_ARG_OUTOFBOUND), OSI_CORE_INFO((osi_core->osd), (OSI_LOG_ARG_OUTOFBOUND),
("L3L4: DELETE: "), (filter_no)); ("L3L4: DELETE: "), (filter_no));
#if !defined(L3L4_WILDCARD_FILTER)
/* update filter mask bit */ /* update filter mask bit */
osi_core->l3l4_filter_bitmask &= ~((nveu32_t)1U << (filter_no & 0x1FU)); osi_core->l3l4_filter_bitmask &= ~((nveu32_t)1U << (filter_no & 0x1FU));
#endif /* !L3L4_WILDCARD_FILTER */
} }
#if !defined(L3L4_WILDCARD_FILTER)
if (osi_core->l3l4_filter_bitmask != 0U) { if (osi_core->l3l4_filter_bitmask != 0U) {
/* enable l3l4 filter */ /* enable l3l4 filter */
ret = hw_config_l3_l4_filter_enable(osi_core, OSI_ENABLE); ret = hw_config_l3_l4_filter_enable(osi_core, OSI_ENABLE);
@@ -956,6 +961,7 @@ static nve32_t configure_l3l4_filter_helper(struct osi_core_priv_data *const osi
/* disable l3l4 filter */ /* disable l3l4 filter */
ret = hw_config_l3_l4_filter_enable(osi_core, OSI_DISABLE); ret = hw_config_l3_l4_filter_enable(osi_core, OSI_DISABLE);
} }
#endif /* !L3L4_WILDCARD_FILTER */
exit_func: exit_func: