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osi: core: add support for HSI error injection

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Add new osi ioctl command OSI_CMD_HSI_INJECT_ERR for
IP specific error injection configuration.
different type of error is injected based on input
error code value.

Bug 3806923
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Change-Id: I01269d211293aa67471fadcf6e349f049f9c1a51
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2786840
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Om Prakash Singh
2022-10-04 20:22:08 +05:30
committed by Bhadram Varka
parent 858dc4815f
commit 0b77df81ad
11 changed files with 237 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

72
osi/core/core_common.c
View File

@@ -25,6 +25,7 @@
#include "mgbe_core.h"
#include "eqos_core.h"
#include "xpcs.h"
#include "macsec.h"
static inline nve32_t poll_check(struct osi_core_priv_data *const osi_core, nveu8_t *addr,
nveu32_t bit_check, nveu32_t *value)
@@ -1408,3 +1409,74 @@ void hw_tsn_init(struct osi_core_priv_data *osi_core,
user application should use IOCTL to set CBS as per requirement
*/
}
#ifdef HSI_SUPPORT
/**
* @brief hsi_common_error_inject
*
* Algorithm:
* - For macsec HSI: trigger interrupt using MACSEC_*_INTERRUPT_SET_0 register
* - For mmc counter based: trigger interrupt by incrementing count by threshold value
* - For rest: Directly set the error detected as there is no other mean to induce error
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] error_code: Ethernet HSI error code
*
* @note MAC should be init and started. see osi_start_mac()
*/
void hsi_common_error_inject(struct osi_core_priv_data *osi_core,
nveu32_t error_code)
{
switch (error_code) {
case OSI_INBOUND_BUS_CRC_ERR:
osi_core->mmc.mmc_rx_crc_error =
osi_update_stats_counter(osi_core->mmc.mmc_rx_crc_error,
osi_core->hsi.err_count_threshold);
break;
case OSI_RECEIVE_CHECKSUM_ERR:
osi_core->mmc.mmc_rx_udp_err =
osi_update_stats_counter(osi_core->mmc.mmc_rx_udp_err,
osi_core->hsi.err_count_threshold);
break;
case OSI_MACSEC_RX_CRC_ERR:
osi_writela(osi_core, MACSEC_RX_MAC_CRC_ERROR,
(nveu8_t *)osi_core->macsec_base +
MACSEC_RX_ISR_SET);
break;
case OSI_MACSEC_TX_CRC_ERR:
osi_writela(osi_core, MACSEC_TX_MAC_CRC_ERROR,
(nveu8_t *)osi_core->macsec_base +
MACSEC_TX_ISR_SET);
break;
case OSI_MACSEC_RX_ICV_ERR:
osi_writela(osi_core, MACSEC_RX_ICV_ERROR,
(nveu8_t *)osi_core->macsec_base +
MACSEC_RX_ISR_SET);
break;
case OSI_MACSEC_REG_VIOL_ERR:
osi_writela(osi_core, MACSEC_SECURE_REG_VIOL,
(nveu8_t *)osi_core->macsec_base +
MACSEC_COMMON_ISR_SET);
break;
case OSI_TX_FRAME_ERR:
osi_core->hsi.report_count_err[TX_FRAME_ERR_IDX] = OSI_ENABLE;
osi_core->hsi.err_code[TX_FRAME_ERR_IDX] = OSI_TX_FRAME_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
break;
case OSI_PCS_AUTONEG_ERR:
osi_core->hsi.err_code[AUTONEG_ERR_IDX] = OSI_PCS_AUTONEG_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[AUTONEG_ERR_IDX] = OSI_ENABLE;
break;
case OSI_XPCS_WRITE_FAIL_ERR:
osi_core->hsi.err_code[XPCS_WRITE_FAIL_IDX] = OSI_XPCS_WRITE_FAIL_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[XPCS_WRITE_FAIL_IDX] = OSI_ENABLE;
break;
default:
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Invalid error code\n", (nveu32_t)error_code);
break;
}
}
#endif