nv-tegra-mirror/nvethernetrm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/kernel/nvethernetrm.git synced 2025-12-22 09:12:10 +03:00
Code Issues Packages Projects Releases Wiki Activity

osi:dma: Fix top-25 Static Analysis issues

Browse Source 
Fixed below rules:
CERT INT32-C
CERT INT30-C
CERT INT08-C
CERT EXP39-C

Jira NET-2045

Change-Id: I1cf3ea2d2f037f70821eaabc737235ce8a592b15
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3275403
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
This commit is contained in:
Sanath Kumar Gampa
2024-12-31 06:28:59 +00:00
committed by mobile promotions
parent db9b81458e
commit 144d7dc226
7 changed files with 154 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
osi/dma/debug.c
View File

@@ -67,7 +67,7 @@ static void dump_struct(struct osi_dma_priv_data *osi_dma,
*/
void structs_dump(struct osi_dma_priv_data *osi_dma)
{
struct dma_local *l_dma = (struct dma_local *)osi_dma;
struct dma_local *l_dma = (struct dma_local *)((void *)osi_dma);
nveu32_t i = 0;
osi_dma->osd_ops.printf(osi_dma, OSI_DEBUG_TYPE_STRUCTS,
@@ -114,7 +114,7 @@ void structs_dump(struct osi_dma_priv_data *osi_dma)
*/
void reg_dump(struct osi_dma_priv_data *osi_dma)
{
struct dma_local *l_dma = (struct dma_local *)osi_dma;
struct dma_local *l_dma = (struct dma_local *)((void *)osi_dma);
unsigned int max_addr;
unsigned int addr;
unsigned int reg_val;
@@ -164,6 +164,13 @@ static void rx_desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int idx,
struct osi_rx_desc *rx_desc = rx_ring->rx_desc + idx;
struct osd_dma_ops *ops = &osi_dma->osd_ops;
if ((rx_ring->rx_desc_phy_addr) >
((OSI_ULLONG_MAX) - (idx * sizeof(struct osi_rx_desc)))) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"Invalid rx addr !!!\n", 0ULL);
goto exit_func;
}
ops->printf(osi_dma, OSI_DEBUG_TYPE_DESC,
"N [%02d %4p %04d %lx R_D] = %#x:%#x:%#x:%#x\n",
chan, rx_desc, idx,
@@ -171,6 +178,9 @@ static void rx_desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int idx,
rx_desc->rdes3, rx_desc->rdes2,
rx_desc->rdes1, rx_desc->rdes0);
exit_func:
return;
}
/**
@@ -191,10 +201,21 @@ static void tx_desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int f_idx,
struct osd_dma_ops *ops = &osi_dma->osd_ops;
unsigned int ctxt = 0, i = 0;
if (osi_dma->tx_ring_sz == 0U) {
ops->printf(osi_dma, OSI_DEBUG_TYPE_DESC,
"In Valid tx_ring_sz\n");
goto exit_func;
}
if (f_idx == l_idx) {
tx_desc = tx_ring->tx_desc + f_idx;
ctxt = tx_desc->tdes3 & TDES3_CTXT;
if ((tx_ring->tx_desc_phy_addr) >
((OSI_ULLONG_MAX) - (f_idx * sizeof(struct osi_tx_desc)))) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"Invalid addr !!!\n", 0ULL);
goto exit_func;
}
ops->printf(osi_dma, OSI_DEBUG_TYPE_DESC,
"%s [%02d %4p %04d %lx %s] = %#x:%#x:%#x:%#x\n",
(ctxt == TDES3_CTXT) ? "C" : "N",
@@ -207,6 +228,12 @@ static void tx_desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int f_idx,
int cnt;
if (f_idx > l_idx) {
if ((l_idx > (UINT_MAX - osi_dma->tx_ring_sz)) ||
((l_idx + osi_dma->tx_ring_sz) < f_idx)) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"Invalid idx !!!\n", 0ULL);
goto exit_func;
}
cnt = (int)(l_idx + osi_dma->tx_ring_sz - f_idx);
} else {
cnt = (int)(l_idx - f_idx);
@@ -216,6 +243,12 @@ static void tx_desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int f_idx,
tx_desc = tx_ring->tx_desc + i;
ctxt = tx_desc->tdes3 & TDES3_CTXT;
if ((tx_ring->tx_desc_phy_addr) >
((OSI_ULLONG_MAX) - (i * sizeof(struct osi_tx_desc)))) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"Invalid addr !!!\n", 0ULL);
break;
}
ops->printf(osi_dma, OSI_DEBUG_TYPE_DESC,
"%s [%02d %4p %04d %lx %s] = %#x:%#x:%#x:%#x\n",
(ctxt == TDES3_CTXT) ? "C" : "N",
@@ -228,6 +261,9 @@ static void tx_desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int f_idx,
INCR_TX_DESC_INDEX(i, osi_dma->tx_ring_sz);
}
}
exit_func:
return;
}
/**
@@ -243,6 +279,13 @@ static void tx_desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int f_idx,
void desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int f_idx,
unsigned int l_idx, unsigned int flag, unsigned int chan)
{
if ((osi_dma->tx_ring_sz == 0U) || (osi_dma->rx_ring_sz == 0U)) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"Invalid Tx/Rx ring size\n", 0ULL);
goto exit_func;
}
switch (flag & TXRX_DESC_DUMP_MASK) {
case TX_DESC_DUMP:
tx_desc_dump(osi_dma, f_idx, l_idx,
@@ -256,5 +299,8 @@ void desc_dump(struct osi_dma_priv_data *osi_dma, unsigned int f_idx,
"Invalid desc dump flag\n", 0ULL);
break;
}
exit_func:
return;
}
#endif /* OSI_DEBUG */

7
osi/dma/dma_local.h
View File

@@ -143,7 +143,7 @@ static inline void osi_dma_writel(nveu32_t val, void *addr)
#define GET_TX_TS_PKTID(idx, c) (((idx) & (PKT_ID_CNT - 1U)) | \
(((c) + 1U) << CHAN_START_POSITION))
/* T264 has saperate logic to tell vdma number so we can use all 10 bits for pktid */
#define GET_TX_TS_PKTID_T264(idx) ((++(idx)) & (PKT_ID_CNT_T264 - 1U))
#define GET_TX_TS_PKTID_T264(idx) ((((idx) & 0x7FFFFFFFU) + 1U) & (PKT_ID_CNT_T264 - 1U))
/** @} */
/**
@@ -338,8 +338,9 @@ static inline void update_rx_tail_ptr(const struct osi_dma_priv_data *const osi_
nveu64_t tailptr)
{
const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = (dma_chan & chan_mask[local_mac]) & (0xFFU);
const nveu32_t tail_ptr_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_RDTP(chan),
MGBE_DMA_CHX_RDTLP(chan),

9
osi/dma/eqos_dma.c
View File

@@ -53,6 +53,7 @@ static void eqos_config_slot(struct osi_dma_priv_data *osi_dma,
{
nveu32_t value;
nveu32_t intr;
nveu32_t local_chan = chan % OSI_EQOS_MAX_NUM_CHANS;
#if 0
CHECK_CHAN_BOUND(chan);
@@ -60,7 +61,7 @@ static void eqos_config_slot(struct osi_dma_priv_data *osi_dma,
if (set == OSI_ENABLE) {
/* Program SLOT CTRL register SIV and set ESC bit */
value = osi_dma_readl((nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
EQOS_DMA_CHX_SLOT_CTRL(local_chan));
value &= ~EQOS_DMA_CHX_SLOT_SIV_MASK;
/* remove overflow bits of interval */
intr = interval & EQOS_DMA_CHX_SLOT_SIV_MASK;
@@ -68,15 +69,15 @@ static void eqos_config_slot(struct osi_dma_priv_data *osi_dma,
/* Set ESC bit */
value |= EQOS_DMA_CHX_SLOT_ESC;
osi_dma_writel(value, (nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
EQOS_DMA_CHX_SLOT_CTRL(local_chan));
} else {
/* Clear ESC bit of SLOT CTRL register */
value = osi_dma_readl((nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
EQOS_DMA_CHX_SLOT_CTRL(local_chan));
value &= ~EQOS_DMA_CHX_SLOT_ESC;
osi_dma_writel(value, (nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
EQOS_DMA_CHX_SLOT_CTRL(local_chan));
}
}

9
osi/dma/mgbe_dma.c
View File

@@ -44,25 +44,26 @@ static void mgbe_config_slot(struct osi_dma_priv_data *osi_dma,
OSI_UNUSED unsigned int interval)
{
unsigned int value;
unsigned int local_chan = chan % OSI_MGBE_MAX_NUM_CHANS;
#if 0
MGBE_CHECK_CHAN_BOUND(chan);
#endif
if (set == OSI_ENABLE) {
/* Program SLOT CTRL register SIV and set ESC bit */
value = osi_dma_readl((unsigned char *)osi_dma->base +
MGBE_DMA_CHX_SLOT_CTRL(chan));
MGBE_DMA_CHX_SLOT_CTRL(local_chan));
/* Set ESC bit */
value |= MGBE_DMA_CHX_SLOT_ESC;
osi_dma_writel(value, (unsigned char *)osi_dma->base +
MGBE_DMA_CHX_SLOT_CTRL(chan));
MGBE_DMA_CHX_SLOT_CTRL(local_chan));
} else {
/* Clear ESC bit of SLOT CTRL register */
value = osi_dma_readl((unsigned char *)osi_dma->base +
MGBE_DMA_CHX_SLOT_CTRL(chan));
MGBE_DMA_CHX_SLOT_CTRL(local_chan));
value &= ~MGBE_DMA_CHX_SLOT_ESC;
osi_dma_writel(value, (unsigned char *)osi_dma->base +
MGBE_DMA_CHX_SLOT_CTRL(chan));
MGBE_DMA_CHX_SLOT_CTRL(local_chan));
}
}

1
osi/dma/mgbe_dma.h
View File

@@ -59,6 +59,7 @@
#define MGBE_DMA_CHX_RDTLP(x) ((0x0080U * (x)) + 0x312CU)
#define MGBE_DMA_CHX_RX_DESC_WR_RNG_OFFSET(x) ((0x0080U * (x)) + 0x317CU)
#define MAX_REG_OFFSET 0xFFFFU
/** @} */
/** @} */

68
osi/dma/osi_dma.c
View File

@@ -195,7 +195,8 @@ static inline nve32_t dma_validate_args(const struct osi_dma_priv_data *const os
nve32_t ret = 0;
if ((osi_dma == OSI_NULL) || (osi_dma->base == OSI_NULL) ||
(l_dma->init_done == OSI_DISABLE)) {
(l_dma->init_done == OSI_DISABLE) ||
(osi_dma->mac >= OSI_MAX_MAC_IP_TYPES)) {
ret = -1;
}
@@ -487,7 +488,9 @@ done:
static inline void start_dma(const struct osi_dma_priv_data *const osi_dma, nveu32_t dma_chan)
{
const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = ((dma_chan & chan_mask[local_mac]) & (0xFFU));
const nveu32_t tx_dma_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_TX_CTRL(chan),
MGBE_DMA_CHX_TX_CTRL(chan),
@@ -501,15 +504,15 @@ static inline void start_dma(const struct osi_dma_priv_data *const osi_dma, nveu
nveu32_t val;
/* Start Tx DMA */
val = osi_dma_readl((nveu8_t *)osi_dma->base + tx_dma_reg[osi_dma->mac]);
val = osi_dma_readl((nveu8_t *)osi_dma->base + tx_dma_reg[local_mac]);
val |= OSI_BIT(0);
osi_dma_writel(val, (nveu8_t *)osi_dma->base + tx_dma_reg[osi_dma->mac]);
osi_dma_writel(val, (nveu8_t *)osi_dma->base + tx_dma_reg[local_mac]);
/* Start Rx DMA */
val = osi_dma_readl((nveu8_t *)osi_dma->base + rx_dma_reg[osi_dma->mac]);
val = osi_dma_readl((nveu8_t *)osi_dma->base + rx_dma_reg[local_mac]);
val |= OSI_BIT(0);
val &= ~OSI_BIT(31);
osi_dma_writel(val, (nveu8_t *)osi_dma->base + rx_dma_reg[osi_dma->mac]);
osi_dma_writel(val, (nveu8_t *)osi_dma->base + rx_dma_reg[local_mac]);
}
static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
@@ -518,7 +521,9 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
nveu32_t pbl = 0;
nveu32_t pdma_chan = 0xFFU;
nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = ((dma_chan & chan_mask[local_mac]) & (0xFFU));
nveu32_t riwt = osi_dma->rx_riwt & 0xFFFU;
const nveu32_t intr_en_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_INTR_ENA(chan),
@@ -704,7 +709,9 @@ exit_func:
static nve32_t init_dma(const struct osi_dma_priv_data *osi_dma, nveu32_t channel)
{
const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
nveu32_t chan = channel & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = ((channel & chan_mask[local_mac]) & (0xFFU));
nve32_t ret = 0;
/* CERT ARR-30C issue observed without this check */
@@ -820,7 +827,9 @@ static inline void stop_dma(const struct osi_dma_priv_data *const osi_dma,
nveu32_t dma_chan)
{
const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = ((dma_chan & chan_mask[local_mac]) & (0xFFU));
const nveu32_t dma_tx_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_TX_CTRL(chan),
MGBE_DMA_CHX_TX_CTRL(chan),
@@ -849,19 +858,27 @@ static inline void set_rx_riit_dma(
const struct osi_dma_priv_data *const osi_dma,
nveu32_t chan, nveu32_t riit)
{
const nveu32_t local_chan = chan % OSI_MGBE_MAX_NUM_CHANS;
const nveu32_t rx_wdt_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_RX_WDT(chan),
MGBE_DMA_CHX_RX_WDT(chan),
MGBE_DMA_CHX_RX_WDT(chan)
EQOS_DMA_CHX_RX_WDT(local_chan),
MGBE_DMA_CHX_RX_WDT(local_chan),
MGBE_DMA_CHX_RX_WDT(local_chan)
};
/* riit is in ns */
const nveu32_t itw_val = {
(((riit * ((nveu32_t)MGBE_AXI_CLK_FREQ / OSI_ONE_MEGA_HZ)) /
(MGBE_DMA_CHX_RX_WDT_ITCU * OSI_MSEC_PER_SEC))
& MGBE_DMA_CHX_RX_WDT_ITW_MAX)
};
nveu32_t itw_val = 0U;
const nveu32_t freq_mghz = (MGBE_AXI_CLK_FREQ / OSI_ONE_MEGA_HZ);
const nveu32_t wdt_msec = (MGBE_DMA_CHX_RX_WDT_ITCU * OSI_MSEC_PER_SEC);
nveu32_t val;
if (riit > (UINT_MAX / freq_mghz)) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"Invalid riit received\n", riit);
goto exit_func;
}
itw_val = (((riit * freq_mghz) / wdt_msec)
& MGBE_DMA_CHX_RX_WDT_ITW_MAX);
if (osi_dma->use_riit != OSI_DISABLE &&
osi_dma->mac == OSI_MAC_HW_MGBE_T26X) {
val = osi_dma_readl((nveu8_t *)osi_dma->base +
@@ -872,6 +889,7 @@ static inline void set_rx_riit_dma(
rx_wdt_reg[osi_dma->mac]);
}
exit_func:
return;
}
@@ -957,13 +975,15 @@ nve32_t osi_get_global_dma_status(struct osi_dma_priv_data *osi_dma,
{
const nveu32_t global_dma_status_reg_cnt[OSI_MAX_MAC_IP_TYPES] = {1, 1, 3};
struct dma_local *l_dma = (struct dma_local *)(void *)osi_dma;
const nveu32_t global_dma_status_reg[OSI_MAX_MAC_IP_TYPES] = {
nveu32_t global_dma_status_reg[OSI_MAX_MAC_IP_TYPES] = {
HW_GLOBAL_DMA_STATUS,
HW_GLOBAL_DMA_STATUS,
MGBE_T26X_GLOBAL_DMA_STATUS,
};
nve32_t ret = 0;
nveu32_t i;
nveu64_t temp_addr = 0U;
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
#ifdef OSI_CL_FTRACE
if ((osi_get_global_dma_status_cnt % 1000) == 0)
@@ -974,10 +994,14 @@ nve32_t osi_get_global_dma_status(struct osi_dma_priv_data *osi_dma,
goto fail;
}
for (i = 0U; i < global_dma_status_reg_cnt[osi_dma->mac]; i++) {
for (i = 0U; i < global_dma_status_reg_cnt[local_mac]; i++) {
if (i < UINT_MAX) {
// Added check to avoid CERT INT30-C
global_dma_status_reg[local_mac] &= MAX_REG_OFFSET;
temp_addr = (nveu64_t)(global_dma_status_reg[local_mac] +
((nveu64_t)i * 4U));
dma_status[i] = osi_dma_readl((nveu8_t *)osi_dma->base +
(global_dma_status_reg[osi_dma->mac] + (i * 4U)));
(nveu32_t)(temp_addr & (nveu64_t)MAX_REG_OFFSET));
}
}
fail:
@@ -1400,7 +1424,7 @@ fail:
nve32_t osi_dma_ioctl(struct osi_dma_priv_data *osi_dma)
{
struct dma_local *l_dma = (struct dma_local *)osi_dma;
struct dma_local *l_dma = (struct dma_local *)(void *)osi_dma;
struct osi_dma_ioctl_data *data;
#ifdef OSI_CL_FTRACE
@@ -1485,7 +1509,7 @@ static inline nve32_t osi_slot_args_validate(struct osi_dma_priv_data *osi_dma,
nve32_t osi_config_slot_function(struct osi_dma_priv_data *osi_dma,
nveu32_t set)
{
struct dma_local *l_dma = (struct dma_local *)osi_dma;
struct dma_local *l_dma = (struct dma_local *)(void *)osi_dma;
nveu32_t i = 0U, chan = 0U, interval = 0U;
struct osi_tx_ring *tx_ring = OSI_NULL;

59
osi/dma/osi_dma_txrx.c
View File

@@ -79,7 +79,8 @@ static inline nve32_t validate_rx_completions_arg(
if (osi_unlikely((osi_dma == OSI_NULL) ||
(more_data_avail == OSI_NULL) ||
(chan >= l_dma->num_max_chans))) {
(chan >= l_dma->num_max_chans) ||
(chan >= OSI_MGBE_MAX_NUM_CHANS))) {
ret = -1;
goto fail;
}
@@ -178,6 +179,9 @@ static inline void check_for_more_data_avail(struct osi_rx_ring *rx_ring, nve32_
* Rx packets, so that the OSD layer can decide to schedule
* this function again.
*/
if ((received_resv < 0) || (received > (INT_MAX - received_resv))) {
return;
}
if ((received + received_resv) >= budget) {
rx_desc = rx_ring->rx_desc + rx_ring->cur_rx_idx;
rx_swcx = rx_ring->rx_swcx + rx_ring->cur_rx_idx;
@@ -218,17 +222,26 @@ static inline nveu32_t compltd_rx_desc_cnt(struct osi_dma_priv_data *osi_dma,
nveu32_t chan)
{
struct osi_rx_ring *rx_ring = osi_dma->rx_ring[chan];
nveu32_t value, rx_desc_wr_idx, descr_compltd;
nveu32_t value = 0U , rx_desc_wr_idx = 0U, descr_compltd = 0U;
/* Already has a check for this in teh caller
* but coverity tool is not able recognize the same
*/
const nveu32_t local_chan = chan % OSI_MGBE_MAX_NUM_CHANS;
value = osi_dma_readl((nveu8_t *)osi_dma->base +
MGBE_DMA_CHX_RX_DESC_WR_RNG_OFFSET(chan));
/* completed desc write back offset */
rx_desc_wr_idx = ((value >> MGBE_RX_DESC_WR_RNG_RWDC_SHIFT ) &
(osi_dma->rx_ring_sz - 1));
descr_compltd = (rx_desc_wr_idx - rx_ring->cur_rx_idx) &
(osi_dma->rx_ring_sz - 1U);
MGBE_DMA_CHX_RX_DESC_WR_RNG_OFFSET(local_chan));
if (osi_dma->rx_ring_sz > 0U) {
/* completed desc write back offset */
rx_desc_wr_idx = ((value >> MGBE_RX_DESC_WR_RNG_RWDC_SHIFT ) &
(osi_dma->rx_ring_sz - 1U));
//If we remove this check we are seeing perf issues on mgbe3_0 of Ferrix
// if (rx_desc_wr_idx >= rx_ring->cur_rx_idx) {
descr_compltd = (rx_desc_wr_idx - rx_ring->cur_rx_idx) &
(osi_dma->rx_ring_sz - 1U);
// }
}
/* offset/index start from 0, so add 1 to get final count */
descr_compltd += 1U;
descr_compltd = (((descr_compltd) & ((nveu32_t)0x7FFFFFFFU)) + (1U));
return descr_compltd;
}
@@ -1135,7 +1148,7 @@ static inline void apply_write_barrier(struct osi_tx_ring *tx_ring)
static inline void dump_tx_descriptors(struct osi_dma_priv_data *osi_dma,
nveu32_t f_idx, nveu32_t l_idx, nveu32_t chan)
{
if (osi_dma->enable_desc_dump == 1U) {
if ((osi_dma->enable_desc_dump == 1U) && (l_idx != 0U)) {
desc_dump(osi_dma, f_idx, DECR_TX_DESC_INDEX(l_idx, osi_dma->tx_ring_sz),
(TX_DESC_DUMP | TX_DESC_DUMP_TX), chan);
}
@@ -1205,7 +1218,9 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
#ifdef OSI_DEBUG
nveu32_t f_idx = tx_ring->cur_tx_idx;
#endif /* OSI_DEBUG */
nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = ((dma_chan & chan_mask[local_mac]) & (0xFFU));
const nveu32_t tail_ptr_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_TDTP(chan),
MGBE_DMA_CHX_TDTLP(chan),
@@ -1299,6 +1314,12 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
/* Fill remaining descriptors */
for (i = 0; i < desc_cnt; i++) {
/* Increase the desc count for first descriptor */
if (tx_ring->desc_cnt == UINT_MAX) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"dma_txrx: Reached Max Desc count\n", 0ULL);
ret = -1;
break;
}
tx_ring->desc_cnt++;
tx_desc->tdes0 = L32(tx_swcx->buf_phy_addr);
@@ -1314,6 +1335,12 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
tx_swcx = tx_ring->tx_swcx + entry;
}
if (tx_ring->desc_cnt == UINT_MAX) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"dma_txrx: Reached Max Desc count\n", 0ULL);
ret = -1;
goto fail;
}
/* Mark it as LAST descriptor */
last_desc->tdes3 |= TDES3_LD;
@@ -1356,7 +1383,7 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
tx_ring->cur_tx_idx = entry;
/* Update the Tx tail pointer */
osi_dma_writel(L32(tailptr), (nveu8_t *)osi_dma->base + tail_ptr_reg[osi_dma->mac]);
osi_dma_writel(L32(tailptr), (nveu8_t *)osi_dma->base + tail_ptr_reg[local_mac]);
fail:
return ret;
@@ -1387,7 +1414,9 @@ static nve32_t rx_dma_desc_initialization(const struct osi_dma_priv_data *const
nveu32_t dma_chan)
{
const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = ((dma_chan & chan_mask[local_mac]) & (0xFFU));
const nveu32_t start_addr_high_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_RDLH(chan),
MGBE_DMA_CHX_RDLH(chan),
@@ -1533,7 +1562,9 @@ static inline void set_tx_ring_len_and_start_addr(const struct osi_dma_priv_data
nveu32_t len)
{
const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
const nveu32_t local_mac = osi_dma->mac % OSI_MAX_MAC_IP_TYPES;
// Added bitwise with 0xFF to avoid CERT INT30-C error
nveu32_t chan = ((dma_chan & chan_mask[local_mac]) & (0xFFU));
const nveu32_t ring_len_reg[OSI_MAX_MAC_IP_TYPES] = {
EQOS_DMA_CHX_TDRL(chan),
MGBE_DMA_CHX_TX_CNTRL2(chan),