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osi: core: Add OSI_CMD_READ_HSI_ERR command

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Issue:
Observed HSI diagnostic timer execution is taking
more than MAX_PROC_TIME due to OSI_CMD_READ_MMC
execution time. As this is reading 151 MMC
registers for MGBE and 91 registers for EQOS.

Fix:
As this OSI_CMD_READ_MMC command execution is not
meeting the MAX_PROC_TIME, add new OSI_CMD_READ_HSI_ERR
command only to read 5 MMC error registers.

Bug 4069585

Change-Id: I38a10b7f09ac7614d548b5caa4203f1c94889908
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2895845
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Mohan Thadikamalla
2023-04-28 15:39:47 +05:30
committed by mobile promotions
parent c6382f708e
commit 163e9cf67c
4 changed files with 112 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
include/osi_core.h
View File

@@ -271,8 +271,11 @@ typedef my_lint_64 nvel64_t;
#define OSI_CMD_RESUME 54U
#ifdef HSI_SUPPORT
#define OSI_CMD_HSI_INJECT_ERR 55U
#endif
#endif /* HSI_SUPPORT */
#define OSI_CMD_READ_STATS 56U
#ifdef HSI_SUPPORT
#define OSI_CMD_READ_HSI_ERR 57U
#endif /* HSI_SUPPORT */
/** @} */
#ifdef LOG_OSI

82
osi/core/core_common.c
View File

@@ -1571,7 +1571,87 @@ nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
return ret;
}
#endif
/**
* @brief hsi_update_mmc_val - function to read register and return value to callee
*
* Algorithm: Read the registers, check for boundary, if more, reset
* counters else return same to caller.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] last_value: previous value of stats variable.
* @param[in] offset: HW register offset
*
* @note
* 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated
*
* @retval 0 on MMC counters overflow
* @retval value on current MMC counter value.
*/
static inline nveu64_t hsi_update_mmc_val(struct osi_core_priv_data *osi_core,
nveu64_t last_value,
nveu64_t offset)
{
nveu64_t temp = 0;
nveu32_t value = osi_readl((nveu8_t *)osi_core->base + offset);
const nveu32_t MMC_CNTRL[MAX_MAC_IP_TYPES] = { EQOS_MMC_CNTRL, MGBE_MMC_CNTRL };
const nveu32_t MMC_CNTRL_CNTRST[MAX_MAC_IP_TYPES] = { EQOS_MMC_CNTRL_CNTRST,
MGBE_MMC_CNTRL_CNTRST };
temp = last_value + value;
if (temp < last_value) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_OUTOFBOUND,
"Value overflow resetting all counters\n", (nveul64_t)offset);
value = osi_readl((nveu8_t *)osi_core->base + MMC_CNTRL[osi_core->mac]);
/* self-clear bit in one clock cycle */
value |= MMC_CNTRL_CNTRST[osi_core->mac];
osi_writel(value, (nveu8_t *)osi_core->base + MMC_CNTRL[osi_core->mac]);
osi_memset(&osi_core->mmc, 0U, sizeof(struct osi_mmc_counters));
}
return temp;
}
/**
* @brief hsi_read_err - To read MMC error registers and update
* ether_mmc_counter structure variable
*
* Algorithm: Pass register offset and old value to helper function and
* update structure.
*
* @param[in] osi_core: OSI core private data structure.
*
* @note
* 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated
*/
void hsi_read_err(struct osi_core_priv_data *const osi_core)
{
struct osi_mmc_counters *mmc = &osi_core->mmc;
const nveu32_t RXCRCERROR[MAX_MAC_IP_TYPES] = { EQOS_MMC_RXCRCERROR,
MGBE_MMC_RXCRCERROR_L };
const nveu32_t RXIPV4_HDRERR_PKTS[MAX_MAC_IP_TYPES] = { EQOS_MMC_RXIPV4_HDRERR_PKTS,
MGBE_MMC_RXIPV4_HDRERR_PKTS_L };
const nveu32_t RXIPV6_HDRERR_PKTS[MAX_MAC_IP_TYPES] = { EQOS_MMC_RXIPV6_HDRERR_PKTS,
MGBE_MMC_RXIPV6_HDRERR_PKTS_L };
const nveu32_t RXUDP_ERR_PKTS[MAX_MAC_IP_TYPES] = { EQOS_MMC_RXUDP_ERR_PKTS,
MGBE_MMC_RXUDP_ERR_PKTS_L };
const nveu32_t RXTCP_ERR_PKTS[MAX_MAC_IP_TYPES] = { EQOS_MMC_RXTCP_ERR_PKTS,
MGBE_MMC_RXTCP_ERR_PKTS_L };
mmc->mmc_rx_crc_error = hsi_update_mmc_val(osi_core, mmc->mmc_rx_crc_error,
RXCRCERROR[osi_core->mac]);
mmc->mmc_rx_ipv4_hderr = hsi_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr,
RXIPV4_HDRERR_PKTS[osi_core->mac]);
mmc->mmc_rx_ipv6_hderr = hsi_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr,
RXIPV6_HDRERR_PKTS[osi_core->mac]);
mmc->mmc_rx_udp_err = hsi_update_mmc_val(osi_core, mmc->mmc_rx_udp_err,
RXUDP_ERR_PKTS[osi_core->mac]);
mmc->mmc_rx_tcp_err = hsi_update_mmc_val(osi_core, mmc->mmc_rx_tcp_err,
RXTCP_ERR_PKTS[osi_core->mac]);
}
#endif /* HSI_SUPPORT */
/**
* @brief prepare_l3l4_ctr_reg - Prepare control register for L3L4 filters.

22
osi/core/core_common.h
View File

@@ -119,6 +119,27 @@
#define EQOS_MAC_L3L4_CTR_DMCHEN_SHIFT 28
#define MGBE_MAC_L3L4_CTR_DMCHEN_SHIFT 31
#ifdef HSI_SUPPORT
/**
* @addtogroup MMC HW register offsets
*
* @brief MMC HW register offsets
* @{
*/
#define EQOS_MMC_RXCRCERROR 0x00794
#define EQOS_MMC_RXIPV4_HDRERR_PKTS 0x00814
#define EQOS_MMC_RXIPV6_HDRERR_PKTS 0x00828
#define EQOS_MMC_RXUDP_ERR_PKTS 0x00834
#define EQOS_MMC_RXTCP_ERR_PKTS 0x0083c
#define MGBE_MMC_RXCRCERROR_L 0x00928
#define MGBE_MMC_RXIPV4_HDRERR_PKTS_L 0x00A6C
#define MGBE_MMC_RXIPV6_HDRERR_PKTS_L 0x00A94
#define MGBE_MMC_RXUDP_ERR_PKTS_L 0x00AAC
#define MGBE_MMC_RXTCP_ERR_PKTS_L 0x00ABC
/** @} */
#endif /* HSI_SUPPORT */
/**
* @addtogroup typedef related info
*
@@ -179,6 +200,7 @@ void prepare_l3l4_registers(const struct osi_core_priv_data *const osi_core,
#ifdef HSI_SUPPORT
nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
nveu32_t error_code);
void hsi_read_err(struct osi_core_priv_data *const osi_core);
#endif
nve32_t hw_validate_avb_input(struct osi_core_priv_data *const osi_core,
const struct osi_core_avb_algorithm *const avb);

6
osi/core/osi_hal.c
View File

@@ -2971,7 +2971,11 @@ static nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core,
case OSI_CMD_HSI_INJECT_ERR:
ret = ops_p->core_hsi_inject_err(osi_core, data->arg1_u32);
break;
#endif
case OSI_CMD_READ_HSI_ERR:
hsi_read_err(osi_core);
ret = 0;
break;
#endif /* HSI_SUPPORT */
#ifdef OSI_DEBUG
case OSI_CMD_DEBUG_INTR_CONFIG: