diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index 84dcd12..8452b26 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -2384,7 +2384,10 @@ static nve32_t mgbe_configure_mac(struct osi_core_priv_data *osi_core)
 	/* RGSMIIIM - RGMII/SMII interrupt and TSIE Enable */
 	/* TXESIE - Transmit Error Status Interrupt Enable */
 	/* TODO: LPI need to be enabled during EEE implementation */
-	value |= (MGBE_IMR_RGSMIIIE | MGBE_IMR_TSIE | MGBE_IMR_TXESIE);
+#ifndef OSI_STRIPPED_LIB
+	value |= (MGBE_IMR_TXESIE);
+#endif
+	value |= (MGBE_IMR_RGSMIIIE | MGBE_IMR_TSIE);
 	osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MAC_IER);
 
 	/* Enable common interrupt at wrapper level */
diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h
index 15fd39e..7514722 100644
--- a/osi/core/mgbe_core.h
+++ b/osi/core/mgbe_core.h
@@ -165,6 +165,7 @@
 #define MGBE_MTL_RXP_BYPASS_CNT			2U
 #define MGBE_MAC_FPE_CTS_SVER			OSI_BIT(1)
 
+#define MGBE_IMR_TXESIE				OSI_BIT(13)
 #endif /* !OSI_STRIPPED_LIB */
 
 #define MGBE_MTL_EST_CONTROL			0x1050
@@ -556,7 +557,6 @@
 #define MGBE_MAC_RQC1R_MCBCQ_SHIFT		8U
 #define MGBE_IMR_RGSMIIIE			OSI_BIT(0)
 #define MGBE_IMR_TSIE				OSI_BIT(12)
-#define MGBE_IMR_TXESIE				OSI_BIT(13)
 #define MGBE_ISR_TSIS				OSI_BIT(12)
 #define MGBE_DMA_ISR_MACIS                      OSI_BIT(17)
 #define MGBE_DMA_ISR_DCH0_DCH15_MASK		0x3FFU