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core: update code for TSN

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- Update CTOV recommended value
- Update PTOV recommended value
- Disable PEC filed on preemption disable
- Disable EEST with message to reprogram
  GCL instead of dropping packet on HLBF/HLBS
- Configure code not to drop any packet silently
  on HLBF and HLBS error
- Q2TC mapping with CBS enable

Bug 200763256
Bug 200765943

Change-Id: I7a2581af488e22a23d32ce1819440c21f4748800
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2593162
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Rakesh Goyal
2021-09-12 20:25:33 +05:30
committed by mobile promotions
parent fc9e41ca31
commit 2200f3d921
4 changed files with 107 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

74
osi/core/eqos_core.c
View File

@@ -1935,25 +1935,24 @@ static void eqos_tsn_init(struct osi_core_priv_data *osi_core,
/* 6*1/(78.6 MHz) in ns*/
temp = (6U * 13U);
} else {
/* 6*1/(312 MHz) in ns*/
temp = (6U * 3U);
temp = EQOS_MTL_EST_PTOV_RECOMMEND;
}
temp = temp << EQOS_MTL_EST_CONTROL_PTOV_SHIFT;
val |= temp;
/* We have a bug on CTOV for Qbv that synopsys is yet to
* fix[Case – 8001147927, Bug 200468714]. You can go ahead
* with 128*8ns for now. TODO */
val &= ~EQOS_MTL_EST_CONTROL_CTOV;
temp = (128U * 8U);
temp = EQOS_MTL_EST_CTOV_RECOMMEND;
temp = temp << EQOS_MTL_EST_CONTROL_CTOV_SHIFT;
val |= temp;
/*Loop Count to report Scheduling Error*/
val &= ~EQOS_MTL_EST_CONTROL_LCSE;
val |= EQOS_MTL_EST_CONTROL_LCSE_VAL;
/* Drop Frames causing Scheduling Error */
val |= EQOS_MTL_EST_CONTROL_DFBS;
val &= ~(EQOS_MTL_EST_CONTROL_DDBF |
EQOS_MTL_EST_CONTROL_DFBS);
val |= EQOS_MTL_EST_CONTROL_DDBF;
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
EQOS_MTL_EST_CONTROL);
@@ -2400,12 +2399,13 @@ static inline void update_dma_sr_stats(
*/
static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
{
unsigned int val = 0;
unsigned int sch_err = 0;
unsigned int frm_err = 0;
unsigned int val = 0U;
unsigned int sch_err = 0U;
unsigned int frm_err = 0U;
unsigned int temp = 0U;
unsigned int i = 0;
unsigned long stat_val = 0;
unsigned long stat_val = 0U;
unsigned int value = 0U;
val = osi_readla(osi_core,
(unsigned char *)osi_core->base + EQOS_MTL_EST_STATUS);
@@ -2446,6 +2446,18 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
sch_err &= 0xFFU; /* only 8 TC allowed so clearing all */
osi_writela(osi_core, sch_err,
(nveu8_t *)osi_core->base + EQOS_MTL_EST_SCH_ERR);
/* Disable est as error happen */
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MTL_EST_CONTROL);
/* DBFS 0 means do not packet */
if ((value & EQOS_MTL_EST_CONTROL_DFBS) == OSI_DISABLE) {
value &= ~EQOS_MTL_EST_CONTROL_EEST;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MTL_EST_CONTROL);
OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID,
"Disabling EST due to HLBS, correct GCL\n",
OSI_NONE);
}
}
if ((val & EQOS_MTL_EST_STATUS_HLBF) == EQOS_MTL_EST_STATUS_HLBF) {
@@ -2468,6 +2480,19 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
frm_err &= 0xFFU; /* 8 TC allowed so clearing all */
osi_writela(osi_core, frm_err, (nveu8_t *)osi_core->base +
EQOS_MTL_EST_FRMS_ERR);
/* Disable est as error happen */
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MTL_EST_CONTROL);
/* DDBF 1 means don't drop packet */
if ((value & EQOS_MTL_EST_CONTROL_DDBF) ==
EQOS_MTL_EST_CONTROL_DDBF) {
value &= ~EQOS_MTL_EST_CONTROL_EEST;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MTL_EST_CONTROL);
OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID,
"Disabling EST due to HLBF, correct GCL\n",
OSI_NONE);
}
}
if ((val & EQOS_MTL_EST_STATUS_SWLC) == EQOS_MTL_EST_STATUS_SWLC) {
@@ -4675,24 +4700,26 @@ static int eqos_hw_config_fpe(struct osi_core_priv_data *osi_core,
osi_core->fpe_ready = OSI_DISABLE;
val = osi_readla(osi_core,
(unsigned char *)osi_core->base + EQOS_MTL_FPE_CTS);
if (((fpe->tx_queue_preemption_enable << EQOS_MTL_FPE_CTS_PEC_SHIFT) &
EQOS_MTL_FPE_CTS_PEC) == OSI_DISABLE) {
val &= ~EQOS_MAC_FPE_CTS_EFPE;
osi_writela(osi_core, val, (unsigned char *)osi_core->base +
EQOS_MAC_FPE_CTS);
val = osi_readla(osi_core,
(nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS);
val &= ~EQOS_MTL_FPE_CTS_PEC;
osi_writela(osi_core, val,
(nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS);
val = osi_readla(osi_core, (unsigned char *)osi_core->base +
EQOS_MAC_RQC1R);
val &= ~EQOS_MAC_RQC1R_FPRQ;
osi_writela(osi_core, val, (unsigned char *)osi_core->base +
EQOS_MAC_RQC1R);
val = osi_readla(osi_core,
(nveu8_t *)osi_core->base + EQOS_MAC_FPE_CTS);
val &= ~EQOS_MAC_FPE_CTS_EFPE;
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
EQOS_MAC_FPE_CTS);
return 0;
}
val = osi_readla(osi_core,
(nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS);
val &= ~EQOS_MTL_FPE_CTS_PEC;
for (i = 0U; i < OSI_MAX_TC_NUM; i++) {
/* max 8 bit for this structure fot TC/TXQ. Set the TC for express or
@@ -4712,7 +4739,7 @@ static int eqos_hw_config_fpe(struct osi_core_priv_data *osi_core,
}
}
osi_writela(osi_core, val,
(unsigned char *)osi_core->base + EQOS_MTL_FPE_CTS);
(nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS);
/* Setting RQ as RxQ 0 is not allowed */
if (fpe->rq == 0x0U || fpe->rq >= OSI_EQOS_MAX_NUM_CHANS) {
@@ -5330,6 +5357,7 @@ static nve32_t eqos_set_avb_algorithm(
EQOS_MTL_CH0_TX_OP_MODE_IDX + qinx);
/* Set Algo and Credit control */
value = OSI_DISABLE;
if (avb->algo == OSI_MTL_TXQ_AVALG_CBS) {
value = (avb->credit_control << EQOS_MTL_TXQ_ETS_CR_CC_SHIFT) &
EQOS_MTL_TXQ_ETS_CR_CC;

2
osi/core/eqos_core.h
View File

@@ -538,6 +538,7 @@
OSI_BIT(28) | OSI_BIT(29) | \
OSI_BIT(30) | OSI_BIT(31))
#define EQOS_MTL_EST_CONTROL_PTOV_SHIFT 24U
#define EQOS_MTL_EST_PTOV_RECOMMEND 32U
#define EQOS_MTL_EST_CONTROL_CTOV (OSI_BIT(12) | OSI_BIT(13) | \
OSI_BIT(14) | OSI_BIT(15) | \
OSI_BIT(16) | OSI_BIT(17) | \
@@ -545,6 +546,7 @@
OSI_BIT(20) | OSI_BIT(21) | \
OSI_BIT(22) | OSI_BIT(23))
#define EQOS_MTL_EST_CONTROL_CTOV_SHIFT 12U
#define EQOS_MTL_EST_CTOV_RECOMMEND 94U
#define EQOS_MTL_EST_CONTROL_TILS (OSI_BIT(8) | OSI_BIT(9) | \
OSI_BIT(10))
#define EQOS_MTL_EST_CONTROL_LCSE (OSI_BIT(6) | OSI_BIT(5))

71
osi/core/mgbe_core.c
View File

@@ -2927,23 +2927,22 @@ static void mgbe_tsn_init(struct osi_core_priv_data *osi_core,
/* 6*1/(78.6 MHz) in ns*/
temp = (6U * 13U);
} else {
/* 6*1/(312 MHz) in ns*/
temp = (6U * 3U);
temp = MGBE_MTL_EST_PTOV_RECOMMEND;
}
temp = temp << MGBE_MTL_EST_CONTROL_PTOV_SHIFT;
val |= temp;
/* We have a bug on CTOV for Qbv that synopsys is yet to
* fix[Case – 8001147927, Bug 200468714]. You can go ahead
* with 128*8ns for now. TODO */
val &= ~MGBE_MTL_EST_CONTROL_CTOV;
temp = (128U * 8U);
temp = MGBE_MTL_EST_CTOV_RECOMMEND;
temp = temp << MGBE_MTL_EST_CONTROL_CTOV_SHIFT;
val |= temp;
/*Loop Count to report Scheduling Error*/
val &= ~MGBE_MTL_EST_CONTROL_LCSE;
val |= MGBE_MTL_EST_CONTROL_LCSE_VAL;
val &= ~MGBE_MTL_EST_CONTROL_DDBF;
val |= MGBE_MTL_EST_CONTROL_DDBF;
osi_writela(osi_core, val, (unsigned char *)osi_core->base +
MGBE_MTL_EST_CONTROL);
@@ -2951,7 +2950,7 @@ static void mgbe_tsn_init(struct osi_core_priv_data *osi_core,
MGBE_MTL_EST_OVERHEAD);
val &= ~MGBE_MTL_EST_OVERHEAD_OVHD;
/* As per hardware programming info */
val |= OVHD_MGBE_MAC;
val |= MGBE_MTL_EST_OVERHEAD_RECOMMEND;
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
MGBE_MTL_EST_OVERHEAD);
@@ -3449,6 +3448,7 @@ static int mgbe_set_avb_algorithm(
value |= ((avb->oper_mode << MGBE_MTL_TX_OP_MODE_TXQEN_SHIFT) &
MGBE_MTL_TX_OP_MODE_TXQEN);
/* Set TC mapping */
value &= ~MGBE_MTL_TX_OP_MODE_Q2TCMAP;
value |= ((tcinx << MGBE_MTL_TX_OP_MODE_Q2TCMAP_SHIFT) &
MGBE_MTL_TX_OP_MODE_Q2TCMAP);
osi_writela(osi_core, value, (unsigned char *)osi_core->base +
@@ -3612,12 +3612,13 @@ static int mgbe_get_avb_algorithm(struct osi_core_priv_data *const osi_core,
*/
static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
{
unsigned int val = 0;
unsigned int sch_err = 0;
unsigned int frm_err = 0;
unsigned int val = 0U;
unsigned int sch_err = 0U;
unsigned int frm_err = 0U;
unsigned int temp = 0U;
unsigned int i = 0;
unsigned long stat_val = 0;
unsigned long stat_val = 0U;
unsigned int value = 0U;
val = osi_readla(osi_core,
(nveu8_t *)osi_core->base + MGBE_MTL_EST_STATUS);
@@ -3658,6 +3659,14 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
sch_err &= 0xFFU; //only 8 TC allowed so clearing all
osi_writela(osi_core, sch_err, (nveu8_t *)osi_core->base +
MGBE_MTL_EST_SCH_ERR);
/* Reset EST with print to configure it properly */
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MTL_EST_CONTROL);
value &= ~MGBE_MTL_EST_EEST;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
MGBE_MTL_EST_CONTROL);
OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID,
"Disabling EST due to HLBS, correct GCL\n", OSI_NONE);
}
if ((val & MGBE_MTL_EST_STATUS_HLBF) == MGBE_MTL_EST_STATUS_HLBF) {
@@ -3680,6 +3689,20 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
frm_err &= 0xFFU; //only 8 TC allowed so clearing all
osi_writela(osi_core, frm_err, (nveu8_t *)osi_core->base +
MGBE_MTL_EST_FRMS_ERR);
/* Reset EST with print to configure it properly */
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MTL_EST_CONTROL);
/* DDBF 1 means don't drop packets */
if ((value & MGBE_MTL_EST_CONTROL_DDBF) ==
MGBE_MTL_EST_CONTROL_DDBF) {
value &= ~MGBE_MTL_EST_EEST;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
MGBE_MTL_EST_CONTROL);
OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID,
"Disabling EST due to HLBF, correct GCL\n",
OSI_NONE);
}
}
if ((val & MGBE_MTL_EST_STATUS_SWLC) == MGBE_MTL_EST_STATUS_SWLC) {
@@ -4698,23 +4721,25 @@ static int mgbe_hw_config_fpe(struct osi_core_priv_data *osi_core,
osi_core->fpe_ready = OSI_DISABLE;
val = osi_readla(osi_core, (unsigned char *)
osi_core->base + MGBE_MTL_FPE_CTS);
if (((fpe->tx_queue_preemption_enable << MGBE_MTL_FPE_CTS_PEC_SHIFT) &
MGBE_MTL_FPE_CTS_PEC) == OSI_DISABLE) {
val &= ~MGBE_MAC_FPE_CTS_EFPE;
osi_writela(osi_core, val, (unsigned char *)osi_core->base +
MGBE_MAC_FPE_CTS);
val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MTL_FPE_CTS);
val &= ~MGBE_MTL_FPE_CTS_PEC;
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
MGBE_MTL_FPE_CTS);
val = osi_readla(osi_core, (unsigned char *)osi_core->base +
MGBE_MAC_RQC1R);
val &= ~MGBE_MAC_RQC1R_RQ;
osi_writela(osi_core, val, (unsigned char *)osi_core->base +
MGBE_MAC_RQC1R);
val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MAC_FPE_CTS);
val &= ~MGBE_MAC_FPE_CTS_EFPE;
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
MGBE_MAC_FPE_CTS);
return 0;
}
val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MTL_FPE_CTS);
val &= ~MGBE_MTL_FPE_CTS_PEC;
for (i = 0U; i < OSI_MAX_TC_NUM; i++) {
/* max 8 bit for this structure fot TC/TXQ. Set the TC for express or
@@ -4733,8 +4758,8 @@ static int mgbe_hw_config_fpe(struct osi_core_priv_data *osi_core,
}
}
}
osi_writela(osi_core, val, (unsigned char *)
osi_core->base + MGBE_MTL_FPE_CTS);
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
MGBE_MTL_FPE_CTS);
if (fpe->rq == 0x0U || fpe->rq >= OSI_MGBE_MAX_NUM_CHANS) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,

11
osi/core/mgbe_core.h
View File

@@ -609,6 +609,7 @@
OSI_BIT(29) | OSI_BIT(30) | \
OSI_BIT(31))
#define MGBE_MTL_EST_CONTROL_PTOV_SHIFT 23U
#define MGBE_MTL_EST_PTOV_RECOMMEND 32U
#define MGBE_MTL_EST_CONTROL_CTOV (OSI_BIT(11) | OSI_BIT(12) | \
OSI_BIT(13) | OSI_BIT(14) | \
OSI_BIT(15) | OSI_BIT(16) | \
@@ -616,6 +617,7 @@
OSI_BIT(19) | OSI_BIT(20) | \
OSI_BIT(21) | OSI_BIT(22))
#define MGBE_MTL_EST_CONTROL_CTOV_SHIFT 11U
#define MGBE_MTL_EST_CTOV_RECOMMEND 42U
#define MGBE_MTL_EST_CONTROL_TILS (OSI_BIT(8) | OSI_BIT(9) | \
OSI_BIT(10))
#define MGBE_MTL_EST_CONTROL_LCSE (OSI_BIT(7) | OSI_BIT(6))
@@ -627,6 +629,7 @@
#define MGBE_MTL_EST_OVERHEAD_OVHD (OSI_BIT(0) | OSI_BIT(1) | \
OSI_BIT(2) | OSI_BIT(3) | \
OSI_BIT(4) | OSI_BIT(5))
#define MGBE_MTL_EST_OVERHEAD_RECOMMEND 56U
/* EST controlOSI_BITmap */
#define MGBE_MTL_EST_EEST OSI_BIT(0)
#define MGBE_MTL_EST_SSWL OSI_BIT(1)
@@ -853,14 +856,6 @@
OSI_MGBE_MAX_MAC_ADDRESS_FILTER + 1U))
/** @} */
/**
* @addtogroup IPG over head
*
* @brief OVHD value for MGBE MAC
* @{
*/
#define OVHD_MGBE_MAC 56U
/**
* @addtogroup MGBE-MAC MGBE MAC HW feature registers
*