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osi: create stripped library for MCAL/QNX

Browse Source 
Update common library to export only API
used in QNX/MCAL driver if OSI_STRIPPED_LIB
is defined.

Bug 200671362

Change-Id: Ide3a5d9a60228b5d07355b58e26f509245db4144
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2410877
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2422285
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
rakesh goyal
2020-09-09 15:29:22 +05:30
committed by Bhadram Varka
parent ae58a6993c
commit 228703f6cf
12 changed files with 1591 additions and 1628 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
include/osi_common.h
View File

@@ -125,7 +125,7 @@
/**
* @addtogroup EQOS_PTP PTP Helper MACROS
*
* @brief EQOS PTP MAC Time stamp contorl reg bit fields
* @brief EQOS PTP MAC Time stamp control reg bit fields
* @{
*/
#define OSI_MAC_TCR_TSENA OSI_BIT(0)
@@ -200,7 +200,7 @@
OSI_LOG_WARN, type, err, loga); \
}
/* Default maximum Gaint Packet Size Limit is 16K */
/* Default maximum Giant Packet Size Limit is 16K */
#define OSI_MAX_MTU_SIZE 16383U
#define OSI_MTU_SIZE_9000 9000U
#define OSI_DFLT_MTU_SIZE 1500U
@@ -609,7 +609,7 @@ struct osi_hw_features {
* feature */
unsigned int auto_safety_pkg;
/** Tx Timestamp FIFO Depth
* This value indicates the depth of the Tx Timetamp FIFO
* This value indicates the depth of the Tx Timestamp FIFO
* 3'b000: Reserved
* 3'b001: 1
* 3'b010: 2
@@ -746,7 +746,7 @@ static inline void osi_unlock_irq_enabled(unsigned int *lock)
*
* @param[in] addr: Memory mapped address.
*
* @pre Physical address has to be memmory mapped.
* @pre Physical address has to be memory mapped.
*
* @return Data from memory mapped register - success.
*/
@@ -761,7 +761,7 @@ static inline unsigned int osi_readl(void *addr)
* @param[in] val: Value to be written.
* @param[in] addr: Memory mapped address.
*
* @pre Physical address has to be memmory mapped.
* @pre Physical address has to be memory mapped.
*/
static inline void osi_writel(unsigned int val, void *addr)
{
@@ -831,7 +831,7 @@ static inline unsigned long osi_update_stats_counter(unsigned long last_value,
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETRM_020
* - SWUD_ID: ETHERNET_NVETHERNETRM_015
*
* @note
* Classification:
@@ -861,7 +861,7 @@ int osi_get_mac_version(void *addr, unsigned int *mac_ver);
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETRM_021
* - SWUD_ID: ETHERNET_NVETHERNETRM_016
*
* @note
* Classification:

1019
include/osi_core.h
View File

File diff suppressed because it is too large Load Diff

278
include/osi_dma.h
View File

@@ -73,8 +73,8 @@
* @addtogroup EQOS-TX Tx done packet context fields
*
* @brief These flags used to convey transmit done packet context information,
* whether transmitted packet used a pagged buffer, whether transmitted packet
* has an tx error, whether tranmitted packet has an TS
* whether transmitted packet used a paged buffer, whether transmitted packet
* has an tx error, whether transmitted packet has an TS
*
* @{
*/
@@ -360,6 +360,7 @@ struct osi_dma_chan_ops {
void (*init_dma_channel) (struct osi_dma_priv_data *osi_dma);
/** Called to set Rx buffer length */
void (*set_rx_buf_len)(struct osi_dma_priv_data *osi_dma);
#ifndef OSI_STRIPPED_LIB
/** Called periodically to read and validate safety critical
* registers against last written value */
int (*validate_regs)(struct osi_dma_priv_data *osi_dma);
@@ -368,6 +369,7 @@ struct osi_dma_chan_ops {
unsigned int chan,
unsigned int set,
unsigned int interval);
#endif /* !OSI_STRIPPED_LIB */
/** Called to get Global DMA status */
unsigned int (*get_global_dma_status)(void *addr);
/** Called to clear VM Tx interrupt */
@@ -467,44 +469,6 @@ struct osi_dma_priv_data {
unsigned long resv_buf_phy_addr;
};
/**
* @brief - Read-validate HW registers for func safety.
*
* @note
* Algorithm:
* - Reads pre-configured list of DMA configuration registers
* and compares with last written value for any modifications.
*
* @param[in] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC has to be out of reset.
* - osi_hw_dma_init has to be called. Internally this would initialize
* the safety_config (see osi_dma_priv_data) based on MAC version and
* which specific registers needs to be validated periodically.
* - Invoke this call iff (osi_dma_priv_data->safety_config != OSI_NULL)
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_016
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 on success
* @retval -1 on failure.
*/
int osi_validate_dma_regs(struct osi_dma_priv_data *osi_dma);
/**
* @brief osi_disable_chan_tx_intr - Disables DMA Tx channel interrupts.
@@ -662,6 +626,22 @@ int osi_disable_chan_rx_intr(struct osi_dma_priv_data *osi_dma,
int osi_enable_chan_rx_intr(struct osi_dma_priv_data *osi_dma,
unsigned int chan);
/**
* @brief osi_get_global_dma_status - Gets DMA status.
*
* Algorithm: Returns global DMA Tx/Rx interrupt status
*
* @param[in] osi_dma: DMA private data.
* @param[in] chan: DMA tx channel number.
*
* @note
* Dependencies: None.
* Protection: None.
*
* @retval status
*/
unsigned int osi_get_global_dma_status(struct osi_dma_priv_data *osi_dma);
/**
* @brief osi_clear_vm_tx_intr - Handles VM Tx interrupt source.
*
@@ -786,7 +766,7 @@ int osi_stop_dma(struct osi_dma_priv_data *osi_dma,
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_008
* - SWUD_ID: ETHERNET_NVETHERNETCL_007
*
* @note
* Classification:
@@ -810,9 +790,9 @@ unsigned int osi_get_refill_rx_desc_cnt(struct osi_rx_ring *rx_ring);
*
* @note
* Algorithm:
* - Initialise a Rx DMA descriptor.
* - Initialize a Rx DMA descriptor.
*
* @param[in] osi_dma: OSI DMA private data struture.
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] rx_ring: HW ring corresponding to Rx DMA channel.
* @param[in] chan: Rx DMA channel number
*
@@ -823,7 +803,7 @@ unsigned int osi_get_refill_rx_desc_cnt(struct osi_rx_ring *rx_ring);
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_007
* - SWUD_ID: ETHERNET_NVETHERNETCL_008
*
* @note
* Classification:
@@ -847,7 +827,7 @@ int osi_rx_dma_desc_init(struct osi_dma_priv_data *osi_dma,
/**
* @brief Updates rx buffer length.
*
* @param[in] osi_dma: OSI DMA private data struture.
* @param[in] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC needs to be out of reset and proper clocks need to be configured.
@@ -961,7 +941,7 @@ void osi_hw_transmit(struct osi_dma_priv_data *osi, unsigned int chan);
* - Run time: Yes
* - De-initialization: No
*
* @returns Number of decriptors (buffers) proccessed.
* @returns Number of descriptors (buffers) processed.
*/
int osi_process_tx_completions(struct osi_dma_priv_data *osi,
unsigned int chan, int budget);
@@ -983,7 +963,7 @@ int osi_process_tx_completions(struct osi_dma_priv_data *osi,
*
* @param[in] osi: OSI private data structure.
* @param[in] chan: Rx DMA channel number
* @param[in] budget: Threshould for reading the packets at a time.
* @param[in] budget: Threshold for reading the packets at a time.
* @param[in] more_data_avail: Pointer to more data available flag. OSI fills
* this flag if more rx packets available to read(1) or not(0).
*
@@ -1009,7 +989,7 @@ int osi_process_tx_completions(struct osi_dma_priv_data *osi,
* - Run time: Yes
* - De-initialization: No
*
* @returns Number of decriptors (buffers) proccessed.
* @returns Number of descriptors (buffers) processed.
*/
int osi_process_rx_completions(struct osi_dma_priv_data *osi,
unsigned int chan, int budget,
@@ -1029,7 +1009,7 @@ int osi_process_rx_completions(struct osi_dma_priv_data *osi,
* @pre
* - Allocate memory for osi_dma
* - MAC needs to be out of reset and proper clocks need to be configured.
* - Numer of dma channels osi_dma->num_dma_chans
* - Number of dma channels osi_dma->num_dma_chans
* - channel list osi_dma->dma_chan
* - base address osi_dma->base
* - allocate tx ring osi_dma->tx_ring[chan] for each channel
@@ -1134,6 +1114,116 @@ int osi_hw_dma_deinit(struct osi_dma_priv_data *osi_dma);
*/
int osi_init_dma_ops(struct osi_dma_priv_data *osi_dma);
/**
* @brief osi_dma_get_systime_from_mac - Get system time
*
* @note
* Algorithm:
* - Gets the current system time
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[out] sec: Value read in Seconds
* @param[out] nsec: Value read in Nano seconds
*
* @pre MAC should be init and started. see osi_start_mac()
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_016
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 on success
* @retval -1 on failure.
*/
int osi_dma_get_systime_from_mac(
struct osi_dma_priv_data *const osi_dma,
unsigned int *sec,
unsigned int *nsec);
/**
* @brief osi_is_mac_enabled - Checks if MAC is enabled.
*
* @note
* Algorithm:
* - Reads MAC MCR register for Tx and Rx enabled bits.
*
* @param[in] osi_dma: OSI DMA private data structure.
*
* @pre MAC should be init and started. see osi_start_mac()
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_017
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*
* @retval OSI_ENABLE if MAC enabled.
* @retval OSI_DISABLE otherwise.
*/
unsigned int osi_is_mac_enabled(struct osi_dma_priv_data *const osi_dma);
#ifndef OSI_STRIPPED_LIB
/**
* @brief - Read-validate HW registers for func safety.
*
* @note
* Algorithm:
* - Reads pre-configured list of DMA configuration registers
* and compares with last written value for any modifications.
*
* @param[in] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC has to be out of reset.
* - osi_hw_dma_init has to be called. Internally this would initialize
* the safety_config (see osi_dma_priv_data) based on MAC version and
* which specific registers needs to be validated periodically.
* - Invoke this call if (osi_dma_priv_data->safety_config != OSI_NULL)
*
* @note
* Traceability Details:
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 on success
* @retval -1 on failure.
*/
int osi_validate_dma_regs(struct osi_dma_priv_data *osi_dma);
/**
* @brief osi_clear_tx_pkt_err_stats - Clear tx packet error stats.
*
@@ -1150,7 +1240,6 @@ int osi_init_dma_ops(struct osi_dma_priv_data *osi_dma);
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_018
*
* @note
* Classification:
@@ -1184,7 +1273,6 @@ int osi_clear_tx_pkt_err_stats(struct osi_dma_priv_data *osi_dma);
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_017
*
* @note
* Classification:
@@ -1204,7 +1292,6 @@ int osi_clear_tx_pkt_err_stats(struct osi_dma_priv_data *osi_dma);
*/
int osi_config_slot_function(struct osi_dma_priv_data *osi_dma,
unsigned int set);
/**
* @brief osi_clear_rx_pkt_err_stats - Clear rx packet error stats.
*
@@ -1244,90 +1331,5 @@ int osi_clear_rx_pkt_err_stats(struct osi_dma_priv_data *osi_dma);
* @retval 0 if ring has outstanding packets.
*/
int osi_txring_empty(struct osi_dma_priv_data *osi_dma, unsigned int chan);
/**
* @brief osi_get_global_dma_status - Gets DMA status.
*
* Algorithm: Returns global DMA Tx/Rx interrupt status
*
* @param[in] osi_dma: OSI DMA private data structure.
*
* @note
* Dependencies: None.
* Protection: None.
*
* @retval status
*/
unsigned int osi_get_global_dma_status(struct osi_dma_priv_data *osi_dma);
/**
* @brief osi_dma_get_systime_from_mac - Get system time
*
* @note
* Algorithm:
* - Gets the current system time
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[out] sec: Value read in Seconds
* @param[out] nsec: Value read in Nano seconds
*
* @pre MAC should be init and started. see osi_start_mac()
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_019
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 on success
* @retval -1 on failure.
*/
int osi_dma_get_systime_from_mac(
struct osi_dma_priv_data *const osi_dma,
unsigned int *sec,
unsigned int *nsec);
/**
* @brief osi_is_mac_enabled - Checks if MAC is enabled.
*
* @note
* Algorithm:
* - Reads MAC MCR register for Tx and Rx enabled bits.
*
* @param[in] osi_dma: OSI DMA private data structure.
*
* @pre MAC should be init and started. see osi_start_mac()
*
* @note
* Traceability Details:
* - SWUD_ID: ETHERNET_NVETHERNETCL_020
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*
* @retval OSI_ENABLE if MAC enabled.
* @retval OSI_DISABLE otherwise.
*/
unsigned int osi_is_mac_enabled(struct osi_dma_priv_data *const osi_dma);
#endif /* !OSI_STRIPPED_LIB */
#endif /* OSI_DMA_H */

1
osi/core/Makefile.tmk
View File

@@ -26,6 +26,7 @@ ifdef NV_COMPONENT_FLAG_SHARED_LIBRARY_SECTION
include $(NV_BUILD_START_COMPONENT)
NV_COMPONENT_STRICT_WARNINGS_qnx_64 := 1
NV_COMPONENT_CFLAGS := -DOSI_STRIPPED_LIB
NV_COMPONENT_NAME := nvethernetrm
NV_COMPONENT_OWN_INTERFACE_DIR := .

1351
osi/core/eqos_core.c
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File diff suppressed because it is too large Load Diff

15
osi/core/libnvethernetrm.export
View File

@@ -1,6 +1,6 @@
################################### tell Emacs this is a -*- makefile-gmake -*-
#
# Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -36,28 +36,15 @@ osi_common_isr
osi_set_mode
osi_set_speed
osi_pad_calibrate
osi_flush_mtl_tx_queue
osi_config_mac_loopback
osi_set_avb
osi_get_avb
osi_configure_txstatus
osi_config_rx_crc_check
osi_get_mac_version
osi_get_hw_features
osi_config_arp_offload
osi_config_rxcsum_offload
osi_configure_flow_control
osi_l2_filter
osi_l3l4_filter
osi_config_vlan_filtering
osi_update_vlan_id
osi_config_fw_err_pkts
osi_ptp_configuration
osi_get_systime_from_mac
osi_adjust_time
osi_adjust_freq
osi_set_systime_to_mac
osi_read_mmc
osi_reset_mmc
osi_validate_core_regs
osi_configure_eee

294
osi/core/osi_core.c
View File

@@ -111,19 +111,6 @@ int osi_hw_core_deinit(struct osi_core_priv_data *const osi_core)
return -1;
}
int osi_validate_core_regs(struct osi_core_priv_data *const osi_core)
{
int ret = -1;
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->validate_regs != OSI_NULL) &&
(osi_core->safety_config != OSI_NULL)) {
ret = osi_core->ops->validate_regs(osi_core);
}
return ret;
}
int osi_start_mac(struct osi_core_priv_data *const osi_core)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
@@ -190,21 +177,10 @@ int osi_pad_calibrate(struct osi_core_priv_data *const osi_core)
return -1;
}
int osi_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core,
const unsigned int qinx)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->flush_mtl_tx_queue != OSI_NULL)) {
return osi_core->ops->flush_mtl_tx_queue(osi_core->base, qinx);
}
return -1;
}
int osi_config_mac_loopback(struct osi_core_priv_data *const osi_core,
const unsigned int lb_mode)
{
/* Configure MAC LoopBack */
/* Configure MAC loopback */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_mac_loopback != OSI_NULL)) {
return osi_core->ops->config_mac_loopback(osi_core->base,
@@ -214,41 +190,6 @@ int osi_config_mac_loopback(struct osi_core_priv_data *const osi_core,
return -1;
}
int osi_set_avb(struct osi_core_priv_data *const osi_core,
const struct osi_core_avb_algorithm *avb)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->set_avb_algorithm != OSI_NULL)) {
return osi_core->ops->set_avb_algorithm(osi_core, avb);
}
return -1;
}
int osi_get_avb(struct osi_core_priv_data *const osi_core,
struct osi_core_avb_algorithm *avb)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->get_avb_algorithm != OSI_NULL)) {
return osi_core->ops->get_avb_algorithm(osi_core, avb);
}
return -1;
}
int osi_configure_txstatus(struct osi_core_priv_data *const osi_core,
const unsigned int tx_status)
{
/* Configure Drop Transmit Status */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_tx_status != OSI_NULL)) {
return osi_core->ops->config_tx_status(osi_core->base,
tx_status);
}
return -1;
}
int osi_config_fw_err_pkts(struct osi_core_priv_data *const osi_core,
const unsigned int qinx, const unsigned int fw_err)
{
@@ -262,47 +203,6 @@ int osi_config_fw_err_pkts(struct osi_core_priv_data *const osi_core,
return -1;
}
int osi_config_rx_crc_check(struct osi_core_priv_data *const osi_core,
const unsigned int crc_chk)
{
/* Configure CRC Checking for Received Packets */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_rx_crc_check != OSI_NULL)) {
return osi_core->ops->config_rx_crc_check(osi_core->base,
crc_chk);
}
return -1;
}
int osi_configure_flow_control(
struct osi_core_priv_data *const osi_core,
const unsigned int flw_ctrl)
{
/* Configure Flow control settings */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_flow_control != OSI_NULL)) {
return osi_core->ops->config_flow_control(osi_core->base,
flw_ctrl);
}
return -1;
}
int osi_config_arp_offload(struct osi_core_priv_data *const osi_core,
const unsigned int flags,
const unsigned char *ip_addr)
{
if (osi_core != OSI_NULL && osi_core->ops != OSI_NULL &&
osi_core->ops->config_arp_offload != OSI_NULL) {
return osi_core->ops->config_arp_offload(osi_core->mac_ver,
osi_core->base,
flags, ip_addr);
}
return -1;
}
int osi_l2_filter(struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter)
{
@@ -521,24 +421,6 @@ int osi_l3l4_filter(struct osi_core_priv_data *const osi_core,
return ret;
}
int osi_config_vlan_filtering(
struct osi_core_priv_data *const osi_core,
const unsigned int filter_enb_dis,
const unsigned int perfect_hash_filtering,
const unsigned int perfect_inverse_match)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_vlan_filtering != OSI_NULL)) {
return osi_core->ops->config_vlan_filtering(
osi_core,
filter_enb_dis,
perfect_hash_filtering,
perfect_inverse_match);
}
return -1;
}
int osi_config_rxcsum_offload(
struct osi_core_priv_data *const osi_core,
const unsigned int enable)
@@ -552,18 +434,6 @@ int osi_config_rxcsum_offload(
return -1;
}
int osi_update_vlan_id(struct osi_core_priv_data *const osi_core,
const unsigned int vid)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->update_vlan_id != OSI_NULL)) {
return osi_core->ops->update_vlan_id(osi_core->base,
vid);
}
return -1;
}
int osi_set_systime_to_mac(struct osi_core_priv_data *const osi_core,
const unsigned int sec, const unsigned int nsec)
{
@@ -721,21 +591,6 @@ int osi_adjust_time(struct osi_core_priv_data *const osi_core,
return ret;
}
int osi_get_systime_from_mac(
struct osi_core_priv_data *const osi_core,
unsigned int *sec,
unsigned int *nsec)
{
if ((osi_core != OSI_NULL) && (osi_core->base != OSI_NULL)) {
common_get_systime_from_mac(osi_core->base, osi_core->mac, sec,
nsec);
} else {
return -1;
}
return 0;
}
int osi_ptp_configuration(struct osi_core_priv_data *const osi_core,
const unsigned int enable)
{
@@ -814,6 +669,124 @@ int osi_read_mmc(struct osi_core_priv_data *const osi_core)
return -1;
}
#ifndef OSI_STRIPPED_LIB
int osi_validate_core_regs(struct osi_core_priv_data *const osi_core)
{
int ret = -1;
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->validate_regs != OSI_NULL) &&
(osi_core->safety_config != OSI_NULL)) {
ret = osi_core->ops->validate_regs(osi_core);
}
return ret;
}
int osi_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core,
const unsigned int qinx)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->flush_mtl_tx_queue != OSI_NULL)) {
return osi_core->ops->flush_mtl_tx_queue(osi_core->base, qinx);
}
return -1;
}
int osi_set_avb(struct osi_core_priv_data *const osi_core,
const struct osi_core_avb_algorithm *avb)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->set_avb_algorithm != OSI_NULL)) {
return osi_core->ops->set_avb_algorithm(osi_core, avb);
}
return -1;
}
int osi_get_avb(struct osi_core_priv_data *const osi_core,
struct osi_core_avb_algorithm *avb)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->get_avb_algorithm != OSI_NULL)) {
return osi_core->ops->get_avb_algorithm(osi_core, avb);
}
return -1;
}
int osi_configure_txstatus(struct osi_core_priv_data *const osi_core,
const unsigned int tx_status)
{
/* Configure Drop Transmit Status */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_tx_status != OSI_NULL)) {
return osi_core->ops->config_tx_status(osi_core->base,
tx_status);
}
return -1;
}
int osi_config_rx_crc_check(struct osi_core_priv_data *const osi_core,
const unsigned int crc_chk)
{
/* Configure CRC Checking for Received Packets */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_rx_crc_check != OSI_NULL)) {
return osi_core->ops->config_rx_crc_check(osi_core->base,
crc_chk);
}
return -1;
}
int osi_config_vlan_filtering(
struct osi_core_priv_data *const osi_core,
const unsigned int filter_enb_dis,
const unsigned int perfect_hash_filtering,
const unsigned int perfect_inverse_match)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_vlan_filtering != OSI_NULL)) {
return osi_core->ops->config_vlan_filtering(
osi_core,
filter_enb_dis,
perfect_hash_filtering,
perfect_inverse_match);
}
return -1;
}
int osi_update_vlan_id(struct osi_core_priv_data *const osi_core,
const unsigned int vid)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->update_vlan_id != OSI_NULL)) {
return osi_core->ops->update_vlan_id(osi_core->base,
vid);
}
return -1;
}
int osi_get_systime_from_mac(
struct osi_core_priv_data *const osi_core,
unsigned int *sec,
unsigned int *nsec)
{
if ((osi_core != OSI_NULL) && (osi_core->base != OSI_NULL)) {
common_get_systime_from_mac(osi_core->base, osi_core->mac, sec,
nsec);
} else {
return -1;
}
return 0;
}
int osi_reset_mmc(struct osi_core_priv_data *const osi_core)
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
@@ -862,3 +835,32 @@ int osi_restore_registers(struct osi_core_priv_data *const osi_core)
return -1;
}
int osi_configure_flow_control(
struct osi_core_priv_data *const osi_core,
const unsigned int flw_ctrl)
{
/* Configure Flow control settings */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_flow_control != OSI_NULL)) {
return osi_core->ops->config_flow_control(osi_core->base,
flw_ctrl);
}
return -1;
}
int osi_config_arp_offload(struct osi_core_priv_data *const osi_core,
const unsigned int flags,
const unsigned char *ip_addr)
{
if (osi_core != OSI_NULL && osi_core->ops != OSI_NULL &&
osi_core->ops->config_arp_offload != OSI_NULL) {
return osi_core->ops->config_arp_offload(osi_core->mac_ver,
osi_core->base,
flags, ip_addr);
}
return -1;
}
#endif /* !OSI_STRIPPED_LIB */

1
osi/dma/Makefile.tmk
View File

@@ -26,6 +26,7 @@ ifdef NV_COMPONENT_FLAG_SHARED_LIBRARY_SECTION
include $(NV_BUILD_START_COMPONENT)
NV_COMPONENT_STRICT_WARNINGS_qnx_64 := 1
NV_COMPONENT_CFLAGS := -DOSI_STRIPPED_LIB
NV_COMPONENT_NAME := nvethernetcl
NV_COMPONENT_OWN_INTERFACE_DIR := .

226
osi/dma/eqos_dma.c
View File

@@ -68,7 +68,7 @@ static inline void eqos_dma_safety_writel(unsigned int val, void *addr,
* - Populate the list of safety critical registers and provide
* - the address of the register
* - Register mask (to ignore reserved/self-critical bits in the reg).
* See eqos_validate_dma_regs which can be ivoked periodically to compare
* See eqos_validate_dma_regs which can be invoked periodically to compare
* the last written value to this register vs the actual value read when
* eqos_validate_dma_regs is scheduled.
*/
@@ -128,70 +128,6 @@ static void eqos_dma_safety_init(struct osi_dma_priv_data *osi_dma)
osi_lock_init(&config->dma_safety_lock);
}
/**
* @brief Read-validate HW registers for functional safety.
*
* @note
* Algorithm:
* - Reads pre-configured list of MAC/MTL configuration registers
* and compares with last written value for any modifications.
*
* @param[in] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC has to be out of reset.
* - osi_hw_dma_init has to be called. Internally this would initialize
* the safety_config (see osi_dma_priv_data) based on MAC version and
* which specific registers needs to be validated periodically.
* - Invoke this call iff (osi_dma_priv_data->safety_config != OSI_NULL)
*
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_validate_dma_regs(struct osi_dma_priv_data *osi_dma)
{
struct dma_func_safety *config =
(struct dma_func_safety *)osi_dma->safety_config;
unsigned int cur_val;
unsigned int i;
osi_lock_irq_enabled(&config->dma_safety_lock);
for (i = EQOS_DMA_CH0_CTRL_IDX; i < EQOS_MAX_DMA_SAFETY_REGS; i++) {
if (config->reg_addr[i] == OSI_NULL) {
continue;
}
/* FIXME
* QNX OSD currently overwrites following registers and
* therefore validation fails using this API. Add an
* exception for following registers until QNX OSD completely
* moves to common library.
*/
if ((i == EQOS_DMA_CH0_TDRL_IDX) ||
(i == EQOS_DMA_CH0_RDRL_IDX))
{
continue;
}
cur_val = osi_readl((unsigned char *)config->reg_addr[i]);
cur_val &= config->reg_mask[i];
if (cur_val == config->reg_val[i]) {
continue;
} else {
/* Register content differs from what was written.
* Return error and let safety manager (NVGaurd etc.)
* take care of corrective action.
*/
osi_unlock_irq_enabled(&config->dma_safety_lock);
return -1;
}
}
osi_unlock_irq_enabled(&config->dma_safety_lock);
return 0;
}
/**
* @brief eqos_disable_chan_tx_intr - Disables DMA Tx channel interrupts.
*
@@ -351,7 +287,7 @@ static void eqos_set_tx_ring_len(void *addr, unsigned int chan,
* @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] chan: DMA Tx channel number.
* @param[in] tx_desc: Tx desc base addess.
* @param[in] tx_desc: Tx desc base address.
*/
static void eqos_set_tx_ring_start_addr(void *addr, unsigned int chan,
unsigned long tx_desc)
@@ -559,56 +495,6 @@ static void eqos_stop_dma(void *addr, unsigned int chan)
EQOS_DMA_CH0_RX_CTRL_IDX + chan);
}
/**
* @brief eqos_config_slot - Configure slot Checking for DMA channel
*
* @note
* Algorithm:
* - Set/Reset the slot function of DMA channel based on given inputs
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: DMA channel number to enable slot function
* @param[in] set: flag for set/reset with value OSI_ENABLE/OSI_DISABLE
* @param[in] interval: slot interval from 0usec to 4095usec
*
* @pre
& - MAC should be init and started. see osi_start_mac()
* - OSD should be initialized
*
* @retval none
*/
static void eqos_config_slot(struct osi_dma_priv_data *osi_dma,
unsigned int chan,
unsigned int set,
unsigned int interval)
{
unsigned int value;
CHECK_CHAN_BOUND(chan);
if (set == OSI_ENABLE) {
/* Program SLOT CTRL register SIV and set ESC bit */
value = osi_readl((unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
value &= ~EQOS_DMA_CHX_SLOT_SIV_MASK;
/* remove overflow bits of interval */
interval &= EQOS_DMA_CHX_SLOT_SIV_MASK;
value |= (interval << EQOS_DMA_CHX_SLOT_SIV_SHIFT);
/* Set ESC bit */
value |= EQOS_DMA_CHX_SLOT_ESC;
osi_writel(value, (unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
} else {
/* Clear ESC bit of SLOT CTRL register */
value = osi_readl((unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
value &= ~EQOS_DMA_CHX_SLOT_ESC;
osi_writel(value, (unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
}
}
/**
* @brief eqos_configure_dma_channel - Configure DMA channel
*
@@ -700,7 +586,7 @@ static void eqos_configure_dma_channel(unsigned int chan,
/* Set Receive Interrupt Watchdog Timer Count */
/* conversion of usec to RWIT value
* Eg:System clock is 125MHz, each clock cycle would then be 8ns
* Eg: System clock is 125MHz, each clock cycle would then be 8ns
* For value 0x1 in RWT, device would wait for 512 clk cycles with
* RWTU as 0x1,
* ie, (8ns x 512) => 4.096us (rounding off to 4us)
@@ -805,6 +691,110 @@ static void eqos_set_rx_buf_len(struct osi_dma_priv_data *osi_dma)
~(EQOS_AXI_BUS_WIDTH - 1U));
}
#ifndef OSI_STRIPPED_LIB
/**
* @brief Read-validate HW registers for functional safety.
*
* @note
* Algorithm:
* - Reads pre-configured list of MAC/MTL configuration registers
* and compares with last written value for any modifications.
*
* @param[in] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC has to be out of reset.
* - osi_hw_dma_init has to be called. Internally this would initialize
* the safety_config (see osi_dma_priv_data) based on MAC version and
* which specific registers needs to be validated periodically.
* - Invoke this call if (osi_dma_priv_data->safety_config != OSI_NULL)
*
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_validate_dma_regs(struct osi_dma_priv_data *osi_dma)
{
struct dma_func_safety *config =
(struct dma_func_safety *)osi_dma->safety_config;
unsigned int cur_val;
unsigned int i;
osi_lock_irq_enabled(&config->dma_safety_lock);
for (i = EQOS_DMA_CH0_CTRL_IDX; i < EQOS_MAX_DMA_SAFETY_REGS; i++) {
if (config->reg_addr[i] == OSI_NULL) {
continue;
}
cur_val = osi_readl((unsigned char *)config->reg_addr[i]);
cur_val &= config->reg_mask[i];
if (cur_val == config->reg_val[i]) {
continue;
} else {
/* Register content differs from what was written.
* Return error and let safety manager (NVGaurd etc.)
* take care of corrective action.
*/
osi_unlock_irq_enabled(&config->dma_safety_lock);
return -1;
}
}
osi_unlock_irq_enabled(&config->dma_safety_lock);
return 0;
}
/**
* @brief eqos_config_slot - Configure slot Checking for DMA channel
*
* @note
* Algorithm:
* - Set/Reset the slot function of DMA channel based on given inputs
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: DMA channel number to enable slot function
* @param[in] set: flag for set/reset with value OSI_ENABLE/OSI_DISABLE
* @param[in] interval: slot interval from 0usec to 4095usec
*
* @pre
& - MAC should be init and started. see osi_start_mac()
* - OSD should be initialized
*
* @retval none
*/
static void eqos_config_slot(struct osi_dma_priv_data *osi_dma,
unsigned int chan,
unsigned int set,
unsigned int interval)
{
unsigned int value;
CHECK_CHAN_BOUND(chan);
if (set == OSI_ENABLE) {
/* Program SLOT CTRL register SIV and set ESC bit */
value = osi_readl((unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
value &= ~EQOS_DMA_CHX_SLOT_SIV_MASK;
/* remove overflow bits of interval */
interval &= EQOS_DMA_CHX_SLOT_SIV_MASK;
value |= (interval << EQOS_DMA_CHX_SLOT_SIV_SHIFT);
/* Set ESC bit */
value |= EQOS_DMA_CHX_SLOT_ESC;
osi_writel(value, (unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
} else {
/* Clear ESC bit of SLOT CTRL register */
value = osi_readl((unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
value &= ~EQOS_DMA_CHX_SLOT_ESC;
osi_writel(value, (unsigned char *)osi_dma->base +
EQOS_DMA_CHX_SLOT_CTRL(chan));
}
}
#endif /* !OSI_STRIPPED_LIB */
/**
* @brief eqos_get_global_dma_status - Gets DMA status.
*
@@ -885,8 +875,10 @@ static struct osi_dma_chan_ops eqos_dma_chan_ops = {
.stop_dma = eqos_stop_dma,
.init_dma_channel = eqos_init_dma_channel,
.set_rx_buf_len = eqos_set_rx_buf_len,
#ifndef OSI_STRIPPED_LIB
.validate_regs = eqos_validate_dma_regs,
.config_slot = eqos_config_slot,
#endif /* !OSI_STRIPPED_LIB */
.get_global_dma_status = eqos_get_global_dma_status,
.clear_vm_tx_intr = eqos_clear_vm_tx_intr,
.clear_vm_rx_intr = eqos_clear_vm_rx_intr,

3
osi/dma/libnvethernetcl.export
View File

@@ -38,8 +38,5 @@ osi_process_rx_completions
osi_hw_dma_init
osi_hw_dma_deinit
osi_init_dma_ops
osi_validate_dma_regs
osi_config_slot_function
osi_clear_tx_pkt_err_stats
osi_dma_get_systime_from_mac
osi_is_mac_enabled

7
osi/dma/osi_dma.c
View File

@@ -29,7 +29,7 @@ int osi_init_dma_ops(struct osi_dma_priv_data *osi_dma)
/*
* Currently these osd_ops are optional to be filled in the OSD layer.
* If OSD updates these pointers, use the same. If not, fall back to the
* exisitng way of using osd_* API's.
* existing way of using osd_* API's.
* TODO: Once These API's are mandatory, return errors instead of
* default API usage.
*/
@@ -331,6 +331,7 @@ int osi_set_rx_buf_len(struct osi_dma_priv_data *osi_dma)
return 0;
}
#ifndef OSI_STRIPPED_LIB
int osi_config_slot_function(struct osi_dma_priv_data *osi_dma,
unsigned int set)
{
@@ -346,7 +347,6 @@ int osi_config_slot_function(struct osi_dma_priv_data *osi_dma,
return -1;
}
/* Configure slot Checking for Tranmit */
if (osi_dma == OSI_NULL || osi_dma->ops == OSI_NULL ||
osi_dma->ops->config_slot == OSI_NULL) {
OSI_ERR(OSI_NULL,
@@ -363,7 +363,7 @@ int osi_config_slot_function(struct osi_dma_priv_data *osi_dma,
/* Ignore 0 and invalid channels */
continue;
}
/* Check for slot enbale */
/* Check for slot enable */
if (osi_dma->slot_enabled[chan] == OSI_ENABLE) {
/* Get DMA slot interval and validate */
interval = osi_dma->slot_interval[chan];
@@ -412,6 +412,7 @@ int osi_txring_empty(struct osi_dma_priv_data *osi_dma, unsigned int chan)
return (tx_ring->clean_idx == tx_ring->cur_tx_idx) ? 1 : 0;
}
#endif /* !OSI_STRIPPED_LIB */
int osi_dma_get_systime_from_mac(struct osi_dma_priv_data *const osi_dma,
unsigned int *sec,

10
osi/dma/osi_dma_txrx.c
View File

@@ -291,7 +291,7 @@ int osi_process_rx_completions(struct osi_dma_priv_data *osi,
break;
}
/* WHen JE is set, HW will accept any valid packet on Rx upto
/* When JE is set, HW will accept any valid packet on Rx upto
* 9K or 16K (depending on GPSCLE bit), irrespective of whether
* MTU set is lower than these specific values. When Rx buf len
* is allocated to be exactly same as MTU, HW will consume more
@@ -468,7 +468,7 @@ static inline void get_tx_err_stats(struct osi_tx_desc *tx_desc,
1UL);
}
/* Execessive Collision Error */
/* Excessive Collision Error */
if ((tx_desc->tdes3 & TDES3_EXCESSIVE_COL_ERR) ==
TDES3_EXCESSIVE_COL_ERR) {
pkt_err_stats->excessive_collision_error =
@@ -494,6 +494,7 @@ static inline void get_tx_err_stats(struct osi_tx_desc *tx_desc,
}
}
#ifndef OSI_STRIPPED_LIB
int osi_clear_tx_pkt_err_stats(struct osi_dma_priv_data *osi_dma)
{
int ret = -1;
@@ -538,6 +539,7 @@ int osi_clear_rx_pkt_err_stats(struct osi_dma_priv_data *osi_dma)
return ret;
}
#endif /* !OSI_STRIPPED_LIB */
int osi_process_tx_completions(struct osi_dma_priv_data *osi,
unsigned int chan, int budget)
@@ -625,7 +627,7 @@ int osi_process_tx_completions(struct osi_dma_priv_data *osi,
/* Don't wait to update tx_ring->clean-idx. It will
* be used by OSD layer to determine the num. of available
* descriptors in the ring, which will inturn be used to
* descriptors in the ring, which will in turn be used to
* wake the corresponding transmit queue in OS layer.
*/
tx_ring->clean_idx = entry;
@@ -814,7 +816,7 @@ void osi_hw_transmit(struct osi_dma_priv_data *osi, unsigned int chan)
return;
}
/* Context decriptor for VLAN/TSO */
/* Context descriptor for VLAN/TSO */
if ((tx_pkt_cx->flags & OSI_PKT_CX_VLAN) == OSI_PKT_CX_VLAN) {
osi->dstats.tx_vlan_pkt_n =
osi_update_stats_counter(osi->dstats.tx_vlan_pkt_n,