nv-tegra-mirror/nvethernetrm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/kernel/nvethernetrm.git synced 2025-12-22 09:12:10 +03:00
Code Issues Packages Projects Releases Wiki Activity

osi: Remove duplicate macros

Browse Source 
The below macros were duplicated in the respective
components of osi/core and osi/dma.
1. MGBE_DMA_CHX_MAX_PBL
2. MGBE_DMA_CHX_PBL_16
3. MGBE_DMA_CHX_PBL_8
4. MGBE_DMA_CHX_PBL_4
5. MGBE_DMA_CHX_PBL_1
6. osi_valid_pbl_value()
7. osi_memset()

Move these common macros and APIs which are used by both
osi/core and osi/dma to include/osi_common.h

This also statically assigns TxPBL=16 for Orin.

Bug 4569357

Change-Id: I390e0ad9c0bfda47a1a7f9dd94cf5f7f45d96b9c
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3211481
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Aniruddha Paul
2024-09-11 07:46:21 +00:00
committed by mobile promotions
parent 8cf1ea5184
commit 22a75ac576
4 changed files with 71 additions and 145 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
include/osi_common.h
View File

@@ -351,6 +351,34 @@ static inline void osi_memset(void *s, nveu8_t c, nveu64_t count)
/** @brief macro for 1 micro second delay */
#define OSI_DELAY_1US 1U
/**
* @addtogroup MGBE PBL settings.
*
* @brief Values defined for PBL settings
* @{
*/
/* Tx Queue size is 128KB */
#define MGBE_TXQ_SIZE 131072U
/* Rx Queue size is 192KB */
#define MGBE_RXQ_SIZE 196608U
/* uFPGA config Tx Queue size is 64KB */
#define MGBE_TXQ_SIZE_UFPGA 65536U
/* PBL values */
#define MGBE_DMA_CHX_MAX_PBL 32U
#define MGBE_DMA_CHX_PBL_16 16U
#define MGBE_DMA_CHX_PBL_8 8U
#define MGBE_DMA_CHX_PBL_4 4U
#define MGBE_DMA_CHX_PBL_1 1U
/* AXI Data width */
#define MGBE_AXI_DATAWIDTH 128U
/** @} */
/**
* @brief MTL Q size depth helper macro
*/
#define Q_SZ_DEPTH(x) (((x) * 1024U) / (MGBE_AXI_DATAWIDTH / 8U))
/**
* @brief OSI PDMA to VDMA mapping data
*/
@@ -363,4 +391,44 @@ struct osi_pdma_vdma_data {
nveu32_t vdma_chans[OSI_MGBE_MAX_NUM_CHANS];
};
/**
* @brief osi_valid_pbl_value - returns the allowed pbl value.
* @note
* Algorithm:
* - Check the pbl range and return allowed pbl value
*
* @param[in] pbl: Calculated PBL value
*
* @note Input parameter should be only nveu32_t type
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval allowed pbl value
*/
static inline nveu32_t osi_valid_pbl_value(nveu32_t pbl_value)
{
nveu32_t allowed_pbl;
nveu32_t pbl;
/* 8xPBL mode is set */
pbl = pbl_value / 8U;
if (pbl >= MGBE_DMA_CHX_MAX_PBL) {
allowed_pbl = MGBE_DMA_CHX_MAX_PBL;
} else if (pbl >= MGBE_DMA_CHX_PBL_16) {
allowed_pbl = MGBE_DMA_CHX_PBL_16;
} else if (pbl >= MGBE_DMA_CHX_PBL_8) {
allowed_pbl = MGBE_DMA_CHX_PBL_8;
} else if (pbl >= MGBE_DMA_CHX_PBL_4) {
allowed_pbl = MGBE_DMA_CHX_PBL_4;
} else {
allowed_pbl = MGBE_DMA_CHX_PBL_1;
}
return allowed_pbl;
}
#endif /* OSI_COMMON_H */