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osi: Remove duplicate macros

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The below macros were duplicated in the respective
components of osi/core and osi/dma.
1. MGBE_DMA_CHX_MAX_PBL
2. MGBE_DMA_CHX_PBL_16
3. MGBE_DMA_CHX_PBL_8
4. MGBE_DMA_CHX_PBL_4
5. MGBE_DMA_CHX_PBL_1
6. osi_valid_pbl_value()
7. osi_memset()

Move these common macros and APIs which are used by both
osi/core and osi/dma to include/osi_common.h

This also statically assigns TxPBL=16 for Orin.

Bug 4569357

Change-Id: I390e0ad9c0bfda47a1a7f9dd94cf5f7f45d96b9c
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3211481
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Aniruddha Paul
2024-09-11 07:46:21 +00:00
committed by mobile promotions
parent 8cf1ea5184
commit 22a75ac576
4 changed files with 71 additions and 145 deletions
Download Patch File Download Diff File Expand all files Collapse all files

68
include/osi_common.h
View File

@@ -351,6 +351,34 @@ static inline void osi_memset(void *s, nveu8_t c, nveu64_t count)
/** @brief macro for 1 micro second delay */
#define OSI_DELAY_1US 1U
/**
* @addtogroup MGBE PBL settings.
*
* @brief Values defined for PBL settings
* @{
*/
/* Tx Queue size is 128KB */
#define MGBE_TXQ_SIZE 131072U
/* Rx Queue size is 192KB */
#define MGBE_RXQ_SIZE 196608U
/* uFPGA config Tx Queue size is 64KB */
#define MGBE_TXQ_SIZE_UFPGA 65536U
/* PBL values */
#define MGBE_DMA_CHX_MAX_PBL 32U
#define MGBE_DMA_CHX_PBL_16 16U
#define MGBE_DMA_CHX_PBL_8 8U
#define MGBE_DMA_CHX_PBL_4 4U
#define MGBE_DMA_CHX_PBL_1 1U
/* AXI Data width */
#define MGBE_AXI_DATAWIDTH 128U
/** @} */
/**
* @brief MTL Q size depth helper macro
*/
#define Q_SZ_DEPTH(x) (((x) * 1024U) / (MGBE_AXI_DATAWIDTH / 8U))
/**
* @brief OSI PDMA to VDMA mapping data
*/
@@ -363,4 +391,44 @@ struct osi_pdma_vdma_data {
nveu32_t vdma_chans[OSI_MGBE_MAX_NUM_CHANS];
};
/**
* @brief osi_valid_pbl_value - returns the allowed pbl value.
* @note
* Algorithm:
* - Check the pbl range and return allowed pbl value
*
* @param[in] pbl: Calculated PBL value
*
* @note Input parameter should be only nveu32_t type
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval allowed pbl value
*/
static inline nveu32_t osi_valid_pbl_value(nveu32_t pbl_value)
{
nveu32_t allowed_pbl;
nveu32_t pbl;
/* 8xPBL mode is set */
pbl = pbl_value / 8U;
if (pbl >= MGBE_DMA_CHX_MAX_PBL) {
allowed_pbl = MGBE_DMA_CHX_MAX_PBL;
} else if (pbl >= MGBE_DMA_CHX_PBL_16) {
allowed_pbl = MGBE_DMA_CHX_PBL_16;
} else if (pbl >= MGBE_DMA_CHX_PBL_8) {
allowed_pbl = MGBE_DMA_CHX_PBL_8;
} else if (pbl >= MGBE_DMA_CHX_PBL_4) {
allowed_pbl = MGBE_DMA_CHX_PBL_4;
} else {
allowed_pbl = MGBE_DMA_CHX_PBL_1;
}
return allowed_pbl;
}
#endif /* OSI_COMMON_H */

70
osi/core/common.h
View File

@@ -37,34 +37,6 @@
#define RETRY_DELAY 1U
/** @} */
/**
* @addtogroup MGBE PBL settings.
*
* @brief Values defined for PBL settings
* @{
*/
/* Tx Queue size is 128KB */
#define MGBE_TXQ_SIZE 131072U
/* Rx Queue size is 192KB */
#define MGBE_RXQ_SIZE 196608U
/* uFPGA config Tx Queue size is 64KB */
#define MGBE_TXQ_SIZE_UFPGA 65536U
/* PBL values */
#define MGBE_DMA_CHX_MAX_PBL 32U
#define MGBE_DMA_CHX_PBL_16 16U
#define MGBE_DMA_CHX_PBL_8 8U
#define MGBE_DMA_CHX_PBL_4 4U
#define MGBE_DMA_CHX_PBL_1 1U
/* AXI Data width */
#define MGBE_AXI_DATAWIDTH 128U
/** @} */
/**
* @brief MTL Q size depth helper macro
*/
#define Q_SZ_DEPTH(x) (((x) * 1024U) / (MGBE_AXI_DATAWIDTH / 8U))
/**
* @brief osi_readl_poll_timeout - Periodically poll an address until
* a condition is met or a timeout occurs
@@ -365,46 +337,4 @@ static inline nve32_t osi_memcmp(const void *dest, const void *src, nve32_t n)
fail:
return ret;
}
/**
* @brief osi_valid_pbl_value - returns the allowed pbl value.
* @note
* Algorithm:
* - Check the pbl range and return allowed pbl value
*
* @param[in] pbl: Calculated PBL value
*
* @note Input parameter should be only nveu32_t type
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval allowed pbl value
*/
static inline nveu32_t osi_valid_pbl_value(nveu32_t pbl_value)
{
nveu32_t allowed_pbl;
nveu32_t pbl;
/* 8xPBL mode is set */
pbl = pbl_value / 8U;
if (pbl >= MGBE_DMA_CHX_MAX_PBL) {
allowed_pbl = MGBE_DMA_CHX_MAX_PBL;
} else if (pbl >= MGBE_DMA_CHX_PBL_16) {
allowed_pbl = MGBE_DMA_CHX_PBL_16;
} else if (pbl >= MGBE_DMA_CHX_PBL_8) {
allowed_pbl = MGBE_DMA_CHX_PBL_8;
} else if (pbl >= MGBE_DMA_CHX_PBL_4) {
allowed_pbl = MGBE_DMA_CHX_PBL_4;
} else {
allowed_pbl = MGBE_DMA_CHX_PBL_1;
}
return allowed_pbl;
}
#endif

18
osi/dma/mgbe_dma.h
View File

@@ -94,6 +94,7 @@
#define MGBE_DMA_CHX_RX_CNTRL2_OWRQ_SCHAN 32U
#define MGBE_DMA_CHX_RX_CNTRL2_OWRQ_MCHAN 64U
#define MGBE_DMA_CHX_RX_CNTRL2_OWRQ_SHIFT 24U
#define MGBE_DMA_CHX_TX_CTRL_TXPBL_RECOMMENDED 0x100000U
#define MGBE_DMA_CHX_CTRL_PBL_SHIFT 16U
/* MGBE VDMA to TC mask */
#define MGBE_TX_VDMA_TC_MASK (OSI_BIT(4) | OSI_BIT(5) | OSI_BIT(6))
@@ -104,23 +105,6 @@
/** @} */
/**
* @addtogroup MGBE_PBL_settings.
*
* @brief Values defined for PBL settings
* @{
*/
/* Tx Queue size is 128KB */
#define MGBE_TXQ_SIZE 131072U
/* Rx Queue size is 192KB */
#define MGBE_RXQ_SIZE 196608U
/* MAX PBL value */
#define MGBE_DMA_CHX_MAX_PBL 256U
#define MGBE_DMA_CHX_MAX_PBL_VAL 0x200000U
/* AXI Data width */
#define MGBE_AXI_DATAWIDTH 128U
/** @} */
/**
* @addtogroup MGBE-MAC MAC register offsets
*

60
osi/dma/osi_dma.c
View File

@@ -33,44 +33,6 @@
#endif /* OSI_DEBUG */
#include "hw_common.h"
#if 1 // copied from osi/core/common.h
/**
* @brief MTL Q size depth helper macro
*/
#define Q_SZ_DEPTH(x) (((x) * 1024U) / (MGBE_AXI_DATAWIDTH / 8U))
/* PBL values */
//redefined #define MGBE_DMA_CHX_MAX_PBL 32U
#define MGBE_DMA_CHX_PBL_16 16U
#define MGBE_DMA_CHX_PBL_8 8U
#define MGBE_DMA_CHX_PBL_4 4U
#define MGBE_DMA_CHX_PBL_1 1U
static inline nveu32_t osi_valid_pbl_value(nveu32_t pbl_value)
{
nveu32_t allowed_pbl;
nveu32_t pbl;
/* 8xPBL mode is set */
pbl = pbl_value / 8U;
if (pbl >= MGBE_DMA_CHX_MAX_PBL) {
allowed_pbl = MGBE_DMA_CHX_MAX_PBL;
} else if (pbl >= MGBE_DMA_CHX_PBL_16) {
allowed_pbl = MGBE_DMA_CHX_PBL_16;
} else if (pbl >= MGBE_DMA_CHX_PBL_8) {
allowed_pbl = MGBE_DMA_CHX_PBL_8;
} else if (pbl >= MGBE_DMA_CHX_PBL_4) {
allowed_pbl = MGBE_DMA_CHX_PBL_4;
} else {
allowed_pbl = MGBE_DMA_CHX_PBL_1;
}
return allowed_pbl;
}
#endif
/**
* @brief g_dma - DMA local data array.
*/
@@ -587,7 +549,7 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
};
nveu32_t tx_pbl[2] = {
EQOS_DMA_CHX_TX_CTRL_TXPBL_RECOMMENDED,
EQOS_DMA_CHX_TX_CTRL_TXPBL_RECOMMENDED
MGBE_DMA_CHX_TX_CTRL_TXPBL_RECOMMENDED
};
const nveu32_t rx_pbl[2] = {
EQOS_DMA_CHX_RX_CTRL_RXPBL_RECOMMENDED,
@@ -623,25 +585,8 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
owrq, owrq, owrq, owrq, owrq, owrq
};
nveu32_t val;
nveu32_t temp_tx_pbl;
nve32_t ret = -1;
temp_tx_pbl = (MGBE_TXQ_SIZE / osi_dma->num_dma_chans);
if (temp_tx_pbl <= osi_dma->mtu) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"temp_tx_pbl is lower than mtu!!!\n", temp_tx_pbl);
goto exit_func;
}
temp_tx_pbl -= osi_dma->mtu;
temp_tx_pbl /= (MGBE_AXI_DATAWIDTH / 8U);
if (temp_tx_pbl <= 5U) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
"Error in distributing queues!!!\n", temp_tx_pbl);
goto exit_func;
}
temp_tx_pbl -= 5U;
tx_pbl[1] = temp_tx_pbl;
/* Enable Transmit/Receive interrupts */
val = osi_dma_readl((nveu8_t *)osi_dma->base + intr_en_reg[osi_dma->mac]);
val |= (DMA_CHX_INTR_TIE | DMA_CHX_INTR_RIE);
@@ -679,8 +624,7 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
* as the TxPBL else we should be using the value whcih we get after
* calculation by using above formula
*/
pbl = osi_valid_pbl_value(tx_pbl[osi_dma->mac]);
val |= (pbl << MGBE_DMA_CHX_CTRL_PBL_SHIFT);
val |= tx_pbl[osi_dma->mac];
} else if (osi_dma->mac == OSI_MAC_HW_MGBE_T26X) {
/* Map Tx VDMA's to TC. TC and PDMA mapped 1 to 1 */
val &= ~MGBE_TX_VDMA_TC_MASK;