nv-tegra-mirror/nvethernetrm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/kernel/nvethernetrm.git synced 2025-12-22 09:12:10 +03:00
Code Issues Packages Projects Releases Wiki Activity

osi: core: move err injec code to vltest

Browse Source 
issue: HSI error injection logic is enabled by default
and is exposed as an ioctl which is a safety-related concern.

fix: move HSI error injection code only for
VLTEST build

Jira NET-1235
Bug 4449611

Change-Id: I9a23895249c7db52586a83a042cf514ef0e5faae
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3077931
(cherry picked from commit 5af42a33298f5408b4209223802139501acf9d39)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3132843
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3293329
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
This commit is contained in:
Narayan Reddy
2024-02-15 22:57:00 +05:30
committed by mobile promotions
parent 1150fc9b29
commit 22e582e01d
8 changed files with 32 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/config.tmk
View File

@@ -1,4 +1,4 @@
# copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved. # copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
# #
# Permission is hereby granted, free of charge, to any person obtaining a # Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"), # copy of this software and associated documentation files (the "Software"),
@@ -38,6 +38,10 @@ NV_COMPONENT_CFLAGS += -DHSI_SUPPORT
NV_COMPONENT_CFLAGS += -DMACSEC_SUPPORT NV_COMPONENT_CFLAGS += -DMACSEC_SUPPORT
NV_COMPONENT_CFLAGS += -DLOG_OSI NV_COMPONENT_CFLAGS += -DLOG_OSI
ifeq ($(NV_BUILD_CONFIGURATION_IS_VLTEST),1)
NV_COMPONENT_CFLAGS += -DNV_VLTEST_BUILD
endif
#NV_COMPONENT_CFLAGS += -DMACSEC_KEY_PROGRAM #NV_COMPONENT_CFLAGS += -DMACSEC_KEY_PROGRAM
HSI_SUPPORT := 1 HSI_SUPPORT := 1
MACSEC_SUPPORT := 1 MACSEC_SUPPORT := 1

7
include/osi_core.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2025, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -269,7 +269,10 @@ typedef my_lint_64 nvel64_t;
#endif #endif
#define OSI_CMD_SUSPEND 53U #define OSI_CMD_SUSPEND 53U
#define OSI_CMD_RESUME 54U #define OSI_CMD_RESUME 54U
#ifdef HSI_SUPPORT #if defined HSI_SUPPORT && defined(NV_VLTEST_BUILD)
/**
* @brief Command to inject HSI error
*/
#define OSI_CMD_HSI_INJECT_ERR 55U #define OSI_CMD_HSI_INJECT_ERR 55U
#endif /* HSI_SUPPORT */ #endif /* HSI_SUPPORT */
#define OSI_CMD_READ_STATS 56U #define OSI_CMD_READ_STATS 56U

4
osi/core/core_common.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -1481,6 +1481,7 @@ void hw_tsn_init(struct osi_core_priv_data *osi_core,
} }
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
#ifdef NV_VLTEST_BUILD
/** /**
* @brief hsi_common_error_inject * @brief hsi_common_error_inject
* *
@@ -1571,6 +1572,7 @@ nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
return ret; return ret;
} }
#endif
/** /**
* @brief hsi_update_mmc_val - function to read register and return value to callee * @brief hsi_update_mmc_val - function to read register and return value to callee

4
osi/core/core_common.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022-2023, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -198,8 +198,10 @@ void prepare_l3l4_registers(const struct osi_core_priv_data *const osi_core,
nveu32_t *l3_addr1_reg, nveu32_t *l3_addr1_reg,
nveu32_t *ctr_reg); nveu32_t *ctr_reg);
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
#ifdef NV_VLTEST_BUILD
nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core, nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
nveu32_t error_code); nveu32_t error_code);
#endif
void hsi_read_err(struct osi_core_priv_data *const osi_core); void hsi_read_err(struct osi_core_priv_data *const osi_core);
#endif #endif
nve32_t hw_validate_avb_input(struct osi_core_priv_data *const osi_core, nve32_t hw_validate_avb_input(struct osi_core_priv_data *const osi_core,

4
osi/core/core_local.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2021-2025, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -229,10 +229,12 @@ struct core_ops {
/** Interface function called to initialize HSI */ /** Interface function called to initialize HSI */
nve32_t (*core_hsi_configure)(struct osi_core_priv_data *const osi_core, nve32_t (*core_hsi_configure)(struct osi_core_priv_data *const osi_core,
const nveu32_t enable); const nveu32_t enable);
#ifdef NV_VLTEST_BUILD
/** Interface function called to inject error */ /** Interface function called to inject error */
nve32_t (*core_hsi_inject_err)(struct osi_core_priv_data *const osi_core, nve32_t (*core_hsi_inject_err)(struct osi_core_priv_data *const osi_core,
const nveu32_t error_code); const nveu32_t error_code);
#endif #endif
#endif
}; };
/** /**

6
osi/core/eqos_core.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2025, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -848,6 +848,7 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core,
return 0; return 0;
} }
#ifdef NV_VLTEST_BUILD
/** /**
* @brief eqos_hsi_inject_err - inject error * @brief eqos_hsi_inject_err - inject error
* *
@@ -891,6 +892,7 @@ static nve32_t eqos_hsi_inject_err(struct osi_core_priv_data *const osi_core,
return ret; return ret;
} }
#endif #endif
#endif
/** /**
* @brief eqos_configure_mac - Configure MAC * @brief eqos_configure_mac - Configure MAC
@@ -4171,6 +4173,8 @@ void eqos_init_core_ops(struct core_ops *ops)
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
ops->core_hsi_configure = eqos_hsi_configure; ops->core_hsi_configure = eqos_hsi_configure;
#ifdef NV_VLTEST_BUILD
ops->core_hsi_inject_err = eqos_hsi_inject_err; ops->core_hsi_inject_err = eqos_hsi_inject_err;
#endif #endif
#endif
} }

6
osi/core/mgbe_core.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -1678,6 +1678,7 @@ fail:
return ret; return ret;
} }
#ifdef NV_VLTEST_BUILD
/** /**
* @brief mgbe_hsi_inject_err - Inject error * @brief mgbe_hsi_inject_err - Inject error
* *
@@ -1727,6 +1728,7 @@ static nve32_t mgbe_hsi_inject_err(struct osi_core_priv_data *const osi_core,
return ret; return ret;
} }
#endif #endif
#endif
/** /**
* @brief mgbe_configure_mac - Configure MAC * @brief mgbe_configure_mac - Configure MAC
@@ -4061,6 +4063,8 @@ void mgbe_init_core_ops(struct core_ops *ops)
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
ops->core_hsi_configure = mgbe_hsi_configure; ops->core_hsi_configure = mgbe_hsi_configure;
#ifdef NV_VLTEST_BUILD
ops->core_hsi_inject_err = mgbe_hsi_inject_err; ops->core_hsi_inject_err = mgbe_hsi_inject_err;
#endif #endif
#endif
}; };

4
osi/core/osi_hal.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2021-2025, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -2968,9 +2968,11 @@ static nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core,
case OSI_CMD_HSI_CONFIGURE: case OSI_CMD_HSI_CONFIGURE:
ret = ops_p->core_hsi_configure(osi_core, data->arg1_u32); ret = ops_p->core_hsi_configure(osi_core, data->arg1_u32);
break; break;
#ifdef NV_VLTEST_BUILD
case OSI_CMD_HSI_INJECT_ERR: case OSI_CMD_HSI_INJECT_ERR:
ret = ops_p->core_hsi_inject_err(osi_core, data->arg1_u32); ret = ops_p->core_hsi_inject_err(osi_core, data->arg1_u32);
break; break;
#endif /* NV_VLTEST_BUILD */
case OSI_CMD_READ_HSI_ERR: case OSI_CMD_READ_HSI_ERR:
hsi_read_err(osi_core); hsi_read_err(osi_core);
ret = 0; ret = 0;