diff --git a/osi/core/core_common.c b/osi/core/core_common.c
index 8d03c68..4d24ec5 100644
--- a/osi/core/core_common.c
+++ b/osi/core/core_common.c
@@ -558,6 +558,30 @@ nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
 	return ret;
 }
 
+nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core,
+				      const nveu32_t filter_enb_dis)
+{
+	nveu32_t value = 0U;
+	void *base = osi_core->base;
+	nve32_t ret = 0;
+
+	/* validate filter_enb_dis argument */
+	if (filter_enb_dis != OSI_ENABLE && filter_enb_dis != OSI_DISABLE) {
+		OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID,
+			"Invalid filter_enb_dis value\n",
+			filter_enb_dis);
+		ret = -1;
+		goto fail;
+	}
+
+	value = osi_readla(osi_core, ((nveu8_t *)base + MAC_PKT_FILTER_REG));
+	value &= ~(MAC_PFR_IPFE);
+	value |= ((filter_enb_dis << MAC_PFR_IPFE_SHIFT) & MAC_PFR_IPFE);
+	osi_writela(osi_core, value, ((nveu8_t *)base + MAC_PKT_FILTER_REG));
+fail:
+	return ret;
+}
+
 #ifndef OSI_STRIPPED_LIB
 /**
  * @brief hw_est_read - indirect read the GCL to Software own list
diff --git a/osi/core/core_common.h b/osi/core/core_common.h
index 77b4d4d..8d1f6ea 100644
--- a/osi/core/core_common.h
+++ b/osi/core/core_common.h
@@ -116,4 +116,6 @@ nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core,
 			   struct osi_core_ptp_tsc_data *data);
 nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
 				     const struct osi_filter *filter);
+nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core,
+				      const nveu32_t filter_enb_dis);
 #endif /* INCLUDED_CORE_COMMON_H */
diff --git a/osi/core/core_local.h b/osi/core/core_local.h
index 0600b53..249d3cb 100644
--- a/osi/core/core_local.h
+++ b/osi/core/core_local.h
@@ -115,10 +115,6 @@ struct core_ops {
 	nve32_t (*update_mac_addr_low_high_reg)(
 				struct osi_core_priv_data *const osi_core,
 				const struct osi_filter *filter);
-	/** Called to configure l3/L4 filter */
-	nve32_t (*config_l3_l4_filter_enable)(
-				struct osi_core_priv_data *const osi_core,
-				const nveu32_t enable);
 	/** Called to configure L3 filter */
 	nve32_t (*config_l3_filters)(struct osi_core_priv_data *const osi_core,
 				     const nveu32_t filter_no,
diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c
index aa659fb..38a3bc4 100644
--- a/osi/core/eqos_core.c
+++ b/osi/core/eqos_core.c
@@ -2858,46 +2858,6 @@ static nve32_t eqos_update_mac_addr_low_high_reg(
 	return ret;
 }
 
-/**
- * @brief eqos_config_l3_l4_filter_enable - register write to enable L3/L4
- *  filters.
- *
- * @note
- * Algorithm:
- *  - This routine to update filter_enb_dis value in IP filter enable register.
- *  - TraceID:ETHERNET_NVETHERNETRM_019
- *
- * @param[in] osi_core: OSI core private data.
- * @param[in] filter_enb_dis: enable/disable
- *
- * @pre MAC should be initialized and started. see osi_start_mac()
- *
- * @note
- * API Group:
- * - Initialization: Yes
- * - Run time: Yes
- * - De-initialization: No
- *
- * @retval 0 on success
- * @retval -1 on failure.
- */
-static nve32_t eqos_config_l3_l4_filter_enable(
-				struct osi_core_priv_data *const osi_core,
-				const nveu32_t filter_enb_dis)
-{
-	nveu32_t value = 0U;
-	void *base = osi_core->base;
-
-	value = osi_readla(osi_core, (nveu8_t *)base + EQOS_MAC_PFR);
-	value &= ~(EQOS_MAC_PFR_IPFE);
-	value |= ((filter_enb_dis << EQOS_MAC_PFR_IPFE_SHIFT) &
-		   EQOS_MAC_PFR_IPFE);
-	eqos_core_safety_writel(osi_core, value, (nveu8_t *)base + EQOS_MAC_PFR,
-				EQOS_MAC_PFR_IDX);
-
-	return 0;
-}
-
 /**
  * @brief eqos_update_ip4_addr - configure register for IPV4 address filtering
  *
@@ -2963,6 +2923,7 @@ static nve32_t eqos_update_ip4_addr(struct osi_core_priv_data *const osi_core,
 
 	return 0;
 }
+
 #ifndef OSI_STRIPPED_LIB
 /**
  * @brief eqos_config_ptp_offload - Enable/Disable PTP offload
@@ -5873,7 +5834,6 @@ void eqos_init_core_ops(struct core_ops *ops)
 	ops->handle_common_intr = eqos_handle_common_intr;
 	ops->pad_calibrate = eqos_pad_calibrate;
 	ops->update_mac_addr_low_high_reg = eqos_update_mac_addr_low_high_reg;
-	ops->config_l3_l4_filter_enable = eqos_config_l3_l4_filter_enable;
 	ops->config_l3_filters = eqos_config_l3_filters;
 	ops->adjust_mactime = eqos_adjust_mactime;
 	ops->read_mmc = eqos_read_mmc;
diff --git a/osi/core/eqos_core.h b/osi/core/eqos_core.h
index bfe5f86..99142a3 100644
--- a/osi/core/eqos_core.h
+++ b/osi/core/eqos_core.h
@@ -24,6 +24,7 @@
 #define INCLUDED_EQOS_CORE_H
 
 #ifndef OSI_STRIPPED_LIB
+#define EQOS_MAC_PFR			0x0008
 #define EQOS_MAC_LPI_CSR		0x00D0
 #define EQOS_MAC_LPI_TIMER_CTRL		0x00D4
 #define EQOS_MAC_LPI_EN_TIMER		0x00D8
@@ -68,6 +69,9 @@
 #define EQOS_CLOCK_CTRL_0		0x8000U
 #define EQOS_APB_ERR_STATUS		0x8214U
 
+#define EQOS_MAC_PFR_VTFE		OSI_BIT(16)
+#define EQOS_MAC_PFR_IPFE		OSI_BIT(20)
+#define EQOS_MAC_PFR_IPFE_SHIFT		20U
 #define EQOS_MAC_MA0HR_IDX			11U
 #define EQOS_5_30_SID		0x3U
 #define EQOS_5_30_SID_CH3	((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_24)
@@ -279,7 +283,6 @@
  */
 #define EQOS_MAC_MCR			0x0000
 #define EQOS_MAC_EXTR			0x0004
-#define EQOS_MAC_PFR			0x0008
 #define EQOS_MAC_VLAN_TAG		0x0050
 #define EQOS_MAC_VLANTIR		0x0060
 #define EQOS_MAC_RQC0R			0x00A0
@@ -460,9 +463,6 @@
 #define EQOS_MTL_RXQ_OP_MODE_RFA_MASK		0x00003F00U
 #define EQOS_MTL_RXQ_OP_MODE_RFD_SHIFT		14U
 #define EQOS_MTL_RXQ_OP_MODE_RFD_MASK		0x000FC000U
-#define EQOS_MAC_PFR_VTFE			OSI_BIT(16)
-#define EQOS_MAC_PFR_IPFE			OSI_BIT(20)
-#define EQOS_MAC_PFR_IPFE_SHIFT		20U
 #define EQOS_MAC_L3L4_CTR_L4SPM0		OSI_BIT(18)
 #define EQOS_MAC_L3L4_CTR_L4SPIM0		OSI_BIT(19)
 #define EQOS_MAC_L3L4_CTR_L4DPM0		OSI_BIT(20)
diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index d45ad98..77950c4 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -824,41 +824,6 @@ static nve32_t mgbe_update_l4_port_no(struct osi_core_priv_data *osi_core,
 }
 #endif /* !OSI_STRIPPED_LIB */
 
-/**
- * @brief mgbe_config_l3_l4_filter_enable - register write to enable L3/L4
- *	filters.
- *
- * Algorithm: This routine to enable/disable L3/l4 filter
- *
- * @param[in] osi_core: OSI core private data structure.
- * @note MAC should be init and started. see osi_start_mac()
- *
- * @retval 0 on success
- * @retval -1 on failure.
- */
-static nve32_t mgbe_config_l3_l4_filter_enable(
-				struct osi_core_priv_data *const osi_core,
-				nveu32_t filter_enb_dis)
-{
-	nveu32_t value = 0U;
-	void *base = osi_core->base;
-
-	/* validate filter_enb_dis argument */
-	if (filter_enb_dis != OSI_ENABLE && filter_enb_dis != OSI_DISABLE) {
-		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
-			"Invalid filter_enb_dis value\n",
-			filter_enb_dis);
-		return -1;
-	}
-
-	value = osi_readla(osi_core, (nveu8_t *)base + MGBE_MAC_PFR);
-	value &= ~(MGBE_MAC_PFR_IPFE);
-	value |= ((filter_enb_dis << MGBE_MAC_PFR_IPFE_SHIFT) &
-		  MGBE_MAC_PFR_IPFE);
-	osi_writela(osi_core, value, (nveu8_t *)base + MGBE_MAC_PFR);
-
-	return 0;
-}
 /**
  * @brief mgbe_set_dcs - check and update dma routing register
  *
@@ -5465,7 +5430,6 @@ void mgbe_init_core_ops(struct core_ops *ops)
 	ops->handle_common_intr = mgbe_handle_common_intr;
 	ops->pad_calibrate = mgbe_pad_calibrate;
 	ops->update_mac_addr_low_high_reg = mgbe_update_mac_addr_low_high_reg;
-	ops->config_l3_l4_filter_enable = mgbe_config_l3_l4_filter_enable;
 	ops->config_l3_filters = mgbe_config_l3_filters;
 	ops->adjust_mactime = mgbe_adjust_mactime;
 	ops->read_mmc = mgbe_read_mmc;
diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h
index 74fb4f2..8a2a498 100644
--- a/osi/core/mgbe_core.h
+++ b/osi/core/mgbe_core.h
@@ -24,6 +24,7 @@
 #define MGBE_CORE_H_
 
 #ifndef OSI_STRIPPED_LIB
+#define MGBE_MAC_PFR				0x0008
 #define MGBE_MAC_RX_FLW_CTRL			0x0090
 #define MGBE_MAC_QX_TX_FLW_CTRL(x)		((0x0004U * (x)) + 0x0070U)
 #define MGBE_MAC_ARPPA				0x0C10
@@ -69,6 +70,9 @@
 #define MGBE_MTL_FPE_CTS			0x1090
 #define MGBE_MTL_FPE_ADV			0x1094
 
+#define MGBE_MAC_PFR_VTFE			OSI_BIT(16)
+#define MGBE_MAC_PFR_IPFE			OSI_BIT(20)
+#define MGBE_MAC_PFR_IPFE_SHIFT			20
 #define MGBE_MTL_TCQ_ETS_CR_AVALG_SHIFT		0U
 #define MGBE_MTL_QINT_TXUNIFS			OSI_BIT(0)
 #define MGBE_MTL_TX_OP_MODE_Q2TCMAP		(OSI_BIT(10) | OSI_BIT(9) |\
@@ -382,7 +386,6 @@
  */
 #define MGBE_MAC_TMCR			0x0000
 #define MGBE_MAC_RMCR			0x0004
-#define MGBE_MAC_PFR			0x0008
 #define MGBE_MAC_VLAN_TR		0x0050
 #define MGBE_MAC_VLANTIR		0x0060
 #define MGBE_MAC_RQC0R			0x00A0
@@ -598,9 +601,6 @@
 #define MGBE_DMA_ISR_DCH0_DCH15_MASK		0x3FFU
 #define MGBE_DMA_CHX_STATUS_TI			OSI_BIT(0)
 #define MGBE_DMA_CHX_STATUS_RI			OSI_BIT(6)
-#define MGBE_MAC_PFR_VTFE			OSI_BIT(16)
-#define MGBE_MAC_PFR_IPFE			OSI_BIT(20)
-#define MGBE_MAC_PFR_IPFE_SHIFT			20
 #define MGBE_MAC_ADDRH_AE			OSI_BIT(31)
 #define MGBE_MAC_ADDRH_SA			OSI_BIT(30)
 #define MGBE_MAC_ADDRH_SA_SHIFT			30
diff --git a/osi/core/osi_hal.c b/osi/core/osi_hal.c
index ca9a8dc..c8592fc 100644
--- a/osi/core/osi_hal.c
+++ b/osi/core/osi_hal.c
@@ -565,11 +565,9 @@ static nve32_t osi_l3l4_filter(struct osi_core_priv_data *const osi_core,
 	}
 
 	if (osi_core->l3l4_filter_bitmask != OSI_DISABLE) {
-		ret = l_core->ops_p->config_l3_l4_filter_enable(osi_core,
-								OSI_ENABLE);
+		ret = hw_config_l3_l4_filter_enable(osi_core, OSI_ENABLE);
 	} else {
-		ret = l_core->ops_p->config_l3_l4_filter_enable(osi_core,
-								OSI_DISABLE);
+		ret = hw_config_l3_l4_filter_enable(osi_core, OSI_DISABLE);
 	}
 
 	return ret;