diff --git a/osi/core/xpcs.c b/osi/core/xpcs.c index 961cdda..9d8703f 100644 --- a/osi/core/xpcs.c +++ b/osi/core/xpcs.c @@ -1080,6 +1080,43 @@ nve32_t xlgpcs_init(struct osi_core_priv_data *osi_core) value |= OSI_BIT(0); osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base + T26X_XPCS_WRAP_CONFIG_0); + + osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_4_CDR_RESET_WIDTH, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_4); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_1_IDDQ_SLEEP_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_1); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_1_IDDQ_SLEEP_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_1); + value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_P_DN_0); + value = value & XPCS_WRAP_UPHY_RX_CTRL_P_DN_0_RXEN_SLEEP_DLY; + value = value | XPCS_WRAP_UPHY_RX_CTRL_P_DN_0_SLEEP_IDDQ_DLY; + osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_P_DN_0); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_P_DN_0_DATARDY_SLEEP_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_0); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_P_DN_1_DATAEN_RDY_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_1); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_P_DN_2_SLEEP_IDDQ_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_2); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_P_DN_3_IDDQ_P_DN_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_3); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_P_DN_4_CAL_DONE_SLP_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_4); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_4_CAL_EN_HIGH_LOW_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_4); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_5_CAL_EN_LOW_DTRDY_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_5); osi_writela(osi_core, XLGPCS_WRAP_UPHY_TO_CTRL2_EQ_DONE_TOV, (nveu8_t *)osi_core->xpcs_base + T26X_XPCS_WRAP_UPHY_T0_CTRL_2_0); @@ -1088,12 +1125,35 @@ nve32_t xlgpcs_init(struct osi_core_priv_data *osi_core) value |= XLGPCS_WRAP_UPHY_RX_CTRL5_RX_EQ_ENABLE; osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base + T26X_XPCS_WRAP_UPHY_RX_CTRL_5_0); + osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_7_EQ_RESET_WIDTH, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_7); + osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_8_EQ_TRAIN_EN_DELAY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_8); + osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_9_EQ_TRAIN_EN_HILO_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_9); + osi_writela(osi_core, XPCS_WRAP_UPHY_TX_CTRL_3_DATAREADY_DATAEN_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_3); + osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_TX_CTRL_2); + osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_2); + osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_3_CAL_DONE_DATA_EN_DLY, + (nveu8_t *)osi_core->xpcs_base + + T26X_XPCS_WRAP_UPHY_RX_CTRL_3); + } if (xpcs_lane_bring_up(osi_core) < 0) { ret = -1; goto fail; } + } /* As a part of bringup debug, below programming is leading to the failures in block lock diff --git a/osi/core/xpcs.h b/osi/core/xpcs.h index 295139f..644c1b7 100644 --- a/osi/core/xpcs.h +++ b/osi/core/xpcs.h @@ -53,6 +53,25 @@ #define T26X_XPCS_WRAP_CONFIG_0 0x8094 #define T26X_XPCS_WRAP_UPHY_T0_CTRL_2_0 0x8078 #define T26X_XPCS_WRAP_UPHY_RX_CTRL_5_0 0x804c +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_4 0x8048 +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_1 0x8004 +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_1 0x803c +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_P_DN_0 0x806c +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_0 0x8020 +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_1 0x8024 +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_2 0x8028 +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_3 0x802c +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_P_DN_4 0x8030 +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_4 0x8010 +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_5 0x8014 +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_7 0x805c +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_8 0x8060 +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_9 0x8064 +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_3 0x800c +#define T26X_XPCS_WRAP_UPHY_TX_CTRL_2 0x8008 +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_2 0x8040 +#define T26X_XPCS_WRAP_UPHY_RX_CTRL_3 0x8044 + /** @} */ @@ -98,6 +117,23 @@ #define XLGPCS_WRAP_UPHY_TO_CTRL2_EQ_DONE_TOV 0xFFFFU #define XLGPCS_WRAP_UPHY_RX_CTRL5_RX_EQ_ENABLE 0x80000000U +#define XPCS_WRAP_UPHY_RX_CTRL_4_CDR_RESET_WIDTH 0x21U +#define XPCS_WRAP_UPHY_TX_CTRL_1_IDDQ_SLEEP_DLY 0x29U +#define XPCS_WRAP_UPHY_RX_CTRL_P_DN_0_RXEN_SLEEP_DLY 0xFFFF0000U +#define XPCS_WRAP_UPHY_RX_CTRL_P_DN_0_SLEEP_IDDQ_DLY 0xA1U +#define XPCS_WRAP_UPHY_TX_CTRL_P_DN_0_DATARDY_SLEEP_DLY 0x29U +#define XPCS_WRAP_UPHY_TX_CTRL_P_DN_1_DATAEN_RDY_DLY 0x81U +#define XPCS_WRAP_UPHY_TX_CTRL_P_DN_2_SLEEP_IDDQ_DLY 0xA1U +#define XPCS_WRAP_UPHY_TX_CTRL_P_DN_3_IDDQ_P_DN_DLY 0x285U +#define XPCS_WRAP_UPHY_TX_CTRL_P_DN_4_CAL_DONE_SLP_DLY 0x29U +#define XPCS_WRAP_UPHY_TX_CTRL_4_CAL_EN_HIGH_LOW_DLY 0x19U +#define XPCS_WRAP_UPHY_TX_CTRL_5_CAL_EN_LOW_DTRDY_DLY 0x79U +#define XPCS_WRAP_UPHY_RX_CTRL_7_EQ_RESET_WIDTH 0x29U +#define XPCS_WRAP_UPHY_RX_CTRL_8_EQ_TRAIN_EN_DELAY 0x29U +#define XPCS_WRAP_UPHY_RX_CTRL_9_EQ_TRAIN_EN_HILO_DLY 0x19U +#define XPCS_WRAP_UPHY_TX_CTRL_3_DATAREADY_DATAEN_DLY 0x82U +#define XPCS_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY 0xFBDU +#define XPCS_WRAP_UPHY_RX_CTRL_3_CAL_DONE_DATA_EN_DLY 0x78U #define EQOS_XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8038 #define EQOS_XPCS_WRAP_UPHY_STATUS 0x8064