osi: core: use MDC CR passed from OSD

o Use MDC CR value, which is passed from OSD
o Set CRS for MGBE to generate higher MDC frequencies
o Remove OSI_CMD_MDC_CONFIG related code which is no
longer required.

Bug 5147775

Change-Id: I4763d6ccaee7f5cc078a3542c069d8052d6c3637
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3336068
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>

include/osi_core.h

@@ -102,7 +102,6 @@ typedef my_lint_64		nvel64_t;
 /** @} */
 
 #define OSI_CMD_RESET_MMC		12U
-#define OSI_CMD_MDC_CONFIG		1U
 #define OSI_CMD_MAC_LB			14U
 #define OSI_CMD_FLOW_CTRL		15U
 #define OSI_CMD_CONFIG_TXSTATUS		27U
@@ -316,6 +315,12 @@ typedef my_lint_64		nvel64_t;
 #define TWO_POWER_32		0x100000000ULL
 /* MDIO clause 45 bit */
 #define OSI_MII_ADDR_C45		OSI_BIT(30)
+/** @brief EQOS default MDC CR value - CSR 300-500 MHz, div=204 */
+#define OSI_EQOS_DEFAULT_MDC_CR		0x6U
+/** @brief MGBE default MDC CR value - CSR 400-500 MHz, div=202 */
+#define OSI_MGBE_DEFAULT_MDC_CR		0x5U
+/** @brief Maximum allowed MDC CR value */
+#define OSI_MAX_MDC_CR			0xFU
 /** @} */
 
 /**

osi/core/core_local.h

@@ -207,9 +207,6 @@ struct core_ops {
 	void (*configure_eee)(struct osi_core_priv_data *const osi_core,
 			      const nveu32_t tx_lpi_enabled,
 			      const nveu32_t tx_lpi_timer);
-	/** Called to set MDC clock rate for MDIO operation */
-	void (*set_mdc_clk_rate)(struct osi_core_priv_data *const osi_core,
-				 const nveu64_t csr_clk_rate);
 	/** Called to configure MAC in loopback mode */
 	nve32_t (*config_mac_loopback)(
 				struct osi_core_priv_data *const osi_core,

osi/core/eqos_core.c

@@ -3589,57 +3589,6 @@ static void eqos_configure_eee(struct osi_core_priv_data *const osi_core,
 	}
 }
 
-/**
- * @brief eqos_set_mdc_clk_rate - Derive MDC clock based on provided AXI_CBB clk
- *
- * @note
- * Algorithm:
- *  - MDC clock rate will be populated OSI core private data structure
- *    based on AXI_CBB clock rate.
- *
- * @param[in, out] osi_core: OSI core private data structure.
- * @param[in] csr_clk_rate: CSR (AXI CBB) clock rate.
- *
- * @pre OSD layer needs get the AXI CBB clock rate with OSD clock API
- *   (ex - clk_get_rate())
- *
- * @note
- * API Group:
- * - Initialization: Yes
- * - Run time: No
- * - De-initialization: No
- */
-static void eqos_set_mdc_clk_rate(struct osi_core_priv_data *const osi_core,
-				  const nveu64_t csr_clk_rate)
-{
-	nveu64_t csr_clk_speed = csr_clk_rate / 1000000UL;
-
-	/* store csr clock speed used in programming
-	 * LPI 1us tick timer register
-	 */
-	if (csr_clk_speed <= UINT_MAX) {
-		osi_core->csr_clk_speed = (nveu32_t)csr_clk_speed;
-	}
-	if (csr_clk_speed > 500UL) {
-		osi_core->mdc_cr = EQOS_CSR_500_800M;
-	} else if (csr_clk_speed > 300UL) {
-		osi_core->mdc_cr = EQOS_CSR_300_500M;
-	} else if (csr_clk_speed > 250UL) {
-		osi_core->mdc_cr = EQOS_CSR_250_300M;
-	} else if (csr_clk_speed > 150UL) {
-		osi_core->mdc_cr = EQOS_CSR_150_250M;
-	} else if (csr_clk_speed > 100UL) {
-		osi_core->mdc_cr = EQOS_CSR_100_150M;
-	} else if (csr_clk_speed > 60UL) {
-		osi_core->mdc_cr = EQOS_CSR_60_100M;
-	} else if (csr_clk_speed > 35UL) {
-		osi_core->mdc_cr = EQOS_CSR_35_60M;
-	} else {
-		/* for CSR < 35mhz */
-		osi_core->mdc_cr = EQOS_CSR_20_35M;
-	}
-}
-
 /**
  * @brief eqos_config_mac_loopback - Configure MAC to support loopback
  *
@@ -4181,7 +4130,6 @@ void eqos_init_core_ops(struct core_ops *ops)
 	ops->config_ptp_offload = eqos_config_ptp_offload;
 	ops->config_vlan_filtering = eqos_config_vlan_filtering;
 	ops->configure_eee = eqos_configure_eee;
-	ops->set_mdc_clk_rate = eqos_set_mdc_clk_rate;
 	ops->config_mac_loopback = eqos_config_mac_loopback;
 	ops->config_rss = eqos_config_rss;
 	ops->get_rss = eqos_get_rss;

osi/core/eqos_core.h

@@ -109,21 +109,6 @@
 #define EQOS_MAC_RQC1R_PTPQ			(OSI_BIT(6) | OSI_BIT(5) | \
 						 OSI_BIT(4))
 #define EQOS_MAC_RQC1R_PTPQ_SHIFT		4U
-/**
- * @addtogroup EQOS-MDC MDC Clock Selection defines
- *
- * @brief MDC Clock defines
- * @{
- */
-#define EQOS_CSR_60_100M	0x0	/* MDC = clk_csr/42 */
-#define EQOS_CSR_100_150M	0x1	/* MDC = clk_csr/62 */
-#define EQOS_CSR_20_35M		0x2	/* MDC = clk_csr/16 */
-#define EQOS_CSR_35_60M		0x3	/* MDC = clk_csr/26 */
-#define EQOS_CSR_150_250M	0x4	/* MDC = clk_csr/102 */
-#define EQOS_CSR_250_300M	0x5	/* MDC = clk_csr/124 */
-#define EQOS_CSR_300_500M	0x6	/* MDC = clk_csr/204 */
-#define EQOS_CSR_500_800M	0x7	/* MDC = clk_csr/324 */
-/** @} */
 #define EQOS_MAC_LPI_CSR_LPITE			OSI_BIT(20)
 #define EQOS_MAC_LPI_CSR_LPITXA			OSI_BIT(19)
 #define EQOS_MAC_LPI_CSR_PLS			OSI_BIT(17)

osi/core/mgbe_core.c

@@ -4422,14 +4422,12 @@ static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *const osi_core,
 	      (((nveu32_t)MGBE_MDIO_SCCD_CMD_WR) << MGBE_MDIO_SCCD_CMD_SHIFT) |
 	      MGBE_MDIO_SCCD_SBUSY;
 
-	/**
+	reg |= (((osi_core->mdc_cr) & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT);
-	 * On FPGA AXI/APB clock is 13MHz. To achive maximum MDC clock
+
-	 * of 2.5MHz need to enable CRS and CR to be set to 1.
+	if (osi_core->mdc_cr > 7U) {
-	 * On Silicon AXI/APB clock is 408MHz. To achive maximum MDC clock
+		/* Set clock range select for higher frequencies */
-	 * of 2.5MHz only CR need to be set to 5.
+		reg |= MGBE_MDIO_SCCD_CRS;
-	 */
+	}
-	reg &= ~MGBE_MDIO_SCCD_CRS;
-	reg |= ((((nveu32_t)0x5U) & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT);
 
 	osi_writela(osi_core, reg, (nveu8_t *)
 		    osi_core->base + MGBE_MDIO_SCCD);
@@ -4492,14 +4490,12 @@ static nve32_t mgbe_read_phy_reg(struct osi_core_priv_data *const osi_core,
 	reg = (((nveu32_t)MGBE_MDIO_SCCD_CMD_RD) << MGBE_MDIO_SCCD_CMD_SHIFT) |
 	       MGBE_MDIO_SCCD_SBUSY;
 
-	 /**
+	reg |= ((osi_core->mdc_cr & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT);
-         * On FPGA AXI/APB clock is 13MHz. To achive maximum MDC clock
+
-         * of 2.5MHz need to enable CRS and CR to be set to 1.
+	if (osi_core->mdc_cr > 7U) {
-         * On Silicon AXI/APB clock is 408MHz. To achive maximum MDC clock
+		/* Set clock range select for higher frequencies */
-         * of 2.5MHz only CR need to be set to 5.
+		reg |= MGBE_MDIO_SCCD_CRS;
-         */
+	}
-	reg &= ~MGBE_MDIO_SCCD_CRS;
-	reg |= ((((nveu32_t)0x5U) & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT);
 
 	osi_writela(osi_core, reg, (nveu8_t *)
 		    osi_core->base + MGBE_MDIO_SCCD);
@@ -5078,13 +5074,6 @@ static nve32_t mgbe_config_rx_crc_check(OSI_UNUSED
 {
 	return 0;
 }
-
-static void mgbe_set_mdc_clk_rate(OSI_UNUSED
-				  struct osi_core_priv_data *const osi_core,
-				  OSI_UNUSED
-				  const nveu64_t csr_clk_rate)
-{
-}
 #endif /* !OSI_STRIPPED_LIB */
 
 #if defined(MACSEC_SUPPORT)
@@ -5213,7 +5202,6 @@ void mgbe_init_core_ops(struct core_ops *ops)
 	ops->config_ptp_offload = mgbe_config_ptp_offload;
 	ops->config_vlan_filtering = mgbe_config_vlan_filtering;
 	ops->configure_eee = mgbe_configure_eee;
-	ops->set_mdc_clk_rate = mgbe_set_mdc_clk_rate;
 	ops->config_mac_loopback = mgbe_config_mac_loopback;
 	ops->config_rss = mgbe_config_rss;
 	ops->get_rss = mgbe_get_rss;

osi/core/osi_hal.c

@@ -2792,9 +2792,6 @@ nve32_t OSI_CMD_ADJ_FREQ_count = 0;
  * @note
  * Algorithm:
  *  - Handle runtime commands to OSI
- *  - OSI_CMD_MDC_CONFIG
- *	Derive MDC clock based on provided AXI_CBB clk
- *	arg1_u32 - CSR (AXI CBB) clock rate.
  *  - OSI_CMD_RESTORE_REGISTER
  *	Restore backup of MAC MMIO address space
  *  - OSI_CMD_POLL_FOR_MAC_RST
@@ -2961,11 +2958,6 @@ static nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core,
 
 	switch (ioctl_data->cmd) {
 #ifndef OSI_STRIPPED_LIB
-	case OSI_CMD_MDC_CONFIG:
-		ops_p->set_mdc_clk_rate(osi_core, ioctl_data->arg5_u64);
-		ret = 0;
-		break;
-
 	case OSI_CMD_MAC_LB:
 		ret = conf_mac_loopback(osi_core, ioctl_data->arg1_u32);
 		break;