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osi: core: Add a BYPASS FRP entry for XDCS

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Issue:
MAC Filters DCH/XDCS is not routing
to the proper DMA channel
after FRP enable.

Fix:
As per HW's suggestion add a BYPASS entry after user entries.

Bug 3899802

Change-Id: I330490ff94ed719ba3fc27f38b6dfaf1bc37369b
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2826024
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Mohan Thadikamalla
2022-12-12 12:54:11 +05:30
committed by Bhadram Varka
parent f0af726970
commit 29242b7c12
1 changed files with 47 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
osi/core/frp.c
View File

@@ -370,8 +370,10 @@ done:
static nve32_t frp_hw_write(struct osi_core_priv_data *const osi_core,
struct core_ops *const ops_p)
{
nve32_t ret, tmp;
nve32_t ret = 0;
nve32_t tmp = 0;
struct osi_core_frp_entry *entry;
struct osi_core_frp_data bypass_entry = {};
nveu32_t frp_cnt = osi_core->frp_cnt, i = OSI_NONE;
/* Disable the FRP in HW */
@@ -384,10 +386,21 @@ static nve32_t frp_hw_write(struct osi_core_priv_data *const osi_core,
goto hw_write_enable_frp;
}
/* Check space for XCS BYPASS rule */
if ((frp_cnt + 1U) > OSI_FRP_MAX_ENTRY) {
ret = -1;
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"No space for rules\n", OSI_NONE);
goto error;
}
/* Check HW table size for non-zero */
if (frp_cnt != 0U) {
/* Write FRP entries into HW */
for (i = 0; i < frp_cnt; i++) {
entry = &osi_core->frp_table[i];
ret = ops_p->update_frp_entry(osi_core, i, &entry->data);
ret = ops_p->update_frp_entry(osi_core, i,
&entry->data);
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Fail to update FRP entry\n",
@@ -396,8 +409,20 @@ static nve32_t frp_hw_write(struct osi_core_priv_data *const osi_core,
}
}
/* Write BYPASS rule for XDCS */
bypass_entry.match_en = 0x0U;
bypass_entry.accept_frame = 1;
bypass_entry.reject_frame = 1;
ret = ops_p->update_frp_entry(osi_core, frp_cnt, &bypass_entry);
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Fail to update BYPASS entry\n",
OSI_NONE);
goto hw_write_enable_frp;
}
/* Update the NVE */
ret = ops_p->update_frp_nve(osi_core, (frp_cnt - 1U));
ret = ops_p->update_frp_nve(osi_core, frp_cnt);
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Fail to update FRP NVE\n",
@@ -407,6 +432,9 @@ static nve32_t frp_hw_write(struct osi_core_priv_data *const osi_core,
/* Enable the FRP in HW */
hw_write_enable_frp:
tmp = ops_p->config_frp(osi_core, OSI_ENABLE);
}
error:
return (ret < 0) ? ret : tmp;
}
@@ -616,6 +644,9 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core,
pos++;
}
/* Update the frp_cnt entry */
osi_core->frp_cnt = (frp_cnt - count);
/* Write FRP Table into HW */
ret = frp_hw_write(osi_core, ops_p);
if (ret < 0) {
@@ -624,9 +655,6 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core,
OSI_NONE);
}
/* Update the frp_cnt entry */
osi_core->frp_cnt = (frp_cnt - count);
done:
return ret;
}