osi: core: mgbe: Fix 9K Jumbo issue

Issue: Not able to transfer 9K Jumbo frame.
Currently each TxQ is divided into 12KB of size
which leads to not making use of 8KB in total which
is affecting 9K Jumbo

Fix: Instead of using 12KB per TxQ, 128KB is equally
divided among 10 Tx Ques.

Bug 3934258

Change-Id: I86623e2726789d42a683aa755f47d77e04391dc1
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2848255
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Narayan Reddy
2023-01-24 17:15:04 +05:30
committed by mobile promotions
parent 91511ff641
commit 2a82c10c8f
2 changed files with 6 additions and 3 deletions

View File

@@ -1200,8 +1200,8 @@ static nve32_t mgbe_configure_mtl_queue(struct osi_core_priv_data *osi_core,
FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(16U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(16U),
}; };
const nveu32_t tx_fifo_sz[OSI_MGBE_MAX_NUM_QUEUES] = { const nveu32_t tx_fifo_sz[OSI_MGBE_MAX_NUM_QUEUES] = {
FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ,
FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ,
}; };
const nveu32_t rfd_rfa[OSI_MGBE_MAX_NUM_QUEUES] = { const nveu32_t rfd_rfa[OSI_MGBE_MAX_NUM_QUEUES] = {
FULL_MINUS_32_K, FULL_MINUS_32_K,

View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -738,6 +738,9 @@
/** @} */ /** @} */
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
/* TXQ Size 128KB is divided equally across 10 MTL Queues*/
#define TX_FIFO_SZ (((((128U * 1024U)/OSI_MGBE_MAX_NUM_QUEUES)) / 256U) - 1U)
/** /**
* @addtogroup MGBE-MAC MGBE MAC HW feature registers * @addtogroup MGBE-MAC MGBE MAC HW feature registers
* *