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nvthernetrm: Add IVC support for OSI

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In case of virtualization the OSI functions will be handled
at Ethernet Server. Add IVC support where OSD can send
IVC packets to ethernet server. Ethernet Server parses the
messages and calls the corresponding OSI API.

OSI and few DMA API's are updated to support osi_core as an
argument.

Bug 2694285

Change-Id: Ic56b8e9f5f9cd70cc70239b61d756bfa2e998588
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2435281
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
nannaiah
2020-10-22 13:20:56 -07:00
committed by Bhadram Varka
parent 0a1138f879
commit 2a873b3f3d
13 changed files with 2478 additions and 538 deletions
Download Patch File Download Diff File Expand all files Collapse all files

204
include/ivc_core.h Normal file
View File

@@ -0,0 +1,204 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef IVC_CORE_H
#define IVC_CORE_H
#include "osi_core.h"
/**
* @brief Ethernet Maximum IVC BUF
*/
#define ETHER_MAX_IVC_BUF 1024
/**
* @brief IVC maximum arguments
*/
#define MAX_ARGS 10
/**
* @brief IVC commands between OSD & OSI.
*/
enum ivc_cmd {
poll_for_swr = 1,
core_init,
core_deinit,
start_mac,
stop_mac,
handle_common_intr,
set_mode,
set_speed,
pad_calibrate,
config_fw_err_pkts,
config_rxcsum_offload,
config_mac_pkt_filter_reg,
update_mac_addr_low_high_reg,
config_l3_l4_filter_enable,
config_l3_filters,
update_ip4_addr,
update_ip6_addr,
config_l4_filters,
update_l4_port_no,
set_systime_to_mac,
config_addend,
adjust_mactime,
config_tscr,
config_ssir,
read_mmc,
write_phy_reg,
read_phy_reg,
reg_read,
reg_write,
#ifndef OSI_STRIPPED_LIB
config_tx_status,
config_rx_crc_check,
config_flow_control,
config_arp_offload,
validate_regs,
flush_mtl_tx_queue,
set_avb_algorithm,
get_avb_algorithm,
config_vlan_filtering,
update_vlan_id,
reset_mmc,
configure_eee,
save_registers,
restore_registers,
set_mdc_clk_rate,
config_mac_loopback,
#endif /* !OSI_STRIPPED_LIB */
};
/**
* @brief IVC arguments structure.
*/
typedef struct ivc_args {
/** Number of arguments */
nveu32_t count;
/** arguments */
nveu32_t arguments[MAX_ARGS];
} ivc_args;
/**
* @brief IVC core argument structure.
*/
typedef struct ivc_core_args {
/** Number of MTL queues enabled in MAC */
nveu32_t num_mtl_queues;
/** Array of MTL queues */
nveu32_t mtl_queues[OSI_EQOS_MAX_NUM_CHANS];
/** List of MTL Rx queue mode that need to be enabled */
nveu32_t rxq_ctrl[OSI_EQOS_MAX_NUM_CHANS];
/** Rx MTl Queue mapping based on User Priority field */
nveu32_t rxq_prio[OSI_EQOS_MAX_NUM_CHANS];
/** Ethernet MAC address */
nveu8_t mac_addr[OSI_ETH_ALEN];
/** Tegra Pre-si platform info */
nveu32_t pre_si;
/** VLAN tag stripping enable(1) or disable(0) */
nveu32_t strip_vlan_tag;
/** pause frame support */
nveu32_t pause_frames;
/** Current flow control settings */
nveu32_t flow_ctrl;
/** Rx fifo size */
nveu32_t rx_fifo_size;
/** Tx fifo size */
nveu32_t tx_fifo_size;
} ivc_core_args;
/**
* @brief IVC message structure.
*/
typedef struct ivc_msg_common {
/**
* Status code returned as part of response message of IVC messages.
* Status code value is "0" for success and "< 0" for failure.
*/
nveu32_t status;
/**
* ID of the CMD.
*/
nveu32_t cmd;
/**
* message count, used for debug
*/
nveu32_t count;
union {
/**
* IVC argument structure
*/
ivc_args args;
#ifndef OSI_STRIPPED_LIB
/**
* avb algorithm structure
*/
struct osi_core_avb_algorithm avb_algo;
#endif
/**
* OSI filter structure
*/
struct osi_filter filter;
/**
* core argument structure
*/
ivc_core_args init_args;
}data;
} ivc_msg_common;
/**
* @brief osd_ivc_send_cmd - OSD ivc send cmd
*
* @param[in] priv: OSD private data
* @param[in] data: data
* @param[in] len: length of data
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*
* @retval ivc status
* @retval -1 on failure
*/
nve32_t osd_ivc_send_cmd(void *priv, void *data, nveu32_t len);
/**
* @brief ivc_get_core_safety_config - Get core safety config
*
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*/
void *ivc_get_core_safety_config(void);
/**
* @brief ivc_get_hw_core_ops - Get hw core operations
*
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*/
struct osi_core_ops *ivc_get_hw_core_ops(void);
#endif /* IVC_CORE_H */

55
include/osi_common.h
View File

@@ -566,44 +566,6 @@ struct osi_hw_features {
nveu32_t num_tbs_ch;
};
/**
* @brief common_get_mac_version - Reading MAC version
*
* @note
* Algorithm:
* - Reads MAC version and check whether its valid or not.
*
* @param[in] addr: io-remap MAC base address.
* @param[out] mac_ver: holds mac version.
*
* @pre MAC has to be out of reset.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 on success
* @retval -1 on failure.
*/
nve32_t common_get_mac_version(void *addr, nveu32_t *mac_ver);
/**
* @brief comon_get_hw_features - Reading MAC HW features
*
* @param[in] base: io-remap MAC base address.
* @param[out] hw_feat: holds the supported features of the hardware.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*
* @pre MAC has to be out of reset.
*/
void common_get_hw_features(void *base, struct osi_hw_features *hw_feat);
/**
* @brief osi_memset - osi memset
*
@@ -618,4 +580,19 @@ void common_get_hw_features(void *base, struct osi_hw_features *hw_feat);
* - De-initialization: No
*/
void osi_memset(void *s, nveu32_t c, nveu64_t count);
#endif /* INCLUDED_OSI_COMMON_H */
/**
* @brief osi_memcpy - osi memcpy
*
* @param[out] dest: destination pointer
* @param[in] src: source pointer
* @param[in] n: number bytes of source
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
void osi_memcpy(void *dest, void *src, int n);
#endif /* OSI_COMMON_H */

51
include/osi_core.h
View File

@@ -183,7 +183,7 @@ struct osi_filter {
* Filter index must be between 0 - 127 */
nveu32_t index;
/** Ethernet MAC address to be added */
const nveu8_t *mac_address;
nveu8_t mac_address[OSI_ETH_ALEN];
/** Indicates dma channel routing enable(1) disable (0) */
nveu32_t dma_routing;
/** indicates dma channel number to program */
@@ -281,8 +281,7 @@ struct osi_core_avb_algorithm {
*/
struct osi_core_ops {
/** Called to poll for software reset bit */
nve32_t (*poll_for_swr)(struct osi_core_priv_data *const osi_core,
nve32_t pre_si);
nve32_t (*poll_for_swr)(struct osi_core_priv_data *const osi_core);
/** Called to initialize MAC and MTL registers */
nve32_t (*core_init)(struct osi_core_priv_data *const osi_core,
const nveu32_t tx_fifo_size,
@@ -290,16 +289,17 @@ struct osi_core_ops {
/** Called to deinitialize MAC and MTL registers */
void (*core_deinit)(struct osi_core_priv_data *const osi_core);
/** Called to start MAC Tx and Rx engine */
void (*start_mac)(void *addr);
void (*start_mac)(struct osi_core_priv_data *const osi_core);
/** Called to stop MAC Tx and Rx engine */
void (*stop_mac)(void *addr);
void (*stop_mac)(struct osi_core_priv_data *const osi_core);
/** Called to handle common interrupt */
void (*handle_common_intr)(struct osi_core_priv_data *const osi_core);
/** Called to set the mode at MAC (full/duplex) */
nve32_t (*set_mode)(struct osi_core_priv_data *const osi_core,
const nve32_t mode);
/** Called to set the speed (10/100/1000) at MAC */
void (*set_speed)(void *ioaddr, const nve32_t speed);
void (*set_speed)(struct osi_core_priv_data *const osi_core,
const nve32_t speed);
/** Called to do pad caliberation */
nve32_t (*pad_calibrate)(struct osi_core_priv_data *const osi_core);
/** Called to configure MTL RxQ to forward the err pkt */
@@ -319,7 +319,8 @@ struct osi_core_ops {
struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter);
/** Called to configure l3/L4 filter */
nve32_t (*config_l3_l4_filter_enable)(void *base,
nve32_t (*config_l3_l4_filter_enable)(
struct osi_core_priv_data *const osi_core,
const nveu32_t enable);
/** Called to configure L3 filter */
nve32_t (*config_l3_filters)(struct osi_core_priv_data *const osi_core,
@@ -367,7 +368,8 @@ struct osi_core_ops {
const nveu32_t sec,
const nveu32_t nsec);
/** Called to configure the TimeStampControl register */
void (*config_tscr)(void *addr, const nveu32_t ptp_filter);
void (*config_tscr)(struct osi_core_priv_data *const osi_core,
const nveu32_t ptp_filter);
/** Called to configure the sub second increment register */
void (*config_ssir)(struct osi_core_priv_data *const osi_core);
/** Called to update MMC counter from HW register */
@@ -381,6 +383,13 @@ struct osi_core_ops {
nve32_t (*read_phy_reg)(struct osi_core_priv_data *const osi_core,
const nveu32_t phyaddr,
const nveu32_t phyreg);
/** Called to read reg */
nveu32_t (*read_reg)(struct osi_core_priv_data *const osi_core,
const nve32_t reg);
/** Called to write reg */
nveu32_t (*write_reg)(struct osi_core_priv_data *const osi_core,
const nveu32_t val,
const nve32_t reg);
#ifndef OSI_STRIPPED_LIB
/** Called periodically to read and validate safety critical
* registers against last written value */
@@ -406,8 +415,7 @@ struct osi_core_ops {
struct osi_core_priv_data *const osi_core,
const nveu32_t flw_ctrl);
/** Called to enable/disable HW ARP offload feature */
nve32_t (*config_arp_offload)(const nveu32_t mac_ver,
struct osi_core_priv_data *const osi_core,
nve32_t (*config_arp_offload)(struct osi_core_priv_data *const osi_core,
const nveu32_t enable,
const nveu8_t *ip_addr);
/** Called to configure VLAN filtering */
@@ -417,7 +425,8 @@ struct osi_core_ops {
const nveu32_t perfect_hash_filtering,
const nveu32_t perfect_inverse_match);
/** called to update VLAN id */
nve32_t (*update_vlan_id)(void *base, const nveu32_t vid);
nve32_t (*update_vlan_id)(struct osi_core_priv_data *const osi_core,
const nveu32_t vid);
/** Called to reset MMC HW counter structure */
void (*reset_mmc)(struct osi_core_priv_data *const osi_core);
/** Called to configure EEE Tx LPI */
@@ -432,7 +441,9 @@ struct osi_core_ops {
void (*set_mdc_clk_rate)(struct osi_core_priv_data *const osi_core,
const nveu64_t csr_clk_rate);
/** Called to configure MAC in loopback mode */
nve32_t (*config_mac_loopback)(void *addr, const nveu32_t lb_mode);
nve32_t (*config_mac_loopback)(
struct osi_core_priv_data *const osi_core,
const nveu32_t lb_mode);
#endif /* !OSI_STRIPPED_LIB */
};
@@ -513,6 +524,8 @@ struct osd_core_ops {
void (*usleep_range)(nveu64_t umin, nveu64_t umax);
/** msleep callback */
void (*msleep)(nveu32_t msec);
/** ivcsend callback*/
nve32_t (*ivc_send)(void *priv, void *data, nveu32_t len);
};
/**
@@ -576,7 +589,9 @@ struct osi_core_priv_data {
*/
nveu32_t csr_clk_speed;
/** Tegra Pre-si platform info */
nve32_t pre_si;
nveu32_t pre_si;
/** Flag which decides virtualization is enabled(1) or disabled(0) */
nveu32_t use_virtualization;
};
/**
@@ -1386,7 +1401,7 @@ nve32_t osi_l3l4_filter(struct osi_core_priv_data *const osi_core,
* Algorithm:
* - Reads MAC version and check whether its valid or not.
*
* @param[in] addr: io-remap MAC base address.
* @param[in] osi_core: OSI core private data structure.
* @param[out] mac_ver: holds mac version.
*
* @pre MAC has to be out of reset.
@@ -1411,12 +1426,13 @@ nve32_t osi_l3l4_filter(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
nve32_t osi_get_mac_version(void *addr, nveu32_t *mac_ver);
nve32_t osi_get_mac_version(struct osi_core_priv_data *const osi_core,
nveu32_t *mac_ver);
/**
* @brief osi_get_hw_features - Reading MAC HW features
*
* @param[in] base: io-remap MAC base address.
* @param[in] osi_core: OSI core private data structure.
* @param[out] hw_feat: holds the supported features of the hardware.
*
* @pre MAC has to be out of reset.
@@ -1439,7 +1455,8 @@ nve32_t osi_get_mac_version(void *addr, nveu32_t *mac_ver);
* - De-initialization: No
*
*/
void osi_get_hw_features(void *base, struct osi_hw_features *hw_feat);
void osi_get_hw_features(struct osi_core_priv_data *const osi_core,
struct osi_hw_features *hw_feat);
#ifndef OSI_STRIPPED_LIB
/**

10
include/osi_dma.h
View File

@@ -398,7 +398,8 @@ struct osi_dma_priv_data;
*/
struct osi_dma_chan_ops {
/** Called to set Transmit Ring length */
void (*set_tx_ring_len)(void *addr, nveu32_t chan,
void (*set_tx_ring_len)(struct osi_dma_priv_data *osi_dma,
nveu32_t chan,
nveu32_t len);
/** Called to set Transmit Ring Base address */
void (*set_tx_ring_start_addr)(void *addr, nveu32_t chan,
@@ -407,7 +408,8 @@ struct osi_dma_chan_ops {
void (*update_tx_tailptr)(void *addr, nveu32_t chan,
nveu64_t tailptr);
/** Called to set Receive channel ring length */
void (*set_rx_ring_len)(void *addr, nveu32_t chan,
void (*set_rx_ring_len)(struct osi_dma_priv_data *osi_dma,
nveu32_t chan,
nveu32_t len);
/** Called to set receive channel ring base address */
void (*set_rx_ring_start_addr)(void *addr, nveu32_t chan,
@@ -424,9 +426,9 @@ struct osi_dma_chan_ops {
/** Called to enable DMA Rx channel interrupts at wrapper level */
void (*enable_chan_rx_intr)(void *addr, nveu32_t chan);
/** Called to start the Tx/Rx DMA */
void (*start_dma)(void *addr, nveu32_t chan);
void (*start_dma)(struct osi_dma_priv_data *osi_dma, nveu32_t chan);
/** Called to stop the Tx/Rx DMA */
void (*stop_dma)(void *addr, nveu32_t chan);
void (*stop_dma)(struct osi_dma_priv_data *osi_dma, nveu32_t chan);
/** Called to initialize the DMA channel */
nve32_t (*init_dma_channel)(struct osi_dma_priv_data *osi_dma);
/** Called to set Rx buffer length */

104
osi/common/common.h
View File

@@ -24,6 +24,8 @@
#include <osi_common.h>
struct osi_core_priv_data;
/**
* @brief osi_lock_init - Initialize lock to unlocked state.
*
@@ -142,6 +144,108 @@ static inline void osi_writel(nveu32_t val, void *addr)
*(volatile nveu32_t *)addr = val;
}
/**
* @brief osi_read_reg - Read a MAC register.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] addr: MAC register
*
* @note
* Traceability Details: TODO
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*
* @retval data from MAC register on success
* @retval -1 on failure
*/
nveu32_t osi_read_reg(struct osi_core_priv_data *const osi_core,
const nve32_t addr);
/**
* @brief osi_write_reg - Write a MAC register.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] val: MAC register value
* @param[in] addr: MAC register
*
* @note
* Traceability Details: TODO
*
* @note
* Classification:
* - Interrupt: No
* - Signal handler: No
* - Thread safe: No
* - Required Privileges: None
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval data from MAC register on success
* @retval -1 on failure
*/
nveu32_t osi_write_reg(struct osi_core_priv_data *const osi_core,
const nveu32_t val, const nve32_t addr);
#ifdef ETHERNET_SERVER
nveu32_t osi_readla(void *priv, void *addr);
void osi_writela(void *priv, nveu32_t val, void *addr);
#else
/**
* @brief osi_readla - Read a memory mapped register.
*
* @ note
* The difference between osi_readla & osi_readl is osi_core argument.
* In case of ethernet server, osi_core used to define policy for each VM.
* In case of non virtualization osi_core argument is ignored.
*
* @param[in] priv: Priv address.
* @param[in] addr: Memory mapped address.
*
* @note Physical address has to be memmory mapped.
*
* @return Data from memory mapped register - success.
*/
static inline nveu32_t osi_readla(void *priv, void *addr)
{
return *(volatile nveu32_t *)addr;
}
/**
*
* @ note
* @brief osi_writela - Write to a memory mapped register.
* The difference between osi_writela & osi_writel is osi_core argument.
* In case of ethernet server, osi_core used to define policy for each VM.
* In case of non virtualization osi_core argument is ignored.
*
* @param[in] priv: Priv address.
* @param[in] val: Value to be written.
* @param[in] addr: Memory mapped address.
*
* @note Physical address has to be memmory mapped.
*/
static inline void osi_writela(void *priv, nveu32_t val, void *addr)
{
*(volatile nveu32_t *)addr = val;
}
#endif
/**
* @brief is_valid_mac_version - Check if read MAC IP is valid or not.
*

110
osi/common/osi_common.c
View File

@@ -24,105 +24,7 @@
#include "eqos_common.h"
#include "../osi/common/common.h"
void common_get_hw_features(void *base, struct osi_hw_features *hw_feat)
{
nveu32_t mac_hfr0;
nveu32_t mac_hfr1;
nveu32_t mac_hfr2;
/* TODO: need to add HFR3 */
mac_hfr0 = osi_readl((nveu8_t *)base + EQOS_MAC_HFR0);
mac_hfr1 = osi_readl((nveu8_t *)base + EQOS_MAC_HFR1);
mac_hfr2 = osi_readl((nveu8_t *)base + EQOS_MAC_HFR2);
hw_feat->mii_sel =
((mac_hfr0 >> 0) & EQOS_MAC_HFR0_MIISEL_MASK);
hw_feat->gmii_sel =
((mac_hfr0 >> 1U) & EQOS_MAC_HFR0_GMIISEL_MASK);
hw_feat->hd_sel =
((mac_hfr0 >> 2U) & EQOS_MAC_HFR0_HDSEL_MASK);
hw_feat->pcs_sel =
((mac_hfr0 >> 3U) & EQOS_MAC_HFR0_PCSSEL_MASK);
hw_feat->sma_sel =
((mac_hfr0 >> 5U) & EQOS_MAC_HFR0_SMASEL_MASK);
hw_feat->rwk_sel =
((mac_hfr0 >> 6U) & EQOS_MAC_HFR0_RWKSEL_MASK);
hw_feat->mgk_sel =
((mac_hfr0 >> 7U) & EQOS_MAC_HFR0_MGKSEL_MASK);
hw_feat->mmc_sel =
((mac_hfr0 >> 8U) & EQOS_MAC_HFR0_MMCSEL_MASK);
hw_feat->arp_offld_en =
((mac_hfr0 >> 9U) & EQOS_MAC_HFR0_ARPOFFLDEN_MASK);
hw_feat->ts_sel =
((mac_hfr0 >> 12U) & EQOS_MAC_HFR0_TSSSEL_MASK);
hw_feat->eee_sel =
((mac_hfr0 >> 13U) & EQOS_MAC_HFR0_EEESEL_MASK);
hw_feat->tx_coe_sel =
((mac_hfr0 >> 14U) & EQOS_MAC_HFR0_TXCOESEL_MASK);
hw_feat->rx_coe_sel =
((mac_hfr0 >> 16U) & EQOS_MAC_HFR0_RXCOE_MASK);
hw_feat->mac_addr_sel =
((mac_hfr0 >> 18U) & EQOS_MAC_HFR0_ADDMACADRSEL_MASK);
hw_feat->mac_addr32_sel =
((mac_hfr0 >> 23U) & EQOS_MAC_HFR0_MACADR32SEL_MASK);
hw_feat->mac_addr64_sel =
((mac_hfr0 >> 24U) & EQOS_MAC_HFR0_MACADR64SEL_MASK);
hw_feat->tsstssel =
((mac_hfr0 >> 25U) & EQOS_MAC_HFR0_TSINTSEL_MASK);
hw_feat->sa_vlan_ins =
((mac_hfr0 >> 27U) & EQOS_MAC_HFR0_SAVLANINS_MASK);
hw_feat->act_phy_sel =
((mac_hfr0 >> 28U) & EQOS_MAC_HFR0_ACTPHYSEL_MASK);
hw_feat->rx_fifo_size =
((mac_hfr1 >> 0) & EQOS_MAC_HFR1_RXFIFOSIZE_MASK);
hw_feat->tx_fifo_size =
((mac_hfr1 >> 6U) & EQOS_MAC_HFR1_TXFIFOSIZE_MASK);
hw_feat->adv_ts_hword =
((mac_hfr1 >> 13U) & EQOS_MAC_HFR1_ADVTHWORD_MASK);
hw_feat->addr_64 =
((mac_hfr1 >> 14U) & EQOS_MAC_HFR1_ADDR64_MASK);
hw_feat->dcb_en =
((mac_hfr1 >> 16U) & EQOS_MAC_HFR1_DCBEN_MASK);
hw_feat->sph_en =
((mac_hfr1 >> 17U) & EQOS_MAC_HFR1_SPHEN_MASK);
hw_feat->tso_en =
((mac_hfr1 >> 18U) & EQOS_MAC_HFR1_TSOEN_MASK);
hw_feat->dma_debug_gen =
((mac_hfr1 >> 19U) & EQOS_MAC_HFR1_DMADEBUGEN_MASK);
hw_feat->av_sel =
((mac_hfr1 >> 20U) & EQOS_MAC_HFR1_AVSEL_MASK);
hw_feat->hash_tbl_sz =
((mac_hfr1 >> 24U) & EQOS_MAC_HFR1_HASHTBLSZ_MASK);
hw_feat->l3l4_filter_num =
((mac_hfr1 >> 27U) & EQOS_MAC_HFR1_L3L4FILTERNUM_MASK);
hw_feat->rx_q_cnt =
((mac_hfr2 >> 0) & EQOS_MAC_HFR2_RXQCNT_MASK);
hw_feat->tx_q_cnt =
((mac_hfr2 >> 6U) & EQOS_MAC_HFR2_TXQCNT_MASK);
hw_feat->rx_ch_cnt =
((mac_hfr2 >> 12U) & EQOS_MAC_HFR2_RXCHCNT_MASK);
hw_feat->tx_ch_cnt =
((mac_hfr2 >> 18U) & EQOS_MAC_HFR2_TXCHCNT_MASK);
hw_feat->pps_out_num =
((mac_hfr2 >> 24U) & EQOS_MAC_HFR2_PPSOUTNUM_MASK);
hw_feat->aux_snap_num =
((mac_hfr2 >> 28U) & EQOS_MAC_HFR2_AUXSNAPNUM_MASK);
}
nve32_t common_get_mac_version(void *addr, nveu32_t *mac_ver)
{
nveu32_t version;
nve32_t ret = 0;
version = osi_readl((nveu8_t *)addr + MAC_VERSION) &
MAC_VERSION_SNVER_MASK;
if (is_valid_mac_version(version) == 0) {
return -1;
}
*mac_ver = version;
return ret;
}
void osi_memset(void *s, nveu32_t c, nveu64_t count)
{
@@ -142,7 +44,19 @@ void osi_memset(void *s, nveu32_t c, nveu64_t count)
}
}
void osi_memcpy(void *dest, void *src, int n)
{
char *csrc = (char *)src;
char *cdest = (char *)dest;
int i = 0;
if (src == OSI_NULL || dest == OSI_NULL) {
return;
}
for (i = 0; i < n; i++) {
cdest[i] = csrc[i];
}
}
void common_get_systime_from_mac(void *addr, nveu32_t mac, nveu32_t *sec,
nveu32_t *nsec)

578
osi/core/eqos_core.c
View File

File diff suppressed because it is too large Load Diff

2
osi/core/eqos_core.h
View File

@@ -94,6 +94,7 @@
#define EQOS_MAC_MCR 0x0000
#define EQOS_MAC_EXTR 0x0004
#define EQOS_MAC_PFR 0x0008U
#define EQOS_MAC_WATCH 0x000CU
#define EQOS_MAC_HTR_REG(x) ((0x0004U * (x)) + 0x0010U)
#define EQOS_MAC_VLAN_TAG 0x0050
#define EQOS_MAC_VLANTIR 0x0060
@@ -167,6 +168,7 @@
* @{
*/
#define EQOS_CLOCK_CTRL_0 0x8000U
#define EQOS_APB_ERR_STATUS 0x8214U
#define EQOS_AXI_ASID_CTRL 0x8400U
#define EQOS_AXI_ASID1_CTRL 0x8404U
#define EQOS_PAD_CRTL 0x8800U

1492
osi/core/ivc_core.c Normal file
View File

File diff suppressed because it is too large Load Diff

178
osi/core/osi_core.c
View File

@@ -23,6 +23,7 @@
#include <osi_core.h>
#include <osd.h>
#include <local_common.h>
#include <ivc_core.h>
nve32_t osi_write_phy_reg(struct osi_core_priv_data *const osi_core,
const nveu32_t phyaddr, const nveu32_t phyreg,
@@ -75,13 +76,27 @@ nve32_t osi_init_core_ops(struct osi_core_priv_data *const osi_core)
}
if (osi_core->mac == OSI_MAC_HW_EQOS) {
if (osi_core->use_virtualization == OSI_DISABLE) {
/* Get EQOS HW ops */
osi_core->ops = eqos_get_hw_core_ops();
/* Explicitly set osi_core->safety_config = OSI_NULL if
* a particular MAC version does not need SW safety mechanisms
* like periodic read-verify.
* a particular MAC version does not need SW safety
* mechanisms like periodic read-verify.
*/
osi_core->safety_config = (void *)eqos_get_core_safety_config();
osi_core->safety_config =
(void *)eqos_get_core_safety_config();
} else {
#ifdef LINUX_IVC
/* Get IVC HW ops */
osi_core->ops = ivc_get_hw_core_ops();
/* Explicitly set osi_core->safety_config = OSI_NULL if
* a particular MAC version does not need SW safety
* mechanisms like periodic read-verify.
*/
osi_core->safety_config =
(void *)ivc_get_core_safety_config();
#endif
}
return 0;
}
@@ -94,8 +109,7 @@ nve32_t osi_poll_for_mac_reset_complete(
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->base != OSI_NULL) &&
(osi_core->ops->poll_for_swr != OSI_NULL)) {
return osi_core->ops->poll_for_swr(osi_core,
osi_core->pre_si);
return osi_core->ops->poll_for_swr(osi_core);
}
return -1;
@@ -131,7 +145,7 @@ nve32_t osi_start_mac(struct osi_core_priv_data *const osi_core)
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->base != OSI_NULL) &&
(osi_core->ops->start_mac != OSI_NULL)) {
osi_core->ops->start_mac(osi_core->base);
osi_core->ops->start_mac(osi_core);
return 0;
}
@@ -143,7 +157,7 @@ nve32_t osi_stop_mac(struct osi_core_priv_data *const osi_core)
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->base != OSI_NULL) &&
(osi_core->ops->stop_mac != OSI_NULL)) {
osi_core->ops->stop_mac(osi_core->base);
osi_core->ops->stop_mac(osi_core);
return 0;
}
@@ -180,7 +194,7 @@ nve32_t osi_set_speed(struct osi_core_priv_data *const osi_core,
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->base != OSI_NULL) &&
(osi_core->ops->set_speed != OSI_NULL)) {
osi_core->ops->set_speed(osi_core->base, speed);
osi_core->ops->set_speed(osi_core, speed);
return 0;
}
@@ -425,11 +439,11 @@ nve32_t osi_l3l4_filter(struct osi_core_priv_data *const osi_core,
if (osi_core->ops->config_l3_l4_filter_enable != OSI_NULL) {
if (osi_core->l3l4_filter_bitmask != OSI_DISABLE) {
ret = osi_core->ops->config_l3_l4_filter_enable(
osi_core->base,
osi_core,
OSI_ENABLE);
} else {
ret = osi_core->ops->config_l3_l4_filter_enable(
osi_core->base,
osi_core,
OSI_DISABLE);
}
@@ -631,10 +645,10 @@ nve32_t osi_ptp_configuration(struct osi_core_priv_data *const osi_core,
if (enable == OSI_DISABLE) {
/* disable hw time stamping */
/* Program MAC_Timestamp_Control Register */
osi_core->ops->config_tscr(osi_core->base, OSI_DISABLE);
osi_core->ops->config_tscr(osi_core, OSI_DISABLE);
} else {
/* Program MAC_Timestamp_Control Register */
osi_core->ops->config_tscr(osi_core->base,
osi_core->ops->config_tscr(osi_core,
osi_core->ptp_config.ptp_filter);
/* Program Sub Second Increment Register */
@@ -694,24 +708,132 @@ nve32_t osi_read_mmc(struct osi_core_priv_data *const osi_core)
return -1;
}
void osi_get_hw_features(void *base, struct osi_hw_features *hw_feat)
nveu32_t osi_read_reg(struct osi_core_priv_data *const osi_core,
const nve32_t addr)
{
if ((base != OSI_NULL) && (hw_feat != OSI_NULL)) {
common_get_hw_features(base, hw_feat);
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->read_reg != OSI_NULL) &&
(osi_core->base != OSI_NULL)) {
return osi_core->ops->read_reg(osi_core, addr);
}
return;
return 0;
}
nve32_t osi_get_mac_version(void *addr, nveu32_t *mac_ver)
nveu32_t osi_write_reg(struct osi_core_priv_data *const osi_core,
const nveu32_t val, const nve32_t addr)
{
nve32_t ret = -1;
if ((addr != OSI_NULL) && (mac_ver != OSI_NULL)) {
return common_get_mac_version(addr, mac_ver);
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->write_reg != OSI_NULL) &&
(osi_core->base != OSI_NULL)) {
return osi_core->ops->write_reg(osi_core, val, addr);
}
return ret;
return 0;
}
nve32_t osi_get_mac_version(struct osi_core_priv_data *const osi_core,
nveu32_t *mac_ver)
{
nveu32_t macver;
macver = osi_read_reg(osi_core, (nve32_t) MAC_VERSION) &
MAC_VERSION_SNVER_MASK;
if (is_valid_mac_version(macver) == 0) {
return -1;
}
*mac_ver = macver;
return 0;
}
void osi_get_hw_features(struct osi_core_priv_data *const osi_core,
struct osi_hw_features *hw_feat)
{
nveu32_t mac_hfr0;
nveu32_t mac_hfr1;
nveu32_t mac_hfr2;
if (hw_feat != OSI_NULL) {
/* TODO: need to add HFR3 */
mac_hfr0 = osi_read_reg(osi_core, EQOS_MAC_HFR0);
mac_hfr1 = osi_read_reg(osi_core, EQOS_MAC_HFR1);
mac_hfr2 = osi_read_reg(osi_core, EQOS_MAC_HFR2);
hw_feat->mii_sel =
((mac_hfr0 >> 0) & EQOS_MAC_HFR0_MIISEL_MASK);
hw_feat->gmii_sel =
((mac_hfr0 >> 1U) & EQOS_MAC_HFR0_GMIISEL_MASK);
hw_feat->hd_sel =
((mac_hfr0 >> 2U) & EQOS_MAC_HFR0_HDSEL_MASK);
hw_feat->pcs_sel =
((mac_hfr0 >> 3U) & EQOS_MAC_HFR0_PCSSEL_MASK);
hw_feat->sma_sel =
((mac_hfr0 >> 5U) & EQOS_MAC_HFR0_SMASEL_MASK);
hw_feat->rwk_sel =
((mac_hfr0 >> 6U) & EQOS_MAC_HFR0_RWKSEL_MASK);
hw_feat->mgk_sel =
((mac_hfr0 >> 7U) & EQOS_MAC_HFR0_MGKSEL_MASK);
hw_feat->mmc_sel =
((mac_hfr0 >> 8U) & EQOS_MAC_HFR0_MMCSEL_MASK);
hw_feat->arp_offld_en =
((mac_hfr0 >> 9U) & EQOS_MAC_HFR0_ARPOFFLDEN_MASK);
hw_feat->ts_sel =
((mac_hfr0 >> 12U) & EQOS_MAC_HFR0_TSSSEL_MASK);
hw_feat->eee_sel =
((mac_hfr0 >> 13U) & EQOS_MAC_HFR0_EEESEL_MASK);
hw_feat->tx_coe_sel =
((mac_hfr0 >> 14U) & EQOS_MAC_HFR0_TXCOESEL_MASK);
hw_feat->rx_coe_sel =
((mac_hfr0 >> 16U) & EQOS_MAC_HFR0_RXCOE_MASK);
hw_feat->mac_addr_sel =
((mac_hfr0 >> 18U) & EQOS_MAC_HFR0_ADDMACADRSEL_MASK);
hw_feat->mac_addr32_sel =
((mac_hfr0 >> 23U) & EQOS_MAC_HFR0_MACADR32SEL_MASK);
hw_feat->mac_addr64_sel =
((mac_hfr0 >> 24U) & EQOS_MAC_HFR0_MACADR64SEL_MASK);
hw_feat->tsstssel =
((mac_hfr0 >> 25U) & EQOS_MAC_HFR0_TSINTSEL_MASK);
hw_feat->sa_vlan_ins =
((mac_hfr0 >> 27U) & EQOS_MAC_HFR0_SAVLANINS_MASK);
hw_feat->act_phy_sel =
((mac_hfr0 >> 28U) & EQOS_MAC_HFR0_ACTPHYSEL_MASK);
hw_feat->rx_fifo_size =
((mac_hfr1 >> 0) & EQOS_MAC_HFR1_RXFIFOSIZE_MASK);
hw_feat->tx_fifo_size =
((mac_hfr1 >> 6U) & EQOS_MAC_HFR1_TXFIFOSIZE_MASK);
hw_feat->adv_ts_hword =
((mac_hfr1 >> 13U) & EQOS_MAC_HFR1_ADVTHWORD_MASK);
hw_feat->addr_64 =
((mac_hfr1 >> 14U) & EQOS_MAC_HFR1_ADDR64_MASK);
hw_feat->dcb_en =
((mac_hfr1 >> 16U) & EQOS_MAC_HFR1_DCBEN_MASK);
hw_feat->sph_en =
((mac_hfr1 >> 17U) & EQOS_MAC_HFR1_SPHEN_MASK);
hw_feat->tso_en =
((mac_hfr1 >> 18U) & EQOS_MAC_HFR1_TSOEN_MASK);
hw_feat->dma_debug_gen =
((mac_hfr1 >> 19U) & EQOS_MAC_HFR1_DMADEBUGEN_MASK);
hw_feat->av_sel =
((mac_hfr1 >> 20U) & EQOS_MAC_HFR1_AVSEL_MASK);
hw_feat->hash_tbl_sz =
((mac_hfr1 >> 24U) & EQOS_MAC_HFR1_HASHTBLSZ_MASK);
hw_feat->l3l4_filter_num =
((mac_hfr1 >> 27U) & EQOS_MAC_HFR1_L3L4FILTERNUM_MASK);
hw_feat->rx_q_cnt =
((mac_hfr2 >> 0) & EQOS_MAC_HFR2_RXQCNT_MASK);
hw_feat->tx_q_cnt =
((mac_hfr2 >> 6U) & EQOS_MAC_HFR2_TXQCNT_MASK);
hw_feat->rx_ch_cnt =
((mac_hfr2 >> 12U) & EQOS_MAC_HFR2_RXCHCNT_MASK);
hw_feat->tx_ch_cnt =
((mac_hfr2 >> 18U) & EQOS_MAC_HFR2_TXCHCNT_MASK);
hw_feat->pps_out_num =
((mac_hfr2 >> 24U) & EQOS_MAC_HFR2_PPSOUTNUM_MASK);
hw_feat->aux_snap_num =
((mac_hfr2 >> 28U) & EQOS_MAC_HFR2_AUXSNAPNUM_MASK);
}
}
#ifndef OSI_STRIPPED_LIB
@@ -817,7 +939,7 @@ nve32_t osi_update_vlan_id(struct osi_core_priv_data *const osi_core,
{
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->update_vlan_id != OSI_NULL)) {
return osi_core->ops->update_vlan_id(osi_core->base,
return osi_core->ops->update_vlan_id(osi_core,
vid);
}
@@ -828,8 +950,9 @@ nve32_t osi_get_systime_from_mac(struct osi_core_priv_data *const osi_core,
nveu32_t *sec,
nveu32_t *nsec)
{
if ((osi_core != OSI_NULL) && (osi_core->base != OSI_NULL)) {
common_get_systime_from_mac(osi_core->base, osi_core->mac, sec,
if ((osi_core != OSI_NULL) && (osi_core->dma_base != OSI_NULL)) {
common_get_systime_from_mac(osi_core->dma_base,
osi_core->mac, sec,
nsec);
} else {
return -1;
@@ -912,8 +1035,7 @@ nve32_t osi_config_arp_offload(struct osi_core_priv_data *const osi_core,
if (osi_core != OSI_NULL && osi_core->ops != OSI_NULL &&
(osi_core->base != OSI_NULL) && (ip_addr != OSI_NULL) &&
(osi_core->ops->config_arp_offload != OSI_NULL)) {
return osi_core->ops->config_arp_offload(osi_core->mac_ver,
osi_core,
return osi_core->ops->config_arp_offload(osi_core,
flags, ip_addr);
}
@@ -938,7 +1060,7 @@ nve32_t osi_config_mac_loopback(struct osi_core_priv_data *const osi_core,
/* Configure MAC loopback */
if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
(osi_core->ops->config_mac_loopback != OSI_NULL)) {
return osi_core->ops->config_mac_loopback(osi_core->base,
return osi_core->ops->config_mac_loopback(osi_core,
lb_mode);
}

64
osi/dma/eqos_dma.c
View File

@@ -42,6 +42,7 @@ static struct dma_func_safety eqos_dma_safety_config;
* this latest value will be compared when eqos_validate_dma_regs is
* scheduled.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] val: Value to be written.
* @param[in] addr: memory mapped register address to be written to.
* @param[in] idx: Index of register corresponding to enum func_safety_dma_regs.
@@ -54,13 +55,14 @@ static struct dma_func_safety eqos_dma_safety_config;
* - Run time: Yes
* - De-initialization: Yes
*/
static inline void eqos_dma_safety_writel(nveu32_t val, void *addr,
static inline void eqos_dma_safety_writel(struct osi_dma_priv_data *osi_dma,
nveu32_t val, void *addr,
nveu32_t idx)
{
struct dma_func_safety *config = &eqos_dma_safety_config;
osi_lock_irq_enabled(&config->dma_safety_lock);
osi_writel(val, addr);
osi_writela(osi_dma->osd, val, addr);
config->reg_val[idx] = (val & config->reg_mask[idx]);
osi_unlock_irq_enabled(&config->dma_safety_lock);
}
@@ -300,8 +302,7 @@ static void eqos_enable_chan_rx_intr(void *addr, nveu32_t chan)
* Algorithm:
* - Set DMA Tx channel ring length for specific channel.
*
* @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: DMA Tx channel number.
* @param[in] len: Length.
*
@@ -311,11 +312,13 @@ static void eqos_enable_chan_rx_intr(void *addr, nveu32_t chan)
* - Run time: No
* - De-initialization: No
*/
static void eqos_set_tx_ring_len(void *addr, nveu32_t chan,
static void eqos_set_tx_ring_len(struct osi_dma_priv_data *osi_dma,
nveu32_t chan,
nveu32_t len)
{
void *addr = osi_dma->base;
CHECK_CHAN_BOUND(chan);
eqos_dma_safety_writel(len, (nveu8_t *)addr +
eqos_dma_safety_writel(osi_dma, len, (nveu8_t *)addr +
EQOS_DMA_CHX_TDRL(chan),
EQOS_DMA_CH0_TDRL_IDX + chan);
}
@@ -402,8 +405,7 @@ static void eqos_update_tx_tailptr(void *addr, nveu32_t chan,
* Algorithm:
* - Sets DMA Rx channel ring length for specific DMA channel.
*
* @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: DMA Rx channel number.
* @param[in] len: Length
*
@@ -413,11 +415,13 @@ static void eqos_update_tx_tailptr(void *addr, nveu32_t chan,
* - Run time: No
* - De-initialization: No
*/
static void eqos_set_rx_ring_len(void *addr, nveu32_t chan,
static void eqos_set_rx_ring_len(struct osi_dma_priv_data *osi_dma,
nveu32_t chan,
nveu32_t len)
{
void *addr = osi_dma->base;
CHECK_CHAN_BOUND(chan);
eqos_dma_safety_writel(len, (nveu8_t *)addr +
eqos_dma_safety_writel(osi_dma, len, (nveu8_t *)addr +
EQOS_DMA_CHX_RDRL(chan),
EQOS_DMA_CH0_RDRL_IDX + chan);
}
@@ -503,8 +507,7 @@ static void eqos_update_rx_tailptr(void *addr, nveu32_t chan,
* Algorithm:
* - Start Tx and Rx DMA for specific channel.
*
* @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: DMA Tx/Rx channel number.
*
* @pre
@@ -517,23 +520,26 @@ static void eqos_update_rx_tailptr(void *addr, nveu32_t chan,
* - Run time: No
* - De-initialization: No
*/
static void eqos_start_dma(void *addr, nveu32_t chan)
static void eqos_start_dma(struct osi_dma_priv_data *osi_dma, nveu32_t chan)
{
nveu32_t val;
void *addr = osi_dma->base;
CHECK_CHAN_BOUND(chan);
/* start Tx DMA */
val = osi_readl((nveu8_t *)addr + EQOS_DMA_CHX_TX_CTRL(chan));
val = osi_readla(osi_dma->osd,
(nveu8_t *)addr + EQOS_DMA_CHX_TX_CTRL(chan));
val |= OSI_BIT(0);
eqos_dma_safety_writel(val, (nveu8_t *)addr +
eqos_dma_safety_writel(osi_dma, val, (nveu8_t *)addr +
EQOS_DMA_CHX_TX_CTRL(chan),
EQOS_DMA_CH0_TX_CTRL_IDX + chan);
/* start Rx DMA */
val = osi_readl((nveu8_t *)addr + EQOS_DMA_CHX_RX_CTRL(chan));
val = osi_readla(osi_dma->osd,
(nveu8_t *)addr + EQOS_DMA_CHX_RX_CTRL(chan));
val |= OSI_BIT(0);
eqos_dma_safety_writel(val, (nveu8_t *)addr +
eqos_dma_safety_writel(osi_dma, val, (nveu8_t *)addr +
EQOS_DMA_CHX_RX_CTRL(chan),
EQOS_DMA_CH0_RX_CTRL_IDX + chan);
}
@@ -545,8 +551,7 @@ static void eqos_start_dma(void *addr, nveu32_t chan)
* Algorithm:
* - Start Tx and Rx DMA for specific channel.
*
* @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: DMA Tx/Rx channel number.
*
* @pre
@@ -559,23 +564,26 @@ static void eqos_start_dma(void *addr, nveu32_t chan)
* - Run time: No
* - De-initialization: Yes
*/
static void eqos_stop_dma(void *addr, nveu32_t chan)
static void eqos_stop_dma(struct osi_dma_priv_data *osi_dma, nveu32_t chan)
{
nveu32_t val;
void *addr = osi_dma->base;
CHECK_CHAN_BOUND(chan);
/* stop Tx DMA */
val = osi_readl((nveu8_t *)addr + EQOS_DMA_CHX_TX_CTRL(chan));
val = osi_readla(osi_dma->osd,
(nveu8_t *)addr + EQOS_DMA_CHX_TX_CTRL(chan));
val &= ~OSI_BIT(0);
eqos_dma_safety_writel(val, (nveu8_t *)addr +
eqos_dma_safety_writel(osi_dma, val, (nveu8_t *)addr +
EQOS_DMA_CHX_TX_CTRL(chan),
EQOS_DMA_CH0_TX_CTRL_IDX + chan);
/* stop Rx DMA */
val = osi_readl((nveu8_t *)addr + EQOS_DMA_CHX_RX_CTRL(chan));
val = osi_readla(osi_dma->osd,
(nveu8_t *)addr + EQOS_DMA_CHX_RX_CTRL(chan));
val &= ~OSI_BIT(0);
eqos_dma_safety_writel(val, (nveu8_t *)addr +
eqos_dma_safety_writel(osi_dma, val, (nveu8_t *)addr +
EQOS_DMA_CHX_RX_CTRL(chan),
EQOS_DMA_CH0_RX_CTRL_IDX + chan);
}
@@ -632,7 +640,7 @@ static void eqos_configure_dma_channel(nveu32_t chan,
EQOS_DMA_CHX_INTR_NIE;
/* For multi-irqs to work nie needs to be disabled */
value &= ~(EQOS_DMA_CHX_INTR_NIE);
eqos_dma_safety_writel(value, (nveu8_t *)osi_dma->base +
eqos_dma_safety_writel(osi_dma, value, (nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_INTR_ENA(chan),
EQOS_DMA_CH0_INTR_ENA_IDX + chan);
@@ -640,7 +648,7 @@ static void eqos_configure_dma_channel(nveu32_t chan,
value = osi_readl((nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_CTRL(chan));
value |= EQOS_DMA_CHX_CTRL_PBLX8;
eqos_dma_safety_writel(value, (nveu8_t *)osi_dma->base +
eqos_dma_safety_writel(osi_dma, value, (nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_CTRL(chan),
EQOS_DMA_CH0_CTRL_IDX + chan);
@@ -654,7 +662,7 @@ static void eqos_configure_dma_channel(nveu32_t chan,
/* enable TSO by default if HW supports */
value |= EQOS_DMA_CHX_TX_CTRL_TSE;
eqos_dma_safety_writel(value, (nveu8_t *)osi_dma->base +
eqos_dma_safety_writel(osi_dma, value, (nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_TX_CTRL(chan),
EQOS_DMA_CH0_TX_CTRL_IDX + chan);
@@ -671,7 +679,7 @@ static void eqos_configure_dma_channel(nveu32_t chan,
value |= (osi_dma->rx_buf_len << EQOS_DMA_CHX_RBSZ_SHIFT);
/* RXPBL = 12 */
value |= EQOS_DMA_CHX_RX_CTRL_RXPBL_RECOMMENDED;
eqos_dma_safety_writel(value, (nveu8_t *)osi_dma->base +
eqos_dma_safety_writel(osi_dma, value, (nveu8_t *)osi_dma->base +
EQOS_DMA_CHX_RX_CTRL(chan),
EQOS_DMA_CH0_RX_CTRL_IDX + chan);

4
osi/dma/osi_dma.c
View File

@@ -231,7 +231,7 @@ nve32_t osi_start_dma(struct osi_dma_priv_data *osi_dma,
if ((osi_dma != OSI_NULL) && (osi_dma->ops != OSI_NULL) &&
(osi_dma->base != OSI_NULL) && (chan < OSI_EQOS_MAX_NUM_CHANS) &&
(osi_dma->ops->start_dma != OSI_NULL)) {
osi_dma->ops->start_dma(osi_dma->base, chan);
osi_dma->ops->start_dma(osi_dma, chan);
return 0;
}
@@ -244,7 +244,7 @@ nve32_t osi_stop_dma(struct osi_dma_priv_data *osi_dma,
if ((osi_dma != OSI_NULL) && (osi_dma->ops != OSI_NULL) &&
(osi_dma->base != OSI_NULL) && (chan < OSI_EQOS_MAX_NUM_CHANS) &&
(osi_dma->ops->stop_dma != OSI_NULL)) {
osi_dma->ops->stop_dma(osi_dma->base, chan);
osi_dma->ops->stop_dma(osi_dma, chan);
return 0;
}

6
osi/dma/osi_dma_txrx.c
View File

@@ -1308,7 +1308,7 @@ static nve32_t rx_dma_desc_initialization(struct osi_dma_priv_data *osi_dma,
return -1;
}
ops->set_rx_ring_len(osi_dma->base, chan, (RX_DESC_CNT - 1U));
ops->set_rx_ring_len(osi_dma, chan, (RX_DESC_CNT - 1U));
ops->update_rx_tailptr(osi_dma->base, chan, tailptr);
ops->set_rx_ring_start_addr(osi_dma->base, chan,
rx_ring->rx_desc_phy_addr);
@@ -1415,8 +1415,8 @@ static nve32_t tx_dma_desc_init(struct osi_dma_priv_data *osi_dma)
tx_ring->slot_check = OSI_DISABLE;
if (osi_likely((ops->set_tx_ring_len != OSI_NULL) ||
(ops->set_tx_ring_start_addr != OSI_NULL))) {
ops->set_tx_ring_len(osi_dma->base, chan,
ops->set_tx_ring_start_addr != OSI_NULL)) {
ops->set_tx_ring_len(osi_dma, chan,
(TX_DESC_CNT - 1U));
ops->set_tx_ring_start_addr(osi_dma->base, chan,
tx_ring->tx_desc_phy_addr);