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osi: core: add m2m sync error detection and reporting

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Issue: New safety requirement to detect
and report M2M eqos sync error.

Fix: add support for error detection and
reporting.

Bug 4033627

Change-Id: I377b8f11a6518841e21fe9e1ab3682447b31138b
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2879433
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Rakesh Goyal
2023-03-23 13:26:43 +05:30
committed by Bhadram Varka
parent 1a0aa7bed3
commit 2e2e449599
3 changed files with 107 additions and 7 deletions
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9
include/osi_core.h
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@@ -376,6 +376,7 @@ typedef my_lint_64 nvel64_t;
#define AUTONEG_ERR_IDX 5U
#define XPCS_WRITE_FAIL_IDX 6U
#define PHY_WRITE_VERIFY_FAIL_IDX 7U
#define MAC2MAC_ERR_IDX 8U
#define MACSEC_RX_CRC_ERR_IDX 0U
#define MACSEC_TX_CRC_ERR_IDX 1U
#define MACSEC_RX_ICV_ERR_IDX 2U
@@ -402,7 +403,7 @@ typedef my_lint_64 nvel64_t;
* @brief Maximum number of different mac error code
* HSI_SW_ERR_CODE + Two (Corrected and Uncorrected error code)
*/
#define OSI_HSI_MAX_MAC_ERROR_CODE 8U
#define OSI_HSI_MAX_MAC_ERROR_CODE 9U
/**
* @brief Maximum number of different macsec error code
@@ -425,6 +426,12 @@ typedef my_lint_64 nvel64_t;
#define OSI_MACSEC_REG_VIOL_ERR 0x1008U
#define OSI_XPCS_WRITE_FAIL_ERR 0x1009U
#define OSI_PHY_WRITE_VERIFY_ERR 0x100AU
#define OSI_M2M_TSC_READ_ERR 0x100BU
#define OSI_M2M_TIME_CAL_ERR 0x100CU
#define OSI_M2M_ADJ_FREQ_ERR 0x100DU
#define OSI_M2M_ADJ_TIME_ERR 0x100EU
#define OSI_M2M_SET_TIME_ERR 0x100FU
#define OSI_M2M_CONFIG_PTP_ERR 0x1010U
#define OSI_HSI_MGBE0_UE_CODE 0x2A00U
#define OSI_HSI_MGBE1_UE_CODE 0x2A01U