diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index 56e60cd..d682f0e 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -2011,10 +2011,10 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
 	nveu32_t value = 0U;
 	nve32_t ret = 0;
 	const nveu32_t xpcs_intr_ctrl_reg[OSI_MAX_MAC_IP_TYPES] = {
-				0,
-				XPCS_WRAP_INTERRUPT_CONTROL,
-				T26X_XPCS_WRAP_INTERRUPT_CONTROL
-			};
+		0,
+		XPCS_WRAP_INTERRUPT_CONTROL,
+		T26X_XPCS_WRAP_INTERRUPT_CONTROL
+	};
 	const nveu32_t intr_en[OSI_MAX_MAC_IP_TYPES] = {
 		0,
 		MGBE_WRAP_COMMON_INTR_ENABLE,
diff --git a/osi/core/xpcs.h b/osi/core/xpcs.h
index 644c1b7..e292721 100644
--- a/osi/core/xpcs.h
+++ b/osi/core/xpcs.h
@@ -213,7 +213,7 @@
 
 #ifdef HSI_SUPPORT
 #define XPCS_WRAP_INTERRUPT_CONTROL			0x8048
-#define T26X_XPCS_WRAP_INTERRUPT_CONTROL		0x8078
+#define T26X_XPCS_WRAP_INTERRUPT_CONTROL		0x8084
 #define XPCS_CORE_CORRECTABLE_ERR			OSI_BIT(10)
 #define XPCS_CORE_UNCORRECTABLE_ERR			OSI_BIT(9)
 #define XPCS_REGISTER_PARITY_ERR			OSI_BIT(8)
@@ -224,7 +224,6 @@
 #define XPCS_SFTY_1US_MULT_SHIFT			0U
 #define XPCS_FSM_TO_SEL_SHIFT				10U
 #define XPCS_FSM_TO_SEL_MASK				0xC00U
-#define XPCS_FEC_EN					OSI_BIT(0)
 #endif
 /** @} */