From 3102008039e16a09e62230a2b01147f6bf5c8ab0 Mon Sep 17 00:00:00 2001 From: Narayan Reddy Date: Wed, 14 Sep 2022 00:48:29 +0530 Subject: [PATCH] osi: core: Fix MISRA issues ===== DIFF ====== Total misra violation count changed by -71 Rule: MISRA_C-2012_Directive_4.5 Diff: -3 Rule: MISRA_C-2012_Rule_11.1 Diff: -5 Rule: MISRA_C-2012_Rule_11.3 Diff: -1 Rule: MISRA_C-2012_Rule_11.5 Diff: 1 Rule: MISRA_C-2012_Rule_12.1 Diff: -6 Rule: MISRA_C-2012_Rule_12.2 Diff: -7 Rule: MISRA_C-2012_Rule_15.1 Diff: -1 Rule: MISRA_C-2012_Rule_15.6 Diff: -1 Rule: MISRA_C-2012_Rule_16.1 Diff: -1 Rule: MISRA_C-2012_Rule_16.3 Diff: -1 Rule: MISRA_C-2012_Rule_17.7 Diff: -4 Rule: MISRA_C-2012_Rule_17.8 Diff: -5 Rule: MISRA_C-2012_Rule_2.4 Diff: -4 Rule: MISRA_C-2012_Rule_2.5 Diff: -18 Rule: MISRA_C-2012_Rule_20.5 Diff: -1 Rule: MISRA_C-2012_Rule_5.6 Diff: -1 Rule: MISRA_C-2012_Rule_5.8 Diff: -1 Rule: MISRA_C-2012_Rule_5.9 Diff: -4 Rule: MISRA_C-2012_Rule_8.3 Diff: -2 Rule: MISRA_C-2012_Rule_8.9 Diff: -5 Rule: MISRA_C-2012_Rule_9.5 Diff: -1 Rule: Total Diff: -71 Bug 3695218 Change-Id: I9bd904f8a77195ca34fb2d47639a214f0083ccf7 Signed-off-by: Narayan Reddy Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2776281 Reviewed-by: Nagarjuna Kristam Reviewed-by: Bhadram Varka Reviewed-by: Srinivas Ramachandran GVS: Gerrit_Virtual_Submit --- include/ivc_core.h | 8 +- include/nvethernetrm_export.h | 17 ++ include/osi_core.h | 14 +- osi/core/core_common.c | 52 +++--- osi/core/core_common.h | 14 +- osi/core/core_local.h | 21 ++- osi/core/eqos_core.c | 131 +++++--------- osi/core/eqos_core.h | 41 ++--- osi/core/ivc_core.c | 111 ++++++------ osi/core/macsec.c | 19 +-- osi/core/mgbe_core.c | 70 ++++---- osi/core/mgbe_core.h | 5 +- osi/core/mgbe_mmc.c | 312 +++++++++++++++++----------------- osi/core/osi_core.c | 15 +- osi/core/osi_hal.c | 11 +- osi/core/xpcs.c | 3 +- 16 files changed, 415 insertions(+), 429 deletions(-) diff --git a/include/ivc_core.h b/include/ivc_core.h index 9488686..e67ab11 100644 --- a/include/ivc_core.h +++ b/include/ivc_core.h @@ -46,7 +46,7 @@ struct osi_stats { /** * @brief IVC commands between OSD & OSI. */ -typedef enum ivc_cmd { +typedef enum { core_init = 1, core_deinit, write_phy_reg, @@ -73,7 +73,7 @@ typedef enum ivc_cmd { /** * @brief IVC arguments structure. */ -typedef struct ivc_args { +typedef struct { /** Number of arguments */ nveu32_t count; /** arguments */ @@ -83,7 +83,7 @@ typedef struct ivc_args { /** * @brief IVC core argument structure. */ -typedef struct ivc_core_args { +typedef struct { /** Number of MTL queues enabled in MAC */ nveu32_t num_mtl_queues; /** Array of MTL queues */ @@ -110,7 +110,7 @@ typedef struct ivc_core_args { * @brief macsec config structure. */ #ifdef MACSEC_SUPPORT -typedef struct macsec_config { +typedef struct { /** MACsec secure channel basic information */ struct osi_macsec_sc_info sc_info; /** MACsec enable or disable */ diff --git a/include/nvethernetrm_export.h b/include/nvethernetrm_export.h index d74538a..1dbbfb6 100644 --- a/include/nvethernetrm_export.h +++ b/include/nvethernetrm_export.h @@ -68,6 +68,23 @@ #define OSI_MTL_TXQ_AVALG_SP 0U /** @} */ +#ifndef OSI_STRIPPED_LIB +/** + * @addtogroup Helper MACROS + * + * @brief EQOS generic helper MACROS. + * @{ + */ +/* L2 DA filter mode(enable/disable) */ +#define OSI_OPER_EN_L2_DA_INV OSI_BIT(4) +#define OSI_OPER_DIS_L2_DA_INV OSI_BIT(5) +#endif /* !OSI_STRIPPED_LIB */ + +/* Ethernet Address length */ +#define OSI_ETH_ALEN 6U +#define OSI_MAX_TC_NUM 8U +/** @} */ + #pragma pack(push, 1) /** * @brief FRP command structure for OSD to OSI diff --git a/include/osi_core.h b/include/osi_core.h index a49b72c..a3d9f34 100644 --- a/include/osi_core.h +++ b/include/osi_core.h @@ -45,6 +45,8 @@ typedef my_lint_64 nvel64_t; /** @} */ #ifndef OSI_STRIPPED_LIB +#define OSI_OPER_EN_L2_DA_INV OSI_BIT(4) +#define OSI_OPER_DIS_L2_DA_INV OSI_BIT(5) #define OSI_PTP_SNAP_TRANSPORT 1U #define OSI_VLAN_ACTION_DEL 0x0U #define OSI_VLAN_ACTION_ADD OSI_BIT(31) @@ -125,13 +127,6 @@ typedef my_lint_64 nvel64_t; #define OSI_PTP_M2M_SECONDARY 2U /** @} */ -/** - * @addtogroup PTP PTP related information - * - *@brief 1 Second in NenoSec - */ -#define OSI_1SEC_TO_NSEC 1000000000LL -/** @} */ /** * @addtogroup EQOS_PTP PTP Helper MACROS @@ -190,8 +185,6 @@ typedef my_lint_64 nvel64_t; #define OSI_OPER_DIS_PROMISC OSI_BIT(1) #define OSI_OPER_EN_ALLMULTI OSI_BIT(2) #define OSI_OPER_DIS_ALLMULTI OSI_BIT(3) -#define OSI_OPER_EN_L2_DA_INV OSI_BIT(4) -#define OSI_OPER_DIS_L2_DA_INV OSI_BIT(5) #define OSI_OPER_EN_PERFECT OSI_BIT(6) #define OSI_OPER_DIS_PERFECT OSI_BIT(7) #define OSI_OPER_ADDR_UPDATE OSI_BIT(8) @@ -220,7 +213,7 @@ typedef my_lint_64 nvel64_t; * @brief Ethernet PHY Interface Modes */ #define OSI_XFI_MODE_10G 0U -#define OSI_XFI_MODE_5G 1U +#define OSI_XFI_MODE_5G 1U #define OSI_USXGMII_MODE_10G 2U #define OSI_USXGMII_MODE_5G 3U @@ -238,7 +231,6 @@ typedef my_lint_64 nvel64_t; #define OSI_CMD_PAD_CALIBRATION 8U #define OSI_CMD_READ_MMC 9U #define OSI_CMD_GET_MAC_VER 10U -#define OSI_CMD_RESET_MMC 12U #define OSI_CMD_SET_MODE 16U #define OSI_CMD_SET_SPEED 17U #define OSI_CMD_L2_FILTER 18U diff --git a/osi/core/core_common.c b/osi/core/core_common.c index 51baef0..00fd99f 100644 --- a/osi/core/core_common.c +++ b/osi/core/core_common.c @@ -109,7 +109,7 @@ nve32_t hw_set_mode(struct osi_core_priv_data *const osi_core, const nve32_t mod void *base = osi_core->base; nveu32_t mcr_val; nve32_t ret = 0; - const nveu32_t set_bit[2] = { EQOS_MCR_DO, EQOS_MCR_DM }; + const nveu32_t bit_set[2] = { EQOS_MCR_DO, EQOS_MCR_DM }; const nveu32_t clear_bit[2] = { EQOS_MCR_DM, EQOS_MCR_DO }; /* don't allow only if loopback mode is other than 0 or 1 */ @@ -122,7 +122,7 @@ nve32_t hw_set_mode(struct osi_core_priv_data *const osi_core, const nve32_t mod if (osi_core->mac == OSI_MAC_HW_EQOS) { mcr_val = osi_readla(osi_core, (nveu8_t *)base + EQOS_MAC_MCR); - mcr_val |= set_bit[mode]; + mcr_val |= bit_set[mode]; mcr_val &= ~clear_bit[mode]; osi_writela(osi_core, mcr_val, ((nveu8_t *)base + EQOS_MAC_MCR)); } @@ -137,9 +137,9 @@ nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t sp void *base = osi_core->base; const nveu32_t mac_mcr[2] = { EQOS_MAC_MCR, MGBE_MAC_TMCR }; - if ((osi_core->mac == OSI_MAC_HW_EQOS && speed > OSI_SPEED_1000) || - (osi_core->mac == OSI_MAC_HW_MGBE && (speed < OSI_SPEED_2500 || - speed > OSI_SPEED_10000))) { + if (((osi_core->mac == OSI_MAC_HW_EQOS) && (speed > OSI_SPEED_1000)) || + ((osi_core->mac == OSI_MAC_HW_MGBE) && ((speed < OSI_SPEED_2500) || + (speed > OSI_SPEED_10000)))) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "unsupported speed\n", (nveul64_t)speed); ret = -1; @@ -148,11 +148,6 @@ nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t sp value = osi_readla(osi_core, ((nveu8_t *)base + mac_mcr[osi_core->mac])); switch (speed) { - default: - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, - "unsupported speed\n", (nveul64_t)speed); - ret = -1; - goto fail; case OSI_SPEED_10: value |= EQOS_MCR_PS; value &= ~EQOS_MCR_FES; @@ -174,7 +169,16 @@ nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t sp case OSI_SPEED_10000: value &= ~MGBE_MAC_TMCR_SS_10G; break; - + default: + if (osi_core->mac == OSI_MAC_HW_EQOS) { + value &= ~EQOS_MCR_PS; + value &= ~EQOS_MCR_FES; + } else if (osi_core->mac == OSI_MAC_HW_MGBE) { + value &= ~MGBE_MAC_TMCR_SS_10G; + } else { + /* Do Nothing */ + } + break; } osi_writela(osi_core, value, ((nveu8_t *)osi_core->base + mac_mcr[osi_core->mac])); @@ -199,10 +203,10 @@ nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core, { void *addr = osi_core->base; nveu32_t tx_op_mode_val = 0U; - nveu32_t qinx = (q_inx & 0xFU); + nveu32_t que_idx = (q_inx & 0xFU); nveu32_t value; - const nveu32_t tx_op_mode[2] = { EQOS_MTL_CHX_TX_OP_MODE(qinx), - MGBE_MTL_CHX_TX_OP_MODE(qinx)}; + const nveu32_t tx_op_mode[2] = { EQOS_MTL_CHX_TX_OP_MODE(que_idx), + MGBE_MTL_CHX_TX_OP_MODE(que_idx)}; /* Read Tx Q Operating Mode Register and flush TxQ */ value = osi_readla(osi_core, ((nveu8_t *)addr + tx_op_mode[osi_core->mac])); @@ -219,16 +223,16 @@ nve32_t hw_config_fw_err_pkts(struct osi_core_priv_data *osi_core, { nveu32_t val; nve32_t ret = 0; - nveu32_t qinx = (q_inx & 0xFU); - const nveu32_t rx_op_mode[2] = { EQOS_MTL_CHX_RX_OP_MODE(qinx), - MGBE_MTL_CHX_RX_OP_MODE(qinx)}; + nveu32_t que_idx = (q_inx & 0xFU); + const nveu32_t rx_op_mode[2] = { EQOS_MTL_CHX_RX_OP_MODE(que_idx), + MGBE_MTL_CHX_RX_OP_MODE(que_idx)}; const nveu32_t max_q[2] = { OSI_EQOS_MAX_NUM_QUEUES, OSI_MGBE_MAX_NUM_QUEUES}; - /* Check for valid enable_fw_err_pkts and qinx values */ - if ((enable_fw_err_pkts != OSI_ENABLE && - enable_fw_err_pkts != OSI_DISABLE) || - (qinx >= max_q[osi_core->mac])) { + /* Check for valid enable_fw_err_pkts and que_idx values */ + if (((enable_fw_err_pkts != OSI_ENABLE) && + (enable_fw_err_pkts != OSI_DISABLE)) || + (que_idx >= max_q[osi_core->mac])) { ret = -1; goto fail; } @@ -269,7 +273,7 @@ nve32_t hw_config_rxcsum_offload(struct osi_core_priv_data *const osi_core, const nveu32_t rxcsum_mode[2] = { EQOS_MAC_MCR, MGBE_MAC_RMCR}; const nveu32_t ipc_value[2] = { EQOS_MCR_IPC, MGBE_MAC_RMCR_IPC}; - if (enabled != OSI_ENABLE && enabled != OSI_DISABLE) { + if ((enabled != OSI_ENABLE) && (enabled != OSI_DISABLE)) { ret = -1; goto fail; } @@ -435,7 +439,7 @@ void hw_config_ssir(struct osi_core_priv_data *const osi_core) { nveul64_t val = 0U; void *addr = osi_core->base; - const struct core_local *l_core = (struct core_local *)osi_core; + const struct core_local *l_core = (struct core_local *)(void *)osi_core; const nveu32_t mac_ssir[2] = { EQOS_MAC_SSIR, MGBE_MAC_SSIR}; const nveu32_t ptp_ssinc[3] = {OSI_PTP_SSINC_4, OSI_PTP_SSINC_6, OSI_PTP_SSINC_4}; @@ -568,7 +572,7 @@ nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core, nve32_t ret = 0; /* validate filter_enb_dis argument */ - if (filter_enb_dis != OSI_ENABLE && filter_enb_dis != OSI_DISABLE) { + if ((filter_enb_dis != OSI_ENABLE) && (filter_enb_dis != OSI_DISABLE)) { OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID, "Invalid filter_enb_dis value\n", filter_enb_dis); diff --git a/osi/core/core_common.h b/osi/core/core_common.h index cd281d9..9cfac2a 100644 --- a/osi/core/core_common.h +++ b/osi/core/core_common.h @@ -24,7 +24,14 @@ #define INCLUDED_CORE_COMMON_H #include "core_local.h" + +#ifndef OSI_STRIPPED_LIB +#define MAC_PFR_PR OSI_BIT(0) +#define MAC_TCR_TSCFUPDT OSI_BIT(1) #define MAC_TCR_TSCTRLSSR OSI_BIT(9) +#define MAC_PFR_PM OSI_BIT(4) +#endif /* !OSI_STRIPPED_LIB */ + #define MTL_EST_ADDR_SHIFT 8 #define MTL_EST_ADDR_MASK (OSI_BIT(8) | OSI_BIT(9) | \ OSI_BIT(10) | OSI_BIT(11) | \ @@ -40,7 +47,6 @@ #define MTL_EST_ERR0 OSI_BIT(20) #define MTL_EST_CONTROL_EEST OSI_BIT(0) #define MTL_EST_STATUS_SWOL OSI_BIT(7) -#define MAC_TCR_TSCFUPDT OSI_BIT(1) /* EST control OSI_BIT map */ #define MTL_EST_EEST OSI_BIT(0) #define MTL_EST_SSWL OSI_BIT(1) @@ -71,9 +77,7 @@ #define MAC_PPS_CTL_PPSCTRL0 (OSI_BIT(3) | OSI_BIT(2) |\ OSI_BIT(1) | OSI_BIT(0)) #define MAC_SSIR_SSINC_SHIFT 16U -#define MAC_PFR_PR OSI_BIT(0) #define MAC_PFR_DAIF OSI_BIT(3) -#define MAC_PFR_PM OSI_BIT(4) #define MAC_PFR_DBF OSI_BIT(5) #define MAC_PFR_PCF (OSI_BIT(6) | OSI_BIT(7)) #define MAC_PFR_SAIF OSI_BIT(8) @@ -115,9 +119,9 @@ void hw_stop_mac(struct osi_core_priv_data *const osi_core); nve32_t hw_set_mode(struct osi_core_priv_data *const osi_core, const nve32_t mode); nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t speed); nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core, - const nveu32_t qinx); + const nveu32_t q_inx); nve32_t hw_config_fw_err_pkts(struct osi_core_priv_data *osi_core, - const nveu32_t qinx, const nveu32_t enable_fw_err_pkts); + const nveu32_t q_inx, const nveu32_t enable_fw_err_pkts); nve32_t hw_config_rxcsum_offload(struct osi_core_priv_data *const osi_core, nveu32_t enabled); nve32_t hw_set_systime_to_mac(struct osi_core_priv_data *const osi_core, diff --git a/osi/core/core_local.h b/osi/core/core_local.h index 164678e..583213c 100644 --- a/osi/core/core_local.h +++ b/osi/core/core_local.h @@ -106,8 +106,8 @@ struct if_core_ops { struct core_ops { /** Called to initialize MAC and MTL registers */ nve32_t (*core_init)(struct osi_core_priv_data *const osi_core, - const nveu32_t tx_fifo_size, - const nveu32_t rx_fifo_size); + nveu32_t tx_fifo_size, + nveu32_t rx_fifo_size); /** Called to handle common interrupt */ void (*handle_common_intr)(struct osi_core_priv_data *const osi_core); /** Called to do pad caliberation */ @@ -268,25 +268,29 @@ struct core_ops { * @brief constant values for drift MAC to MAC sync. */ /* No longer needed since DRIFT CAL is not used */ -#undef ENABLE_DRIFT_CAL #ifdef ENABLE_DRIFT_CAL #define DRIFT_CAL 1 #define I_COMPONENT_BY_10 3 #define P_COMPONENT_BY_10 7 #define WEIGHT_BY_10 10 #define MAX_FREQ 85000000LL +#define SERVO_STATS_0 0U +#define SERVO_STATS_1 1U +#define SERVO_STATS_2 2U #else #define DRIFT_CAL 0 #endif + +#if (!defined(ETHERNET_SERVER) && !defined(__QNX__)) || DRIFT_CAL #define EQOS_SEC_OFFSET 0xB08 #define EQOS_NSEC_OFFSET 0xB0C #define MGBE_SEC_OFFSET 0xD08 #define MGBE_NSEC_OFFSET 0xD0C #define ETHER_NSEC_MASK 0x7FFFFFFFU -#define SERVO_STATS_0 0U -#define SERVO_STATS_1 1U -#define SERVO_STATS_2 2U +#define OSI_1SEC_TO_NSEC 1000000000LL +#endif +#if DRIFT_CAL /** * @brief servo data structure. */ @@ -311,6 +315,7 @@ struct core_ptp_servo { /* MAC to MAC locking to access HW time register within OSI calls */ nveu32_t m2m_lock; }; +#endif /** * @brief L3/L4 dynamic config storage structure. @@ -409,7 +414,7 @@ struct core_local { /** This is the head node for PTP packet ID queue */ struct osi_core_tx_ts tx_ts_head; /** Maximum number of queues/channels */ - nveu32_t max_chans; + nveu32_t num_max_chans; /** GCL depth supported by HW */ nveu32_t gcl_dep; /** Max GCL width (time + gate) value supported by HW */ @@ -418,8 +423,10 @@ struct core_local { nveu32_t ts_lock; /** Controller mac to mac role */ nveu32_t ether_m2m_role; +#if DRIFT_CAL /** Servo structure */ struct core_ptp_servo serv; +#endif /** HW comeout from reset successful OSI_ENABLE else OSI_DISABLE */ nveu32_t hw_init_successful; /** Dynamic MAC to MAC time sync control for secondary interface */ diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c index 907f799..596d60e 100644 --- a/osi/core/eqos_core.c +++ b/osi/core/eqos_core.c @@ -39,6 +39,7 @@ static nve32_t eqos_pre_pad_calibrate( struct osi_core_priv_data *const osi_core); #endif /* UPDATED_PAD_CAL */ +#ifndef OSI_STRIPPED_LIB /** * @brief eqos_core_safety_config - EQOS MAC core safety configuration */ @@ -82,7 +83,6 @@ static inline void eqos_core_safety_writel( osi_unlock_irq_enabled(&config->core_safety_lock); } -#ifndef OSI_STRIPPED_LIB /** * @brief Initialize the eqos_core_safety_config. * @@ -387,9 +387,7 @@ static nve32_t eqos_config_flow_control( } /* Write to MAC Tx Flow control Register of Q0 */ - eqos_core_safety_writel(osi_core, val, (nveu8_t *)addr + - EQOS_MAC_QX_TX_FLW_CTRL(0U), - EQOS_MAC_Q0_TXFC_IDX); + osi_writela(osi_core, val, (nveu8_t *)addr + EQOS_MAC_QX_TX_FLW_CTRL(0U)); /* Configure MAC Rx Flow control*/ /* Read MAC Rx Flow control Register */ @@ -595,9 +593,7 @@ static nve32_t eqos_pad_calibrate(struct osi_core_priv_data *const osi_core) (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); value |= EQOS_PAD_AUTO_CAL_CFG_START | EQOS_PAD_AUTO_CAL_CFG_ENABLE; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)ioaddr + - EQOS_PAD_AUTO_CAL_CFG, - EQOS_PAD_AUTO_CAL_CFG_IDX); + osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); /* 4. Wait on 10 to 12 us before start checking for calibration done. * This delay is consumed in delay inside while loop. @@ -687,9 +683,8 @@ static nve32_t eqos_pad_calibrate(struct osi_core_priv_data *const osi_core) (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); value |= EQOS_PAD_AUTO_CAL_CFG_START | EQOS_PAD_AUTO_CAL_CFG_ENABLE; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)ioaddr + - EQOS_PAD_AUTO_CAL_CFG, - EQOS_PAD_AUTO_CAL_CFG_IDX); + osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); + /* 4. Wait on 1 to 3 us before start checking for calibration done. * This delay is consumed in delay inside while loop. */ @@ -867,9 +862,9 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t q_inx, { nveu32_t value = 0; nve32_t ret = 0; - nveu32_t qinx = (q_inx & 0xFU); + nveu32_t que_idx = (q_inx & 0xFU); - ret = hw_flush_mtl_tx_queue(osi_core, qinx); + ret = hw_flush_mtl_tx_queue(osi_core, que_idx); if (ret < 0) { return ret; } @@ -879,13 +874,11 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t q_inx, value |= EQOS_MTL_TSF; /* Enable TxQ */ value |= EQOS_MTL_TXQEN; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MTL_CHX_TX_OP_MODE(qinx), - EQOS_MTL_CH0_TX_OP_MODE_IDX + qinx); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MTL_CHX_TX_OP_MODE(que_idx)); /* read RX Q0 Operating Mode Register */ value = osi_readla(osi_core, (nveu8_t *)osi_core->base + - EQOS_MTL_CHX_RX_OP_MODE(qinx)); + EQOS_MTL_CHX_RX_OP_MODE(que_idx)); value |= (rx_fifo << EQOS_MTL_RXQ_SIZE_SHIFT); /* Enable Store and Forward mode */ value |= EQOS_MTL_RSF; @@ -895,24 +888,19 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t q_inx, * RFD: Threshold for Deactivating Flow Control */ update_ehfc_rfa_rfd(rx_fifo, &value); - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MTL_CHX_RX_OP_MODE(qinx), - EQOS_MTL_CH0_RX_OP_MODE_IDX + qinx); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MTL_CHX_RX_OP_MODE(que_idx)); /* Transmit Queue weight */ value = osi_readla(osi_core, (nveu8_t *)osi_core->base + - EQOS_MTL_TXQ_QW(qinx)); + EQOS_MTL_TXQ_QW(que_idx)); value |= EQOS_MTL_TXQ_QW_ISCQW; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MTL_TXQ_QW(qinx), - EQOS_MTL_TXQ0_QW_IDX + qinx); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MTL_TXQ_QW(que_idx)); /* Enable Rx Queue Control */ value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_RQC0R); - value |= ((osi_core->rxq_ctrl[qinx] & EQOS_RXQ_EN_MASK) << (qinx * 2U)); - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_RQC0R, EQOS_MAC_RQC0R_IDX); + value |= ((osi_core->rxq_ctrl[que_idx] & EQOS_RXQ_EN_MASK) << (que_idx * 2U)); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_RQC0R); return 0; } @@ -1275,9 +1263,7 @@ static void eqos_configure_rxq_priority( mfix_var2 <<= mfix_var1; val |= (temp & mfix_var2); /* Priorities Selected in the Receive Queue 0 */ - eqos_core_safety_writel(osi_core, val, - (nveu8_t *)osi_core->base + - EQOS_MAC_RQC2R, EQOS_MAC_RQC2R_IDX); + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + EQOS_MAC_RQC2R); } } @@ -1308,8 +1294,7 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core, value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); value |= EQOS_IMR_TXESIE; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_IMR, EQOS_MAC_IMR_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); /* T23X-EQOS_HSIv2-1: Enabling of Memory ECC */ value = osi_readla(osi_core, @@ -1375,8 +1360,7 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core, value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); value &= ~EQOS_IMR_TXESIE; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_IMR, EQOS_MAC_IMR_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); /* T23X-EQOS_HSIv2-1: Disable of Memory ECC */ value = osi_readla(osi_core, @@ -1483,8 +1467,7 @@ static void eqos_configure_mac(struct osi_core_priv_data *const osi_core) /* do nothing for default mtu size */ } - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_MCR, EQOS_MAC_MCR_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_MCR); /* Enable common interrupt at wrapper level */ if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) { @@ -1511,12 +1494,11 @@ static void eqos_configure_mac(struct osi_core_priv_data *const osi_core) /* Routing Multicast and Broadcast depending on mac version */ value &= ~(EQOS_MAC_RQC1R_MCBCQ); if (osi_core->mac_ver > OSI_EQOS_MAC_5_00) { - value |= EQOS_MAC_RQC1R_MCBCQ7 << EQOS_MAC_RQC1R_MCBCQ_SHIFT; + value |= ((nveu32_t)EQOS_MAC_RQC1R_MCBCQ7) << EQOS_MAC_RQC1R_MCBCQ_SHIFT; } else { - value |= EQOS_MAC_RQC1R_MCBCQ3 << EQOS_MAC_RQC1R_MCBCQ_SHIFT; + value |= ((nveu32_t)EQOS_MAC_RQC1R_MCBCQ3) << EQOS_MAC_RQC1R_MCBCQ_SHIFT; } - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_RQC1R, EQOS_MAC_RQC1R_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_RQC1R); /* Disable all MMC interrupts */ /* Disable all MMC Tx Interrupts */ @@ -1544,8 +1526,7 @@ static void eqos_configure_mac(struct osi_core_priv_data *const osi_core) /* RGSMIIIE - RGMII/SMII interrupt Enable. * LPIIE is not enabled. MMC LPI counters is maintained in HW */ value |= EQOS_IMR_RGSMIIIE; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_IMR, EQOS_MAC_IMR_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); /* Enable VLAN configuration */ value = osi_readla(osi_core, @@ -1628,9 +1609,7 @@ static void eqos_configure_dma(struct osi_core_priv_data *const osi_core) /* AXI Maximum Write Outstanding Request Limit = 31 */ value |= EQOS_DMA_SBUS_WR_OSR_LMT; - eqos_core_safety_writel(osi_core, value, - (nveu8_t *)base + EQOS_DMA_SBUS, - EQOS_DMA_SBUS_IDX); + osi_writela(osi_core, value, (nveu8_t *)base + EQOS_DMA_SBUS); value = osi_readla(osi_core, (nveu8_t *)base + EQOS_DMA_BMR); value |= EQOS_DMA_BMR_DPSW; @@ -1709,8 +1688,8 @@ static void eqos_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core) * @retval -1 on failure. */ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core, - const nveu32_t tx_fifo_size, - const nveu32_t rx_fifo_size) + nveu32_t tx_fifo_size, + nveu32_t rx_fifo_size) { nve32_t ret = 0; nveu32_t qinx = 0; @@ -1774,15 +1753,10 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core, value1 = EQOS_RXQ_TO_DMA_CHAN_MAP1; } - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MTL_RXQ_DMA_MAP0, - EQOS_MTL_RXQ_DMA_MAP0_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MTL_RXQ_DMA_MAP0); if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) { - eqos_core_safety_writel(osi_core, value1, - (nveu8_t *)osi_core->base + - EQOS_MTL_RXQ_DMA_MAP1, - EQOS_MTL_RXQ_DMA_MAP1_IDX); + osi_writela(osi_core, value1, (nveu8_t *)osi_core->base + EQOS_MTL_RXQ_DMA_MAP1); } if (osi_unlikely(osi_core->num_mtl_queues > OSI_EQOS_MAX_NUM_QUEUES)) { @@ -1993,14 +1967,17 @@ static void eqos_handle_mac_intrs(struct osi_core_priv_data *const osi_core, /* set speed at MAC level */ /* TODO: set_tx_clk needs to be done */ /* Maybe through workqueue for QNX */ + /* hw_set_speed is treated as void since it is + * an internal functin which will be always success + */ if ((mac_pcs & EQOS_MAC_PCS_LNKSPEED) == EQOS_MAC_PCS_LNKSPEED_10) { - hw_set_speed(osi_core, OSI_SPEED_10); + (void)hw_set_speed(osi_core, OSI_SPEED_10); } else if ((mac_pcs & EQOS_MAC_PCS_LNKSPEED) == EQOS_MAC_PCS_LNKSPEED_100) { - hw_set_speed(osi_core, OSI_SPEED_100); + (void)hw_set_speed(osi_core, OSI_SPEED_100); } else if ((mac_pcs & EQOS_MAC_PCS_LNKSPEED) == EQOS_MAC_PCS_LNKSPEED_1000) { - hw_set_speed(osi_core, OSI_SPEED_1000); + (void)hw_set_speed(osi_core, OSI_SPEED_1000); } else { /* Nothing here */ } @@ -2424,16 +2401,12 @@ static void eqos_config_mac_tx(struct osi_core_priv_data *const osi_core, value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_MCR); /* Enable MAC Transmit */ value |= EQOS_MCR_TE; - eqos_core_safety_writel(osi_core, value, - (nveu8_t *)addr + EQOS_MAC_MCR, - EQOS_MAC_MCR_IDX); + osi_writela(osi_core, value, (nveu8_t *)addr + EQOS_MAC_MCR); } else { value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_MCR); /* Disable MAC Transmit */ value &= ~EQOS_MCR_TE; - eqos_core_safety_writel(osi_core, value, - (nveu8_t *)addr + EQOS_MAC_MCR, - EQOS_MAC_MCR_IDX); + osi_writela(osi_core, value, (nveu8_t *)addr + EQOS_MAC_MCR); } } #endif /* MACSEC_SUPPORT */ @@ -2791,8 +2764,7 @@ static nve32_t eqos_config_ptp_offload(struct osi_core_priv_data *const osi_core if (pto_config->en_dis == OSI_DISABLE) { osi_core->ptp_config.ptp_filter = value; osi_writela(osi_core, ptc_value, addr + EQOS_MAC_PTO_CR); - eqos_core_safety_writel(osi_core, value, addr + - EQOS_MAC_TCR, EQOS_MAC_TCR_IDX); + osi_writela(osi_core, value, addr + EQOS_MAC_TCR); osi_writela(osi_core, OSI_NONE, addr + EQOS_MAC_PIDR0); osi_writela(osi_core, OSI_NONE, addr + EQOS_MAC_PIDR1); osi_writela(osi_core, OSI_NONE, addr + EQOS_MAC_PIDR2); @@ -2845,8 +2817,7 @@ static nve32_t eqos_config_ptp_offload(struct osi_core_priv_data *const osi_core osi_core->ptp_config.ptp_filter = value; /** Write PTO_CR and TCR registers */ osi_writela(osi_core, ptc_value, addr + EQOS_MAC_PTO_CR); - eqos_core_safety_writel(osi_core, value, addr + EQOS_MAC_TCR, - EQOS_MAC_TCR_IDX); + osi_writela(osi_core, value, addr + EQOS_MAC_TCR); /* Port ID for PTP offload packet created */ port_id = pto_config->portid & EQOS_MAC_PIDR_PID_MASK; osi_writela(osi_core, port_id, addr + EQOS_MAC_PIDR0); @@ -3545,9 +3516,7 @@ static nve32_t eqos_adjust_mactime(struct osi_core_priv_data *const osi_core, * specified in MAC_STSUR and MAC_STNSUR */ mac_tcr |= EQOS_MAC_TCR_TSUPDT; - eqos_core_safety_writel(osi_core, mac_tcr, - (nveu8_t *)addr + EQOS_MAC_TCR, - EQOS_MAC_TCR_IDX); + osi_writela(osi_core, mac_tcr, (nveu8_t *)addr + EQOS_MAC_TCR); ret = eqos_poll_for_update_ts_complete(osi_core, &mac_tcr); if (ret == -1) { @@ -4270,9 +4239,7 @@ static nve32_t eqos_set_avb_algorithm( /* Set TxQ/TC mode as per input struct after masking 3 bit */ value |= (avb->oper_mode << EQOS_MTL_TXQEN_MASK_SHIFT) & EQOS_MTL_TXQEN_MASK; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MTL_CHX_TX_OP_MODE(qinx), - EQOS_MTL_CH0_TX_OP_MODE_IDX + qinx); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MTL_CHX_TX_OP_MODE(qinx)); /* Set Algo and Credit control */ value = OSI_DISABLE; @@ -4489,9 +4456,7 @@ static nve32_t eqos_config_arp_offload( mac_mcr &= ~EQOS_MCR_ARPEN; } - eqos_core_safety_writel(osi_core, mac_mcr, - (nveu8_t *)addr + EQOS_MAC_MCR, - EQOS_MAC_MCR_IDX); + osi_writela(osi_core, mac_mcr, (nveu8_t *)addr + EQOS_MAC_MCR); return 0; } @@ -4555,8 +4520,7 @@ static nve32_t eqos_config_vlan_filtering( value = osi_readla(osi_core, (nveu8_t *)base + EQOS_MAC_PFR); value &= ~(EQOS_MAC_PFR_VTFE); value |= ((filter_enb_dis << EQOS_MAC_PFR_SHIFT) & EQOS_MAC_PFR_VTFE); - eqos_core_safety_writel(osi_core, value, (nveu8_t *)base + EQOS_MAC_PFR, - EQOS_MAC_PFR_IDX); + osi_writela(osi_core, value, (nveu8_t *)base + EQOS_MAC_PFR); value = osi_readla(osi_core, (nveu8_t *)base + EQOS_MAC_VLAN_TR); value &= ~(EQOS_MAC_VLAN_TR_VTIM | EQOS_MAC_VLAN_TR_VTHM); @@ -4831,9 +4795,7 @@ static nve32_t eqos_config_mac_loopback( (nveu8_t *)addr + EQOS_CLOCK_CTRL_0); /* Write to MAC Configuration Register */ - eqos_core_safety_writel(osi_core, mcr_val, - (nveu8_t *)addr + EQOS_MAC_MCR, - EQOS_MAC_MCR_IDX); + osi_writela(osi_core, mcr_val, (nveu8_t *)addr + EQOS_MAC_MCR); return 0; } @@ -5114,8 +5076,7 @@ static nve32_t eqos_pre_pad_calibrate(struct osi_core_priv_data *const osi_core) /* Read MAC IMR Register */ value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); value &= ~(EQOS_IMR_RGSMIIIE); - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_IMR, EQOS_MAC_IMR_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); hw_stop_mac(osi_core); ret = poll_for_mii_idle(osi_core); if (ret < 0) { @@ -5152,8 +5113,7 @@ error: /* Read MAC IMR Register */ value = osi_readl((nveu8_t *)osi_core->base + EQOS_MAC_IMR); value |= EQOS_IMR_RGSMIIIE; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + - EQOS_MAC_IMR, EQOS_MAC_IMR_IDX); + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); return ret; } @@ -5208,8 +5168,7 @@ static nve32_t eqos_post_pad_calibrate( hw_start_mac(osi_core); /* Enable MAC RGSMIIIE - RGMII/SMII interrupts */ mac_imr |= EQOS_IMR_RGSMIIIE; - eqos_core_safety_writel(osi_core, mac_imr, (nveu8_t *)osi_core->base + - EQOS_MAC_IMR, EQOS_MAC_IMR_IDX); + osi_writela(osi_core, mac_imr, (nveu8_t *)osi_core->base + EQOS_MAC_IMR); return ret; } #endif /* UPDATED_PAD_CAL */ diff --git a/osi/core/eqos_core.h b/osi/core/eqos_core.h index fd963f0..75a6268 100644 --- a/osi/core/eqos_core.h +++ b/osi/core/eqos_core.h @@ -642,6 +642,27 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value); +#define EQOS_MAX_CORE_SAFETY_REGS 45U + +/** + * @brief core_func_safety - Struct used to store last written values of + * critical core HW registers. + */ +struct core_func_safety { + /** Array of reg MMIO addresses (base of EQoS + offset of reg) */ + void *reg_addr[EQOS_MAX_CORE_SAFETY_REGS]; + /** Array of bit-mask value of each corresponding reg + * (used to ignore self-clearing/reserved bits in reg) + */ + nveu32_t reg_mask[EQOS_MAX_CORE_SAFETY_REGS]; + /** Array of value stored in each corresponding register */ + nveu32_t reg_val[EQOS_MAX_CORE_SAFETY_REGS]; + /** OSI lock variable used to protect writes to reg while + * validation is in-progress + */ + nveu32_t core_safety_lock; +}; + /** * @addtogroup EQOS-Safety-Register EQOS Safety Register Mask * @@ -654,6 +675,7 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value); * EQOS_MAX_CORE_SAFETY_REGS. * Using macro instead of enum due to misra error. */ +#ifndef OSI_STRIPPED_LIB #define EQOS_MAC_MCR_IDX 0U #define EQOS_MAC_PFR_IDX 1U #define EQOS_MAC_RQC0R_IDX 7U @@ -668,27 +690,8 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value); #define EQOS_MTL_CH0_RX_OP_MODE_IDX 34U #define EQOS_DMA_SBUS_IDX 43U #define EQOS_MTL_RXQ_DMA_MAP1_IDX 44U -#define EQOS_MAX_CORE_SAFETY_REGS 45U /** @} */ -/** - * @brief core_func_safety - Struct used to store last written values of - * critical core HW registers. - */ -struct core_func_safety { - /** Array of reg MMIO addresses (base of EQoS + offset of reg) */ - void *reg_addr[EQOS_MAX_CORE_SAFETY_REGS]; - /** Array of bit-mask value of each corresponding reg - * (used to ignore self-clearing/reserved bits in reg) */ - nveu32_t reg_mask[EQOS_MAX_CORE_SAFETY_REGS]; - /** Array of value stored in each corresponding register */ - nveu32_t reg_val[EQOS_MAX_CORE_SAFETY_REGS]; - /** OSI lock variable used to protect writes to reg while - * validation is in-progress */ - nveu32_t core_safety_lock; -}; - -#ifndef OSI_STRIPPED_LIB /** * @addtogroup EQOS_HW EQOS HW BACKUP registers * diff --git a/osi/core/ivc_core.c b/osi/core/ivc_core.c index aec2d6e..1820778 100644 --- a/osi/core/ivc_core.c +++ b/osi/core/ivc_core.c @@ -30,11 +30,6 @@ #include "../osi/common/common.h" #include "macsec.h" -/** - * @brief ivc_safety_config - EQOS MAC core safety configuration - */ -static struct core_func_safety ivc_safety_config; - /** * @brief ivc_handle_ioctl - marshell input argument to handle runtime command * @@ -55,29 +50,31 @@ static nve32_t ivc_handle_ioctl(struct osi_core_priv_data *osi_core, osi_memset(&msg, 0, sizeof(msg)); msg.cmd = handle_ioctl; - msg.status = osi_memcpy((void *)&msg.data.ioctl_data, - (void *)data, - sizeof(struct osi_ioctl)); + /* osi_memcpy is treated as void since it is + * an internal functin which will be always success + */ + (void)osi_memcpy((void *)&msg.data.ioctl_data, (void *)data, + sizeof(struct osi_ioctl)); if (data->cmd == OSI_CMD_CONFIG_PTP) { - osi_memcpy((void *)&msg.data.ioctl_data.ptp_config, - (void *)&osi_core->ptp_config, - sizeof(struct osi_ptp_config)); + (void)osi_memcpy((void *)&msg.data.ioctl_data.ptp_config, + (void *)&osi_core->ptp_config, + sizeof(struct osi_ptp_config)); } ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (data->cmd == OSI_CMD_READ_MMC) { - msg.status = osi_memcpy((void *)&osi_core->mmc, - (void *)&msg.data.mmc, - sizeof(struct osi_mmc_counters)); - msg.status = osi_memcpy((void *)&osi_core->tsn_stats, - (void *)&msg.data.eth_stats.tsn_s, - sizeof(struct osi_tsn_stats)); + (void)osi_memcpy((void *)&osi_core->mmc, + (void *)&msg.data.mmc, + sizeof(struct osi_mmc_counters)); + (void)osi_memcpy((void *)&osi_core->tsn_stats, + (void *)&msg.data.eth_stats.tsn_s, + sizeof(struct osi_tsn_stats)); } else { - msg.status = osi_memcpy((void *)data, - (void *)&msg.data.ioctl_data, - sizeof(struct osi_ioctl)); + (void)osi_memcpy((void *)data, + (void *)&msg.data.ioctl_data, + sizeof(struct osi_ioctl)); } return ret; } @@ -214,18 +211,18 @@ static nve32_t ivc_macsec_dbg_events_config( msg.cmd = dbg_events_config_macsec; - msg.status = osi_memcpy((void *)&msg.data.dbg_buf_config, - (void *)dbg_buf_config, - sizeof(struct osi_macsec_dbg_buf_config)); + (void)osi_memcpy((void *)&msg.data.dbg_buf_config, + (void *)dbg_buf_config, + sizeof(struct osi_macsec_dbg_buf_config)); ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { goto done; } - msg.status = osi_memcpy((void *)dbg_buf_config, - (void *)&msg.data.dbg_buf_config, - sizeof(struct osi_macsec_dbg_buf_config)); + (void)osi_memcpy((void *)dbg_buf_config, + (void *)&msg.data.dbg_buf_config, + sizeof(struct osi_macsec_dbg_buf_config)); done: return ret; } @@ -250,18 +247,18 @@ static nve32_t ivc_macsec_dbg_buf_config( msg.cmd = dbg_buf_config_macsec; - msg.status = osi_memcpy((void *)&msg.data.dbg_buf_config, - (void *)dbg_buf_config, - sizeof(struct osi_macsec_dbg_buf_config)); + (void)osi_memcpy((void *)&msg.data.dbg_buf_config, + (void *)dbg_buf_config, + sizeof(struct osi_macsec_dbg_buf_config)); ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { goto done; } - msg.status = osi_memcpy((void *)dbg_buf_config, - (void *) &msg.data.dbg_buf_config, - sizeof(struct osi_macsec_dbg_buf_config)); + (void)osi_memcpy((void *)dbg_buf_config, + (void *) &msg.data.dbg_buf_config, + sizeof(struct osi_macsec_dbg_buf_config)); done: return ret; } @@ -289,12 +286,12 @@ static void ivc_macsec_read_mmc(struct osi_core_priv_data *const osi_core) msg.status = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); - msg.status = osi_memcpy((void *)&osi_core->macsec_mmc, - (void *) &msg.data.macsec_mmc, - sizeof(struct osi_macsec_mmc_counters)); - msg.status = osi_memcpy((void *)&osi_core->macsec_irq_stats, - (void *) &msg.data.macsec_irq_stats, - sizeof(struct osi_macsec_irq_stats)); + (void)osi_memcpy((void *)&osi_core->macsec_mmc, + (void *) &msg.data.macsec_mmc, + sizeof(struct osi_macsec_mmc_counters)); + (void)osi_memcpy((void *)&osi_core->macsec_irq_stats, + (void *) &msg.data.macsec_irq_stats, + sizeof(struct osi_macsec_irq_stats)); } /** @@ -319,9 +316,9 @@ static nve32_t ivc_get_sc_lut_key_index(struct osi_core_priv_data *const osi_cor osi_memset(&msg, 0, sizeof(msg)); msg.cmd = macsec_get_sc_lut_key_index; - msg.status = osi_memcpy((void *) &msg.data.macsec_cfg.sci, - (void *)sci, - OSI_SCI_LEN); + (void)osi_memcpy((void *) &msg.data.macsec_cfg.sci, + (void *)sci, + OSI_SCI_LEN); msg.data.macsec_cfg.ctlr = ctlr; ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); @@ -356,9 +353,9 @@ static nve32_t ivc_macsec_config(struct osi_core_priv_data *const osi_core, osi_memset(&msg, 0, sizeof(msg)); msg.cmd = config_macsec; - msg.status = osi_memcpy((void *) &msg.data.macsec_cfg.sc_info, - (void *)sc, - sizeof(struct osi_macsec_sc_info)); + (void)osi_memcpy((void *) &msg.data.macsec_cfg.sc_info, + (void *)sc, + sizeof(struct osi_macsec_sc_info)); msg.data.macsec_cfg.enable = enable; msg.data.macsec_cfg.ctlr = ctlr; msg.data.macsec_cfg.kt_idx = *kt_idx; @@ -444,18 +441,18 @@ static nve32_t ivc_macsec_kt_config(struct osi_core_priv_data *const osi_core, osi_memset(&msg, 0, sizeof(msg)); msg.cmd = kt_config_macsec; - msg.status = osi_memcpy((void *) &msg.data.kt_config, - (void *)kt_config, - sizeof(struct osi_macsec_kt_config)); + (void)osi_memcpy((void *) &msg.data.kt_config, + (void *)kt_config, + sizeof(struct osi_macsec_kt_config)); ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { return ret; } - msg.status = osi_memcpy((void *)kt_config, - (void *)&msg.data.kt_config, - sizeof(struct osi_macsec_kt_config)); + (void)osi_memcpy((void *)kt_config, + (void *)&msg.data.kt_config, + sizeof(struct osi_macsec_kt_config)); return ret; } #endif /* MACSEC_KEY_PROGRAM */ @@ -502,18 +499,18 @@ static nve32_t ivc_macsec_lut_config(struct osi_core_priv_data *const osi_core, osi_memset(&msg, 0, sizeof(msg)); msg.cmd = lut_config_macsec; - msg.status = osi_memcpy((void *) &msg.data.lut_config, - (void *)lut_config, - sizeof(struct osi_macsec_lut_config)); + (void)osi_memcpy((void *) &msg.data.lut_config, + (void *)lut_config, + sizeof(struct osi_macsec_lut_config)); ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { goto done; } - msg.status = osi_memcpy((void *)lut_config, - (void *)&msg.data.lut_config, - sizeof(struct osi_macsec_lut_config)); + (void)osi_memcpy((void *)lut_config, + (void *)&msg.data.lut_config, + sizeof(struct osi_macsec_lut_config)); done: return ret; } @@ -614,6 +611,8 @@ void ivc_init_macsec_ops(void *macsecops) */ void *ivc_get_core_safety_config(void) { + static struct core_func_safety ivc_safety_config; + return &ivc_safety_config; } diff --git a/osi/core/macsec.c b/osi/core/macsec.c index c2c9ecd..e566a89 100644 --- a/osi/core/macsec.c +++ b/osi/core/macsec.c @@ -4440,7 +4440,7 @@ static void macsec_intr_config(struct osi_core_priv_data *const osi_core, nveu32 #endif /* DEBUG_MACSEC */ /** - * @brief macsec_init - Inititlizes macsec + * @brief macsec_initialize - Inititlizes macsec * * @note * Algorithm: @@ -4476,8 +4476,7 @@ static void macsec_intr_config(struct osi_core_priv_data *const osi_core, nveu32 * @retval 0 for success * @retval -1 for failure */ -static nve32_t macsec_init(struct osi_core_priv_data *const osi_core, - nveu32_t mtu) +static nve32_t macsec_initialize(struct osi_core_priv_data *const osi_core, nveu32_t mtu) { nveu32_t val = 0; #if defined(MACSEC_SUPPORT) && !defined(OSI_STRIPPED_LIB) @@ -5311,7 +5310,7 @@ exit: } /** - * @brief config_macsec - API to update LUTs for addition/deletion of SC/SA + * @brief macsec_configure - API to update LUTs for addition/deletion of SC/SA * * @note * Algorithm: @@ -5342,10 +5341,10 @@ exit: * @retval 0 on success * @retval -1 on failure */ -static nve32_t config_macsec(struct osi_core_priv_data *const osi_core, - struct osi_macsec_sc_info *const sc, - nveu32_t enable, nveu16_t ctlr, - nveu16_t *kt_idx) +static nve32_t macsec_configure(struct osi_core_priv_data *const osi_core, + struct osi_macsec_sc_info *const sc, + nveu32_t enable, nveu16_t ctlr, + nveu16_t *kt_idx) { struct osi_macsec_sc_info *existing_sc = OSI_NULL; struct osi_macsec_sc_info tmp_sc; @@ -5465,7 +5464,7 @@ nve32_t osi_init_macsec_ops(struct osi_core_priv_data *const osi_core) static struct osi_macsec_core_ops virt_macsec_ops; nve32_t ret = 0; static struct osi_macsec_core_ops macsec_ops = { - .init = macsec_init, + .init = macsec_initialize, .deinit = macsec_deinit, .handle_irq = macsec_handle_irq, .lut_config = macsec_lut_config, @@ -5474,7 +5473,7 @@ nve32_t osi_init_macsec_ops(struct osi_core_priv_data *const osi_core) #endif /* MACSEC_KEY_PROGRAM */ .cipher_config = macsec_cipher_config, .macsec_en = macsec_enable, - .config = config_macsec, + .config = macsec_configure, .read_mmc = macsec_read_mmc, .get_sc_lut_key_index = macsec_get_key_index, .update_mtu = macsec_update_mtu, diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c index 1aaa8a7..8cf7dda 100644 --- a/osi/core/mgbe_core.c +++ b/osi/core/mgbe_core.c @@ -848,18 +848,20 @@ static inline nveu32_t mgbe_set_dcs(struct osi_core_priv_data *osi_core, nveu32_t dma_routing_enable, nveu32_t dma_chan) { + nveu32_t temp = value; + if ((dma_routing_enable == OSI_ENABLE) && (dma_chan < OSI_MGBE_MAX_NUM_CHANS) && (osi_core->dcs_en == OSI_ENABLE)) { - value |= ((dma_routing_enable << - MGBE_MAC_L3L4_CTR_DMCHEN0_SHIFT) & - MGBE_MAC_L3L4_CTR_DMCHEN0); - value |= ((dma_chan << - MGBE_MAC_L3L4_CTR_DMCHN0_SHIFT) & - MGBE_MAC_L3L4_CTR_DMCHN0); + temp |= ((dma_routing_enable << + MGBE_MAC_L3L4_CTR_DMCHEN0_SHIFT) & + MGBE_MAC_L3L4_CTR_DMCHEN0); + temp |= ((dma_chan << + MGBE_MAC_L3L4_CTR_DMCHN0_SHIFT) & + MGBE_MAC_L3L4_CTR_DMCHN0); } - return value; + return temp; } /** @@ -918,7 +920,7 @@ static inline void mgbe_helper_l3l4_bitmask(nveu32_t *bitmask, * @retval 0 on success * @retval -1 on failure. */ -static nve32_t mgbe_config_l3_filters(struct osi_core_priv_data *osi_core, +static nve32_t mgbe_config_l3_filters(struct osi_core_priv_data *const osi_core, const nveu32_t filter_no, const nveu32_t enb_dis, const nveu32_t ipv4_ipv6_match, @@ -2353,7 +2355,7 @@ static nve32_t mgbe_configure_mac(struct osi_core_priv_data *osi_core) /* if MTU greater 9K use GPSLCE */ value |= MGBE_MAC_RMCR_GPSLCE | MGBE_MAC_RMCR_WD; value &= ~MGBE_MAC_RMCR_GPSL_MSK; - value |= ((OSI_MAX_MTU_SIZE << 16) & MGBE_MAC_RMCR_GPSL_MSK); + value |= ((((nveu32_t)OSI_MAX_MTU_SIZE) << 16U) & MGBE_MAC_RMCR_GPSL_MSK); } else { value &= ~MGBE_MAC_RMCR_JE; value &= ~MGBE_MAC_RMCR_GPSLCE; @@ -4033,10 +4035,10 @@ static inline nve32_t mgbe_restore_registers( * @retval 0 on success * @retval -1 on failure. */ -static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *osi_core, - nveu32_t phyaddr, - nveu32_t phyreg, - nveu16_t phydata) +static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *const osi_core, + const nveu32_t phyaddr, + const nveu32_t phyreg, + const nveu16_t phydata) { nve32_t ret = 0; nveu32_t reg; @@ -4063,7 +4065,7 @@ static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *osi_core, /* Program Data register */ reg = phydata | - (MGBE_MDIO_SCCD_CMD_WR << MGBE_MDIO_SCCD_CMD_SHIFT) | + (((nveu32_t)MGBE_MDIO_SCCD_CMD_WR) << MGBE_MDIO_SCCD_CMD_SHIFT) | MGBE_MDIO_SCCD_SBUSY; /** @@ -4073,7 +4075,7 @@ static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *osi_core, * of 2.5MHz only CR need to be set to 5. */ reg &= ~MGBE_MDIO_SCCD_CRS; - reg |= ((0x5U & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT); + reg |= ((((nveu32_t)0x5U) & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT); osi_writela(osi_core, reg, (nveu8_t *) osi_core->base + MGBE_MDIO_SCCD); @@ -4105,9 +4107,9 @@ static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *osi_core, * @retval 0 on success * @retval -1 on failure. */ -static nve32_t mgbe_read_phy_reg(struct osi_core_priv_data *osi_core, - nveu32_t phyaddr, - nveu32_t phyreg) +static nve32_t mgbe_read_phy_reg(struct osi_core_priv_data *const osi_core, + const nveu32_t phyaddr, + const nveu32_t phyreg) { nveu32_t reg; nveu32_t data; @@ -4133,7 +4135,7 @@ static nve32_t mgbe_read_phy_reg(struct osi_core_priv_data *osi_core, osi_core->base + MGBE_MDIO_SCCA); /* Program Data register */ - reg = (MGBE_MDIO_SCCD_CMD_RD << MGBE_MDIO_SCCD_CMD_SHIFT) | + reg = (((nveu32_t)MGBE_MDIO_SCCD_CMD_RD) << MGBE_MDIO_SCCD_CMD_SHIFT) | MGBE_MDIO_SCCD_SBUSY; /** @@ -4143,7 +4145,7 @@ static nve32_t mgbe_read_phy_reg(struct osi_core_priv_data *osi_core, * of 2.5MHz only CR need to be set to 5. */ reg &= ~MGBE_MDIO_SCCD_CRS; - reg |= ((0x5U & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT); + reg |= ((((nveu32_t)0x5U) & MGBE_MDIO_SCCD_CR_MASK) << MGBE_MDIO_SCCD_CR_SHIFT); osi_writela(osi_core, reg, (nveu8_t *) osi_core->base + MGBE_MDIO_SCCD); @@ -4511,17 +4513,21 @@ static inline nve32_t mgbe_poll_for_update_ts_complete( * @retval 0 on success * @retval -1 on failure. */ -static nve32_t mgbe_adjust_mactime(struct osi_core_priv_data *osi_core, - nveu32_t sec, nveu32_t nsec, - nveu32_t add_sub, - nveu32_t one_nsec_accuracy) +static nve32_t mgbe_adjust_mactime(struct osi_core_priv_data *const osi_core, + const nveu32_t sec, const nveu32_t nsec, + const nveu32_t add_sub, + const nveu32_t one_nsec_accuracy) { void *addr = osi_core->base; nveu32_t mac_tcr; nveu32_t value = 0; nveul64_t temp = 0; + nveu32_t temp_sec; + nveu32_t temp_nsec; nve32_t ret; + temp_sec = sec; + temp_nsec = nsec; /* To be sure previous write was flushed (if Any) */ ret = mgbe_poll_for_update_ts_complete(osi_core, &mac_tcr); if (ret == -1) { @@ -4533,9 +4539,9 @@ static nve32_t mgbe_adjust_mactime(struct osi_core_priv_data *osi_core, * the system time, then MAC_STSUR reg should be * programmed with (2^32 – ) */ - temp = (TWO_POWER_32 - sec); + temp = (TWO_POWER_32 - temp_sec); if (temp < UINT_MAX) { - sec = (nveu32_t)temp; + temp_sec = (nveu32_t)temp; } else { /* do nothing here */ } @@ -4547,23 +4553,23 @@ static nve32_t mgbe_adjust_mactime(struct osi_core_priv_data *osi_core, * (2^32 - if MAC_TCR.TSCTRLSSR is reset) */ if (one_nsec_accuracy == OSI_ENABLE) { - if (nsec < UINT_MAX) { - nsec = (TEN_POWER_9 - nsec); + if (temp_nsec < UINT_MAX) { + temp_nsec = (TEN_POWER_9 - temp_nsec); } } else { - if (nsec < UINT_MAX) { - nsec = (TWO_POWER_31 - nsec); + if (temp_nsec < UINT_MAX) { + temp_nsec = (TWO_POWER_31 - temp_nsec); } } } /* write seconds value to MAC_System_Time_Seconds_Update register */ - osi_writela(osi_core, sec, (nveu8_t *)addr + MGBE_MAC_STSUR); + osi_writela(osi_core, temp_sec, (nveu8_t *)addr + MGBE_MAC_STSUR); /* write nano seconds value and add_sub to * MAC_System_Time_Nanoseconds_Update register */ - value |= nsec; + value |= temp_nsec; value |= (add_sub << MGBE_MAC_STNSUR_ADDSUB_SHIFT); osi_writela(osi_core, value, (nveu8_t *)addr + MGBE_MAC_STNSUR); diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h index 1f89cd9..0b4ae00 100644 --- a/osi/core/mgbe_core.h +++ b/osi/core/mgbe_core.h @@ -162,6 +162,9 @@ #define MGBE_MAC_PFR_VTFE_SHIFT 16 #define MGBE_MAC_PIDR_PID_MASK 0XFFFFU +#define MGBE_MTL_RXP_BYPASS_CNT 2U +#define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1) + #endif /* !OSI_STRIPPED_LIB */ #define MGBE_MTL_EST_CONTROL 0x1050 @@ -229,7 +232,6 @@ #define MGBE_MAC_FPE_CTS_TRSP OSI_BIT(19) #define MGBE_MAC_FPE_CTS_TVER OSI_BIT(18) #define MGBE_MAC_FPE_CTS_RVER OSI_BIT(16) -#define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1) #define MGBE_MAC_FPE_CTS_SRSP OSI_BIT(2) /* MTL FPE adv registers */ #define MGBE_MAC_IMR_FPEIS OSI_BIT(16) @@ -308,7 +310,6 @@ #define MGBE_MTL_FRP_IE2_AF OSI_BIT(0) #define MGBE_MTL_FRP_IE3_DCH_MASK 0xFFFFU /* Indirect register defines */ -#define MGBE_MTL_RXP_BYPASS_CNT 2U #define MGBE_MTL_RXP_IND_CS_BUSY OSI_BIT(31) #define MGBE_MTL_RXP_IND_CS_ACCSEL OSI_BIT(24) #define MGBE_MTL_RXP_IND_CS_WRRDN OSI_BIT(16) diff --git a/osi/core/mgbe_mmc.c b/osi/core/mgbe_mmc.c index 10f6563..3a522f2 100644 --- a/osi/core/mgbe_mmc.c +++ b/osi/core/mgbe_mmc.c @@ -27,7 +27,7 @@ #include "mgbe_core.h" /** - * @brief update_mmc_val - function to read register and return value to callee + * @brief mgbe_update_mmc_val - function to read register and return value to callee * * Algorithm: Read the registers, check for boundary, if more, reset * counters else return same to caller. @@ -43,9 +43,9 @@ * @retval 0 on MMC counters overflow * @retval value on current MMC counter value. */ -static inline nveu64_t update_mmc_val(struct osi_core_priv_data *osi_core, - nveu64_t last_value, - nveu64_t offset) +static inline nveu64_t mgbe_update_mmc_val(struct osi_core_priv_data *osi_core, + nveu64_t last_value, + nveu64_t offset) { nveu64_t temp; nveu32_t value = osi_readl((nveu8_t *)osi_core->base + @@ -62,7 +62,7 @@ static inline nveu64_t update_mmc_val(struct osi_core_priv_data *osi_core, return temp; } - return 0; + return 0ULL; } /** @@ -104,456 +104,456 @@ void mgbe_read_mmc(struct osi_core_priv_data *const osi_core) struct osi_mmc_counters *mmc = &osi_core->mmc; mmc->mmc_tx_octetcount_gb = - update_mmc_val(osi_core, mmc->mmc_tx_octetcount_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_octetcount_gb, MMC_TXOCTETCOUNT_GB_L); mmc->mmc_tx_octetcount_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_octetcount_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_octetcount_gb_h, MMC_TXOCTETCOUNT_GB_H); mmc->mmc_tx_framecount_gb = - update_mmc_val(osi_core, mmc->mmc_tx_framecount_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_framecount_gb, MMC_TXPACKETCOUNT_GB_L); mmc->mmc_tx_framecount_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_framecount_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_framecount_gb_h, MMC_TXPACKETCOUNT_GB_H); mmc->mmc_tx_broadcastframe_g = - update_mmc_val(osi_core, mmc->mmc_tx_broadcastframe_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_broadcastframe_g, MMC_TXBROADCASTPACKETS_G_L); mmc->mmc_tx_broadcastframe_g_h = - update_mmc_val(osi_core, mmc->mmc_tx_broadcastframe_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_broadcastframe_g_h, MMC_TXBROADCASTPACKETS_G_H); mmc->mmc_tx_multicastframe_g = - update_mmc_val(osi_core, mmc->mmc_tx_multicastframe_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_multicastframe_g, MMC_TXMULTICASTPACKETS_G_L); mmc->mmc_tx_multicastframe_g_h = - update_mmc_val(osi_core, mmc->mmc_tx_multicastframe_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_multicastframe_g_h, MMC_TXMULTICASTPACKETS_G_H); mmc->mmc_tx_64_octets_gb = - update_mmc_val(osi_core, mmc->mmc_tx_64_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_64_octets_gb, MMC_TX64OCTETS_GB_L); mmc->mmc_tx_64_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_64_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_64_octets_gb_h, MMC_TX64OCTETS_GB_H); mmc->mmc_tx_65_to_127_octets_gb = - update_mmc_val(osi_core, mmc->mmc_tx_65_to_127_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_65_to_127_octets_gb, MMC_TX65TO127OCTETS_GB_L); mmc->mmc_tx_65_to_127_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_65_to_127_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_65_to_127_octets_gb_h, MMC_TX65TO127OCTETS_GB_H); mmc->mmc_tx_128_to_255_octets_gb = - update_mmc_val(osi_core, mmc->mmc_tx_128_to_255_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_128_to_255_octets_gb, MMC_TX128TO255OCTETS_GB_L); mmc->mmc_tx_128_to_255_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_128_to_255_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_128_to_255_octets_gb_h, MMC_TX128TO255OCTETS_GB_H); mmc->mmc_tx_256_to_511_octets_gb = - update_mmc_val(osi_core, mmc->mmc_tx_256_to_511_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_256_to_511_octets_gb, MMC_TX256TO511OCTETS_GB_L); mmc->mmc_tx_256_to_511_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_256_to_511_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_256_to_511_octets_gb_h, MMC_TX256TO511OCTETS_GB_H); mmc->mmc_tx_512_to_1023_octets_gb = - update_mmc_val(osi_core, mmc->mmc_tx_512_to_1023_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_512_to_1023_octets_gb, MMC_TX512TO1023OCTETS_GB_L); mmc->mmc_tx_512_to_1023_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_512_to_1023_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_512_to_1023_octets_gb_h, MMC_TX512TO1023OCTETS_GB_H); mmc->mmc_tx_1024_to_max_octets_gb = - update_mmc_val(osi_core, mmc->mmc_tx_1024_to_max_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_1024_to_max_octets_gb, MMC_TX1024TOMAXOCTETS_GB_L); mmc->mmc_tx_1024_to_max_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_1024_to_max_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_1024_to_max_octets_gb_h, MMC_TX1024TOMAXOCTETS_GB_H); mmc->mmc_tx_unicast_gb = - update_mmc_val(osi_core, mmc->mmc_tx_unicast_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_unicast_gb, MMC_TXUNICASTPACKETS_GB_L); mmc->mmc_tx_unicast_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_unicast_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_unicast_gb_h, MMC_TXUNICASTPACKETS_GB_H); mmc->mmc_tx_multicast_gb = - update_mmc_val(osi_core, mmc->mmc_tx_multicast_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_multicast_gb, MMC_TXMULTICASTPACKETS_GB_L); mmc->mmc_tx_multicast_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_multicast_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_multicast_gb_h, MMC_TXMULTICASTPACKETS_GB_H); mmc->mmc_tx_broadcast_gb = - update_mmc_val(osi_core, mmc->mmc_tx_broadcast_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_broadcast_gb, MMC_TXBROADCASTPACKETS_GB_L); mmc->mmc_tx_broadcast_gb_h = - update_mmc_val(osi_core, mmc->mmc_tx_broadcast_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_broadcast_gb_h, MMC_TXBROADCASTPACKETS_GB_H); mmc->mmc_tx_underflow_error = - update_mmc_val(osi_core, mmc->mmc_tx_underflow_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_underflow_error, MMC_TXUNDERFLOWERROR_L); mmc->mmc_tx_underflow_error_h = - update_mmc_val(osi_core, mmc->mmc_tx_underflow_error_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_underflow_error_h, MMC_TXUNDERFLOWERROR_H); mmc->mmc_tx_singlecol_g = - update_mmc_val(osi_core, mmc->mmc_tx_singlecol_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_singlecol_g, MMC_TXSINGLECOL_G); mmc->mmc_tx_multicol_g = - update_mmc_val(osi_core, mmc->mmc_tx_multicol_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_multicol_g, MMC_TXMULTICOL_G); mmc->mmc_tx_deferred = - update_mmc_val(osi_core, mmc->mmc_tx_deferred, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_deferred, MMC_TXDEFERRED); mmc->mmc_tx_latecol = - update_mmc_val(osi_core, mmc->mmc_tx_latecol, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_latecol, MMC_TXLATECOL); mmc->mmc_tx_exesscol = - update_mmc_val(osi_core, mmc->mmc_tx_exesscol, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_exesscol, MMC_TXEXESSCOL); mmc->mmc_tx_carrier_error = - update_mmc_val(osi_core, mmc->mmc_tx_carrier_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_carrier_error, MMC_TXCARRIERERROR); mmc->mmc_tx_octetcount_g = - update_mmc_val(osi_core, mmc->mmc_tx_octetcount_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_octetcount_g, MMC_TXOCTETCOUNT_G_L); mmc->mmc_tx_octetcount_g_h = - update_mmc_val(osi_core, mmc->mmc_tx_octetcount_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_octetcount_g_h, MMC_TXOCTETCOUNT_G_H); mmc->mmc_tx_framecount_g = - update_mmc_val(osi_core, mmc->mmc_tx_framecount_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_framecount_g, MMC_TXPACKETSCOUNT_G_L); mmc->mmc_tx_framecount_g_h = - update_mmc_val(osi_core, mmc->mmc_tx_framecount_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_framecount_g_h, MMC_TXPACKETSCOUNT_G_H); mmc->mmc_tx_excessdef = - update_mmc_val(osi_core, mmc->mmc_tx_excessdef, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_excessdef, MMC_TXEXECESS_DEFERRED); mmc->mmc_tx_pause_frame = - update_mmc_val(osi_core, mmc->mmc_tx_pause_frame, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_pause_frame, MMC_TXPAUSEPACKETS_L); mmc->mmc_tx_pause_frame_h = - update_mmc_val(osi_core, mmc->mmc_tx_pause_frame_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_pause_frame_h, MMC_TXPAUSEPACKETS_H); mmc->mmc_tx_vlan_frame_g = - update_mmc_val(osi_core, mmc->mmc_tx_vlan_frame_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_vlan_frame_g, MMC_TXVLANPACKETS_G_L); mmc->mmc_tx_vlan_frame_g_h = - update_mmc_val(osi_core, mmc->mmc_tx_vlan_frame_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_vlan_frame_g_h, MMC_TXVLANPACKETS_G_H); mmc->mmc_rx_framecount_gb = - update_mmc_val(osi_core, mmc->mmc_rx_framecount_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_framecount_gb, MMC_RXPACKETCOUNT_GB_L); mmc->mmc_rx_framecount_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_framecount_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_framecount_gb_h, MMC_RXPACKETCOUNT_GB_H); mmc->mmc_rx_octetcount_gb = - update_mmc_val(osi_core, mmc->mmc_rx_octetcount_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_octetcount_gb, MMC_RXOCTETCOUNT_GB_L); mmc->mmc_rx_octetcount_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_octetcount_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_octetcount_gb_h, MMC_RXOCTETCOUNT_GB_H); mmc->mmc_rx_octetcount_g = - update_mmc_val(osi_core, mmc->mmc_rx_octetcount_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_octetcount_g, MMC_RXOCTETCOUNT_G_L); mmc->mmc_rx_octetcount_g_h = - update_mmc_val(osi_core, mmc->mmc_rx_octetcount_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_octetcount_g_h, MMC_RXOCTETCOUNT_G_H); mmc->mmc_rx_broadcastframe_g = - update_mmc_val(osi_core, mmc->mmc_rx_broadcastframe_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_broadcastframe_g, MMC_RXBROADCASTPACKETS_G_L); mmc->mmc_rx_broadcastframe_g_h = - update_mmc_val(osi_core, mmc->mmc_rx_broadcastframe_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_broadcastframe_g_h, MMC_RXBROADCASTPACKETS_G_H); mmc->mmc_rx_multicastframe_g = - update_mmc_val(osi_core, mmc->mmc_rx_multicastframe_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_multicastframe_g, MMC_RXMULTICASTPACKETS_G_L); mmc->mmc_rx_multicastframe_g_h = - update_mmc_val(osi_core, mmc->mmc_rx_multicastframe_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_multicastframe_g_h, MMC_RXMULTICASTPACKETS_G_H); mmc->mmc_rx_crc_error = - update_mmc_val(osi_core, mmc->mmc_rx_crc_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_crc_error, MMC_RXCRCERROR_L); mmc->mmc_rx_crc_error_h = - update_mmc_val(osi_core, mmc->mmc_rx_crc_error_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_crc_error_h, MMC_RXCRCERROR_H); mmc->mmc_rx_align_error = - update_mmc_val(osi_core, mmc->mmc_rx_align_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_align_error, MMC_RXALIGNMENTERROR); mmc->mmc_rx_runt_error = - update_mmc_val(osi_core, mmc->mmc_rx_runt_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_runt_error, MMC_RXRUNTERROR); mmc->mmc_rx_jabber_error = - update_mmc_val(osi_core, mmc->mmc_rx_jabber_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_jabber_error, MMC_RXJABBERERROR); mmc->mmc_rx_undersize_g = - update_mmc_val(osi_core, mmc->mmc_rx_undersize_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_undersize_g, MMC_RXUNDERSIZE_G); mmc->mmc_rx_oversize_g = - update_mmc_val(osi_core, mmc->mmc_rx_oversize_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_oversize_g, MMC_RXOVERSIZE_G); mmc->mmc_rx_64_octets_gb = - update_mmc_val(osi_core, mmc->mmc_rx_64_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_64_octets_gb, MMC_RX64OCTETS_GB_L); mmc->mmc_rx_64_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_64_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_64_octets_gb_h, MMC_RX64OCTETS_GB_H); mmc->mmc_rx_65_to_127_octets_gb = - update_mmc_val(osi_core, mmc->mmc_rx_65_to_127_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_65_to_127_octets_gb, MMC_RX65TO127OCTETS_GB_L); mmc->mmc_rx_65_to_127_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_65_to_127_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_65_to_127_octets_gb_h, MMC_RX65TO127OCTETS_GB_H); mmc->mmc_rx_128_to_255_octets_gb = - update_mmc_val(osi_core, mmc->mmc_rx_128_to_255_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_128_to_255_octets_gb, MMC_RX128TO255OCTETS_GB_L); mmc->mmc_rx_128_to_255_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_128_to_255_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_128_to_255_octets_gb_h, MMC_RX128TO255OCTETS_GB_H); mmc->mmc_rx_256_to_511_octets_gb = - update_mmc_val(osi_core, mmc->mmc_rx_256_to_511_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_256_to_511_octets_gb, MMC_RX256TO511OCTETS_GB_L); mmc->mmc_rx_256_to_511_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_256_to_511_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_256_to_511_octets_gb_h, MMC_RX256TO511OCTETS_GB_H); mmc->mmc_rx_512_to_1023_octets_gb = - update_mmc_val(osi_core, mmc->mmc_rx_512_to_1023_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_512_to_1023_octets_gb, MMC_RX512TO1023OCTETS_GB_L); mmc->mmc_rx_512_to_1023_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_512_to_1023_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_512_to_1023_octets_gb_h, MMC_RX512TO1023OCTETS_GB_H); mmc->mmc_rx_1024_to_max_octets_gb = - update_mmc_val(osi_core, mmc->mmc_rx_1024_to_max_octets_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_1024_to_max_octets_gb, MMC_RX1024TOMAXOCTETS_GB_L); mmc->mmc_rx_1024_to_max_octets_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_1024_to_max_octets_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_1024_to_max_octets_gb_h, MMC_RX1024TOMAXOCTETS_GB_H); mmc->mmc_rx_unicast_g = - update_mmc_val(osi_core, mmc->mmc_rx_unicast_g, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_unicast_g, MMC_RXUNICASTPACKETS_G_L); mmc->mmc_rx_unicast_g_h = - update_mmc_val(osi_core, mmc->mmc_rx_unicast_g_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_unicast_g_h, MMC_RXUNICASTPACKETS_G_H); mmc->mmc_rx_length_error = - update_mmc_val(osi_core, mmc->mmc_rx_length_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_length_error, MMC_RXLENGTHERROR_L); mmc->mmc_rx_length_error_h = - update_mmc_val(osi_core, mmc->mmc_rx_length_error_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_length_error_h, MMC_RXLENGTHERROR_H); mmc->mmc_rx_outofrangetype = - update_mmc_val(osi_core, mmc->mmc_rx_outofrangetype, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_outofrangetype, MMC_RXOUTOFRANGETYPE_L); mmc->mmc_rx_outofrangetype_h = - update_mmc_val(osi_core, mmc->mmc_rx_outofrangetype_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_outofrangetype_h, MMC_RXOUTOFRANGETYPE_H); mmc->mmc_rx_pause_frames = - update_mmc_val(osi_core, mmc->mmc_rx_pause_frames, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_pause_frames, MMC_RXPAUSEPACKETS_L); mmc->mmc_rx_pause_frames_h = - update_mmc_val(osi_core, mmc->mmc_rx_pause_frames_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_pause_frames_h, MMC_RXPAUSEPACKETS_H); mmc->mmc_rx_fifo_overflow = - update_mmc_val(osi_core, mmc->mmc_rx_fifo_overflow, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_fifo_overflow, MMC_RXFIFOOVERFLOW_L); mmc->mmc_rx_fifo_overflow_h = - update_mmc_val(osi_core, mmc->mmc_rx_fifo_overflow_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_fifo_overflow_h, MMC_RXFIFOOVERFLOW_H); mmc->mmc_rx_vlan_frames_gb = - update_mmc_val(osi_core, mmc->mmc_rx_vlan_frames_gb, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_vlan_frames_gb, MMC_RXVLANPACKETS_GB_L); mmc->mmc_rx_vlan_frames_gb_h = - update_mmc_val(osi_core, mmc->mmc_rx_vlan_frames_gb_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_vlan_frames_gb_h, MMC_RXVLANPACKETS_GB_H); mmc->mmc_rx_watchdog_error = - update_mmc_val(osi_core, mmc->mmc_rx_watchdog_error, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_watchdog_error, MMC_RXWATCHDOGERROR); mmc->mmc_tx_lpi_usec_cntr = - update_mmc_val(osi_core, mmc->mmc_tx_lpi_usec_cntr, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_lpi_usec_cntr, MMC_TXLPIUSECCNTR); mmc->mmc_tx_lpi_tran_cntr = - update_mmc_val(osi_core, mmc->mmc_tx_lpi_tran_cntr, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_lpi_tran_cntr, MMC_TXLPITRANCNTR); mmc->mmc_rx_lpi_usec_cntr = - update_mmc_val(osi_core, mmc->mmc_rx_lpi_usec_cntr, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_lpi_usec_cntr, MMC_RXLPIUSECCNTR); mmc->mmc_rx_lpi_tran_cntr = - update_mmc_val(osi_core, mmc->mmc_rx_lpi_tran_cntr, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_lpi_tran_cntr, MMC_RXLPITRANCNTR); mmc->mmc_rx_ipv4_gd = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd, MMC_RXIPV4_GD_PKTS_L); mmc->mmc_rx_ipv4_gd_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd_h, MMC_RXIPV4_GD_PKTS_H); mmc->mmc_rx_ipv4_hderr = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr, MMC_RXIPV4_HDRERR_PKTS_L); mmc->mmc_rx_ipv4_hderr_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr_h, MMC_RXIPV4_HDRERR_PKTS_H); mmc->mmc_rx_ipv4_nopay = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay, MMC_RXIPV4_NOPAY_PKTS_L); mmc->mmc_rx_ipv4_nopay_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay_h, MMC_RXIPV4_NOPAY_PKTS_H); mmc->mmc_rx_ipv4_frag = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag, MMC_RXIPV4_FRAG_PKTS_L); mmc->mmc_rx_ipv4_frag_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag_h, MMC_RXIPV4_FRAG_PKTS_H); mmc->mmc_rx_ipv4_udsbl = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl, MMC_RXIPV4_UBSBL_PKTS_L); mmc->mmc_rx_ipv4_udsbl_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl_h, MMC_RXIPV4_UBSBL_PKTS_H); mmc->mmc_rx_ipv6_gd = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd, MMC_RXIPV6_GD_PKTS_L); mmc->mmc_rx_ipv6_gd_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd_h, MMC_RXIPV6_GD_PKTS_H); mmc->mmc_rx_ipv6_hderr = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr, MMC_RXIPV6_HDRERR_PKTS_L); mmc->mmc_rx_ipv6_hderr_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr_h, MMC_RXIPV6_HDRERR_PKTS_H); mmc->mmc_rx_ipv6_nopay = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay, MMC_RXIPV6_NOPAY_PKTS_L); mmc->mmc_rx_ipv6_nopay_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay_h, MMC_RXIPV6_NOPAY_PKTS_H); mmc->mmc_rx_udp_gd = - update_mmc_val(osi_core, mmc->mmc_rx_udp_gd, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_gd, MMC_RXUDP_GD_PKTS_L); mmc->mmc_rx_udp_gd_h = - update_mmc_val(osi_core, mmc->mmc_rx_udp_gd_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_gd_h, MMC_RXUDP_GD_PKTS_H); mmc->mmc_rx_udp_err = - update_mmc_val(osi_core, mmc->mmc_rx_udp_err, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_err, MMC_RXUDP_ERR_PKTS_L); mmc->mmc_rx_udp_err_h = - update_mmc_val(osi_core, mmc->mmc_rx_udp_err_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_err_h, MMC_RXUDP_ERR_PKTS_H); mmc->mmc_rx_tcp_gd = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd, MMC_RXTCP_GD_PKTS_L); mmc->mmc_rx_tcp_gd_h = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd_h, MMC_RXTCP_GD_PKTS_H); mmc->mmc_rx_tcp_err = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_err, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_err, MMC_RXTCP_ERR_PKTS_L); mmc->mmc_rx_tcp_err_h = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_err_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_err_h, MMC_RXTCP_ERR_PKTS_H); mmc->mmc_rx_icmp_gd = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd, MMC_RXICMP_GD_PKTS_L); mmc->mmc_rx_icmp_gd_h = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd_h, MMC_RXICMP_GD_PKTS_H); mmc->mmc_rx_icmp_err = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_err, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_err, MMC_RXICMP_ERR_PKTS_L); mmc->mmc_rx_icmp_err_h = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_err_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_err_h, MMC_RXICMP_ERR_PKTS_H); mmc->mmc_rx_ipv4_gd_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd_octets, MMC_RXIPV4_GD_OCTETS_L); mmc->mmc_rx_ipv4_gd_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_gd_octets_h, MMC_RXIPV4_GD_OCTETS_H); mmc->mmc_rx_ipv4_hderr_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr_octets, MMC_RXIPV4_HDRERR_OCTETS_L); mmc->mmc_rx_ipv4_hderr_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_hderr_octets_h, MMC_RXIPV4_HDRERR_OCTETS_H); mmc->mmc_rx_ipv4_nopay_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay_octets, MMC_RXIPV4_NOPAY_OCTETS_L); mmc->mmc_rx_ipv4_nopay_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_nopay_octets_h, MMC_RXIPV4_NOPAY_OCTETS_H); mmc->mmc_rx_ipv4_frag_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag_octets, MMC_RXIPV4_FRAG_OCTETS_L); mmc->mmc_rx_ipv4_frag_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_frag_octets_h, MMC_RXIPV4_FRAG_OCTETS_H); mmc->mmc_rx_ipv4_udsbl_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl_octets, MMC_RXIPV4_UDP_CHKSM_DIS_OCT_L); mmc->mmc_rx_ipv4_udsbl_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv4_udsbl_octets_h, MMC_RXIPV4_UDP_CHKSM_DIS_OCT_H); mmc->mmc_rx_udp_gd_octets = - update_mmc_val(osi_core, mmc->mmc_rx_udp_gd_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_gd_octets, MMC_RXUDP_GD_OCTETS_L); mmc->mmc_rx_udp_gd_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_udp_gd_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_gd_octets_h, MMC_RXUDP_GD_OCTETS_H); mmc->mmc_rx_ipv6_gd_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd_octets, MMC_RXIPV6_GD_OCTETS_L); mmc->mmc_rx_ipv6_gd_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_gd_octets_h, MMC_RXIPV6_GD_OCTETS_H); mmc->mmc_rx_ipv6_hderr_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr_octets, MMC_RXIPV6_HDRERR_OCTETS_L); mmc->mmc_rx_ipv6_hderr_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_hderr_octets_h, MMC_RXIPV6_HDRERR_OCTETS_H); mmc->mmc_rx_ipv6_nopay_octets = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay_octets, MMC_RXIPV6_NOPAY_OCTETS_L); mmc->mmc_rx_ipv6_nopay_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_ipv6_nopay_octets_h, MMC_RXIPV6_NOPAY_OCTETS_H); mmc->mmc_rx_udp_err_octets = - update_mmc_val(osi_core, mmc->mmc_rx_udp_err_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_err_octets, MMC_RXUDP_ERR_OCTETS_L); mmc->mmc_rx_udp_err_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_udp_err_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_udp_err_octets_h, MMC_RXUDP_ERR_OCTETS_H); mmc->mmc_rx_tcp_gd_octets = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd_octets, MMC_RXTCP_GD_OCTETS_L); mmc->mmc_rx_tcp_gd_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_gd_octets_h, MMC_RXTCP_GD_OCTETS_H); mmc->mmc_rx_tcp_err_octets = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_err_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_err_octets, MMC_RXTCP_ERR_OCTETS_L); mmc->mmc_rx_tcp_err_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_tcp_err_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_tcp_err_octets_h, MMC_RXTCP_ERR_OCTETS_H); mmc->mmc_rx_icmp_gd_octets = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd_octets, MMC_RXICMP_GD_OCTETS_L); mmc->mmc_rx_icmp_gd_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_gd_octets_h, MMC_RXICMP_GD_OCTETS_H); mmc->mmc_rx_icmp_err_octets = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_err_octets, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_err_octets, MMC_RXICMP_ERR_OCTETS_L); mmc->mmc_rx_icmp_err_octets_h = - update_mmc_val(osi_core, mmc->mmc_rx_icmp_err_octets_h, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_icmp_err_octets_h, MMC_RXICMP_ERR_OCTETS_H); mmc->mmc_tx_fpe_frag_cnt = - update_mmc_val(osi_core, mmc->mmc_tx_fpe_frag_cnt, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_fpe_frag_cnt, MMC_TX_FPE_FRAG_COUNTER); mmc->mmc_tx_fpe_hold_req_cnt = - update_mmc_val(osi_core, mmc->mmc_tx_fpe_hold_req_cnt, + mgbe_update_mmc_val(osi_core, mmc->mmc_tx_fpe_hold_req_cnt, MMC_TX_HOLD_REQ_COUNTER); mmc->mmc_rx_packet_reass_err_cnt = - update_mmc_val(osi_core, mmc->mmc_rx_packet_reass_err_cnt, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_packet_reass_err_cnt, MMC_RX_PKT_ASSEMBLY_ERR_CNTR); mmc->mmc_rx_packet_smd_err_cnt = - update_mmc_val(osi_core, mmc->mmc_rx_packet_smd_err_cnt, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_packet_smd_err_cnt, MMC_RX_PKT_SMD_ERR_CNTR); mmc->mmc_rx_packet_asm_ok_cnt = - update_mmc_val(osi_core, mmc->mmc_rx_packet_asm_ok_cnt, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_packet_asm_ok_cnt, MMC_RX_PKT_ASSEMBLY_OK_CNTR); mmc->mmc_rx_fpe_fragment_cnt = - update_mmc_val(osi_core, mmc->mmc_rx_fpe_fragment_cnt, + mgbe_update_mmc_val(osi_core, mmc->mmc_rx_fpe_fragment_cnt, MMC_RX_FPE_FRAG_CNTR); } diff --git a/osi/core/osi_core.c b/osi/core/osi_core.c index 4930cc8..9759da4 100644 --- a/osi/core/osi_core.c +++ b/osi/core/osi_core.c @@ -44,17 +44,6 @@ nveu32_t hsi_err_code[][3] = { }; #endif -/** - * @brief g_core - Static core local data array - */ -static struct core_local g_core[MAX_CORE_INSTANCES]; - -/** - * @brief if_ops - Static core interface operations for virtual/non-virtual - * case - */ -static struct if_core_ops if_ops[MAX_INTERFACE_OPS]; - /** * @brief Function to validate function pointers. * @@ -126,6 +115,7 @@ static inline nve32_t validate_if_args(struct osi_core_priv_data *const osi_core struct osi_core_priv_data *osi_get_core(void) { nveu32_t i; + static struct core_local g_core[MAX_CORE_INSTANCES]; for (i = 0U; i < MAX_CORE_INSTANCES; i++) { if (g_core[i].if_init_done == OSI_ENABLE) { @@ -173,6 +163,7 @@ struct osi_core_priv_data *get_role_pointer(nveu32_t role) nve32_t osi_init_core_ops(struct osi_core_priv_data *const osi_core) { struct core_local *l_core = (struct core_local *)(void *)osi_core; + static struct if_core_ops if_ops[MAX_INTERFACE_OPS]; nve32_t ret = -1; if (osi_core == OSI_NULL) { @@ -210,10 +201,12 @@ nve32_t osi_init_core_ops(struct osi_core_priv_data *const osi_core) } l_core->ts_lock = OSI_DISABLE; l_core->ether_m2m_role = osi_core->m2m_role; +#if DRIFT_CAL l_core->serv.count = SERVO_STATS_0; l_core->serv.drift = 0; l_core->serv.last_ppb = 0; osi_lock_init(&l_core->serv.m2m_lock); +#endif #ifdef MACSEC_SUPPORT osi_lock_init(&osi_core->macsec_fpe_lock); #endif /* MACSEC_SUPPORT */ diff --git a/osi/core/osi_hal.c b/osi/core/osi_hal.c index d69f0f2..e9e890b 100644 --- a/osi/core/osi_hal.c +++ b/osi/core/osi_hal.c @@ -34,7 +34,6 @@ /** * @brief g_ops - Static core operations array. */ -static struct core_ops g_ops[MAX_MAC_IP_TYPES]; /** * @brief Function to validate input arguments of API. @@ -136,11 +135,12 @@ nve32_t osi_hal_read_phy_reg(struct osi_core_priv_data *const osi_core, static nve32_t osi_hal_init_core_ops(struct osi_core_priv_data *const osi_core) { struct core_local *l_core = (struct core_local *)(void *)osi_core; - typedef void (*init_ops_arr)(struct core_ops *local_ops); + typedef void (*init_core_ops_arr)(struct core_ops *local_ops); + static struct core_ops g_ops[MAX_MAC_IP_TYPES]; #ifndef OSI_STRIPPED_LIB typedef void *(*safety_init)(void); #endif - init_ops_arr i_ops[MAX_MAC_IP_TYPES][MAX_MAC_IP_TYPES] = { + init_core_ops_arr i_ops[MAX_MAC_IP_TYPES][MAX_MAC_IP_TYPES] = { { eqos_init_core_ops, OSI_NULL }, { mgbe_init_core_ops, OSI_NULL } }; @@ -836,7 +836,8 @@ static nve32_t osi_get_mac_version(struct osi_core_priv_data *const osi_core, nv *mac_ver = osi_readla(osi_core, ((nveu8_t *)osi_core->base + (nve32_t)MAC_VERSION)) & MAC_VERSION_SNVER_MASK; - if (validate_mac_ver_update_chans(*mac_ver, &l_core->max_chans, &l_core->l_mac_ver) == 0) { + if (validate_mac_ver_update_chans(*mac_ver, &l_core->num_max_chans, + &l_core->l_mac_ver) == 0) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid MAC version\n", (nveu64_t)*mac_ver) return -1; @@ -1710,7 +1711,7 @@ static void apply_dynamic_cfg(struct osi_core_priv_data *osi_core) { struct core_local *l_core = (struct core_local *)(void *)osi_core; typedef void (*cfg_fn)(struct core_local *local_core); - const cfg_fn fn[] = { + const cfg_fn fn[10] = { [DYNAMIC_CFG_L3_L4_IDX] = cfg_l3_l4_filter, [DYNAMIC_CFG_L2_IDX] = cfg_l2_filter, [DYNAMIC_CFG_RXCSUM_IDX] = cfg_rxcsum, diff --git a/osi/core/xpcs.c b/osi/core/xpcs.c index 66cc78f..2a3b652 100644 --- a/osi/core/xpcs.c +++ b/osi/core/xpcs.c @@ -600,8 +600,9 @@ nve32_t xpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis) return -1; } - if (xpcs_base == OSI_NULL) + if (xpcs_base == OSI_NULL) { return -1; + } if (en_dis == OSI_DISABLE) { val = xpcs_read(xpcs_base, XPCS_VR_XS_PCS_EEE_MCTRL0);