mirror of
git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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nvethernetrm: address review comments
- Convert primitive data type to nv_ type's - Replace debug pr_ prints with OSI_CORE_ print macro's - Add all macsec register macro's with prefix MACSEC_ - Update all osi function header as per 5.2 coding guidelines(PLC) - Remove printk.h header file and use OSI_CORE_ERR macro's in all prints - Implement clean up LUT's in add_upd_sc() and del_upd_sc() Bug 3264523 Change-Id: Ie41097c85fbcb90ce0c4cac470fe0f068ed22247 Signed-off-by: Mahesh Patil <maheshp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2548476 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com> Reviewed-by: Bhadram Varka <vbhadram@nvidia.com> Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
This commit is contained in:
Mahesh Patil
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mobile promotions
mobile promotions
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d4e6ad6ec6
commit
330acf2e3d
@@ -587,43 +587,43 @@ struct osi_xtra_stat_counters {
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struct osi_macsec_mmc_counters {
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/** This counter provides the number of controller port macsec
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* untaged packets */
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unsigned long long rx_pkts_no_tag;
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nveul64_t rx_pkts_no_tag;
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/** This counter provides the number of controller port macsec
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* untaged packets validateFrame != strict */
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unsigned long long rx_pkts_untagged;
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nveul64_t rx_pkts_untagged;
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/** This counter provides the number of invalid tag or icv packets */
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unsigned long long rx_pkts_bad_tag;
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nveul64_t rx_pkts_bad_tag;
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/** This counter provides the number of no sc lookup hit or sc match
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* packets */
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unsigned long long rx_pkts_no_sa_err;
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nveul64_t rx_pkts_no_sa_err;
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/** This counter provides the number of no sc lookup hit or sc match
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* packets validateFrame != strict */
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unsigned long long rx_pkts_no_sa;
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nveul64_t rx_pkts_no_sa;
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/** This counter provides the number of late packets
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*received PN < lowest PN */
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unsigned long long rx_pkts_late[OSI_MACSEC_SC_INDEX_MAX];
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nveul64_t rx_pkts_late[OSI_MACSEC_SC_INDEX_MAX];
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/** This counter provides the number of overrun packets */
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unsigned long long rx_pkts_overrun;
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nveul64_t rx_pkts_overrun;
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/** This counter provides the number of octets after IVC passing */
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unsigned long long rx_octets_validated;
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nveul64_t rx_octets_validated;
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/** This counter provides the number not valid packets */
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unsigned long long rx_pkts_not_valid[OSI_MACSEC_SC_INDEX_MAX];
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nveul64_t rx_pkts_not_valid[OSI_MACSEC_SC_INDEX_MAX];
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/** This counter provides the number of invalid packets */
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unsigned long long in_pkts_invalid[OSI_MACSEC_SC_INDEX_MAX];
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nveul64_t in_pkts_invalid[OSI_MACSEC_SC_INDEX_MAX];
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/** This counter provides the number of in packet delayed */
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unsigned long long rx_pkts_delayed[OSI_MACSEC_SC_INDEX_MAX];
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nveul64_t rx_pkts_delayed[OSI_MACSEC_SC_INDEX_MAX];
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/** This counter provides the number of in packets un checked */
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unsigned long long rx_pkts_unchecked[OSI_MACSEC_SC_INDEX_MAX];
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nveul64_t rx_pkts_unchecked[OSI_MACSEC_SC_INDEX_MAX];
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/** This counter provides the number of in packets ok */
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unsigned long long rx_pkts_ok[OSI_MACSEC_SC_INDEX_MAX];
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nveul64_t rx_pkts_ok[OSI_MACSEC_SC_INDEX_MAX];
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/** This counter provides the number of out packets untaged */
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unsigned long long tx_pkts_untaged;
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nveul64_t tx_pkts_untaged;
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/** This counter provides the number of out too long */
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unsigned long long tx_pkts_too_long;
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nveul64_t tx_pkts_too_long;
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/** This counter provides the number of out packets protected */
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unsigned long long tx_pkts_protected[OSI_MACSEC_SC_INDEX_MAX];
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nveul64_t tx_pkts_protected[OSI_MACSEC_SC_INDEX_MAX];
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/** This counter provides the number of out octets protected */
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unsigned long long tx_octets_protected;
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nveul64_t tx_octets_protected;
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};
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#endif /* MACSEC_SUPPORT */
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#endif /* INCLUDED_MMC_H */
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@@ -986,7 +986,7 @@ struct osd_core_ops {
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nveu32_t len);
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#ifdef MACSEC_SUPPORT
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/** Program macsec key table through Trust Zone callback */
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int (*macsec_tz_kt_config)(void *priv, unsigned char cmd,
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nve32_t (*macsec_tz_kt_config)(void *priv, unsigned char cmd,
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void *const kt_config,
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void *const genl_info);
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#endif /* MACSEC_SUPPORT */
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@@ -998,43 +998,43 @@ struct osd_core_ops {
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*/
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struct osi_macsec_irq_stats {
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/** Tx debug buffer capture done */
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unsigned long tx_dbg_capture_done;
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nveu64_t tx_dbg_capture_done;
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/** Tx MTU check failed */
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unsigned long tx_mtu_check_fail;
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nveu64_t tx_mtu_check_fail;
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/** Tx MAC CRC err */
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unsigned long tx_mac_crc_error;
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nveu64_t tx_mac_crc_error;
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/** Tx SC AN not valid */
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unsigned long tx_sc_an_not_valid;
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nveu64_t tx_sc_an_not_valid;
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/** Tx AES GCM buffer overflow */
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unsigned long tx_aes_gcm_buf_ovf;
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nveu64_t tx_aes_gcm_buf_ovf;
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/** Tx LUT lookup miss */
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unsigned long tx_lkup_miss;
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nveu64_t tx_lkup_miss;
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/** Tx uninitialized key slot */
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unsigned long tx_uninit_key_slot;
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nveu64_t tx_uninit_key_slot;
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/** Tx PN threshold reached */
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unsigned long tx_pn_threshold;
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nveu64_t tx_pn_threshold;
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/** Tx PN exhausted */
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unsigned long tx_pn_exhausted;
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nveu64_t tx_pn_exhausted;
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/** Tx debug buffer capture done */
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unsigned long rx_dbg_capture_done;
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nveu64_t rx_dbg_capture_done;
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/** Rx ICV error threshold */
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unsigned long rx_icv_err_threshold;
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nveu64_t rx_icv_err_threshold;
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/** Rx replay error */
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unsigned long rx_replay_error;
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nveu64_t rx_replay_error;
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/** Rx MTU check failed */
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unsigned long rx_mtu_check_fail;
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nveu64_t rx_mtu_check_fail;
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/** Rx MAC CRC err */
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unsigned long rx_mac_crc_error;
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nveu64_t rx_mac_crc_error;
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/** Rx AES GCM buffer overflow */
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unsigned long rx_aes_gcm_buf_ovf;
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nveu64_t rx_aes_gcm_buf_ovf;
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/** Rx LUT lookup miss */
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unsigned long rx_lkup_miss;
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nveu64_t rx_lkup_miss;
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/** Rx uninitialized key slot */
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unsigned long rx_uninit_key_slot;
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nveu64_t rx_uninit_key_slot;
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/** Rx PN exhausted */
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unsigned long rx_pn_exhausted;
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nveu64_t rx_pn_exhausted;
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/** Secure reg violation */
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unsigned long secure_reg_viol;
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nveu64_t secure_reg_viol;
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};
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#endif /* MACSEC_SUPPORT */
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@@ -1144,7 +1144,7 @@ struct osi_core_priv_data {
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/** Memory mapped base address of MACsec TZ page */
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void *tz_base;
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/** Address of MACsec HW operations structure */
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struct macsec_core_ops *macsec_ops;
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struct osi_macsec_core_ops *macsec_ops;
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/** Instance of macsec interrupt stats structure */
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struct osi_macsec_irq_stats macsec_irq_stats;
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/** Instance of macsec HW controller Tx/Rx LUT status */
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File diff suppressed because it is too large
Load Diff
@@ -35,6 +35,10 @@
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typedef unsigned int my_uint32_t;
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/** intermediate type for int */
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typedef int my_int32_t;
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/** intermediate type for unsigned short */
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typedef unsigned short my_uint16_t;
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/** intermediate type for short */
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typedef short my_int16_t;
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/** intermediate type for char */
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typedef char my_int8_t;
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/** intermediate type for unsigned char */
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@@ -49,6 +53,10 @@ typedef unsigned long my_uint64_t;
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typedef my_uint32_t nveu32_t;
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/** typedef equivalent to int */
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typedef my_int32_t nve32_t;
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/** typedef equivalent to unsigned short */
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typedef my_uint16_t nveu16_t;
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/** typedef equivalent to short */
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typedef my_int16_t nve16_t;
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/** typedef equivalent to char */
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typedef my_int8_t nve8_t;
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/** typedef equivalent to unsigned char */
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@@ -516,7 +516,7 @@ static int ivc_macsec_init(struct osi_core_priv_data *const osi_core)
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*/
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void ivc_init_macsec_ops(void *macsecops)
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{
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struct macsec_core_ops *ops = (struct macsec_core_ops *) macsecops;
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struct osi_macsec_core_ops *ops = (struct osi_macsec_core_ops *) macsecops;
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ops->init = ivc_macsec_init;
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ops->deinit = ivc_macsec_deinit;
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2084
osi/core/macsec.c
2084
osi/core/macsec.c
File diff suppressed because it is too large
Load Diff
@@ -29,115 +29,114 @@
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* @brief MACsec controller register offsets
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* @{
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*/
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#define GCM_KEYTABLE_CONFIG 0x0000
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#define GCM_KEYTABLE_DATA(x) (0x0004 + (x * 4))
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#define RX_ICV_ERR_CNTRL 0x4000
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#define INTERRUPT_COMMON_SR 0x4004
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#define TX_IMR 0x4008
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#define TX_ISR 0x400C
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#define RX_IMR 0x4048
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#define RX_ISR 0x404C
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#define INTERRUPT_MASK1_0 0x40A0
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#define TX_SC_PN_THRESHOLD_STATUS0_0 0x4018
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#define TX_SC_PN_THRESHOLD_STATUS1_0 0x401C
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#define TX_SC_PN_EXHAUSTED_STATUS0_0 0x4024
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#define TX_SC_PN_EXHAUSTED_STATUS1_0 0x4028
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#define TX_SC_ERROR_INTERRUPT_STATUS_0 0x402C
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#define RX_SC_PN_EXHAUSTED_STATUS0_0 0x405C
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#define RX_SC_PN_EXHAUSTED_STATUS1_0 0x4060
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#define RX_SC_REPLAY_ERROR_STATUS0_0 0x4090
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#define RX_SC_REPLAY_ERROR_STATUS1_0 0x4094
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#define STATS_CONFIG 0x9000
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#define STATS_CONTROL_0 0x900C
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#define TX_PKTS_UNTG_LO_0 0x9010
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#define TX_PKTS_UNTG_HI_0 0x9014
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#define TX_OCTETS_PRTCTD_LO_0 0x9018
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#define TX_OCTETS_PRTCTD_HI_0 0x901C
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#define TX_PKTS_TOO_LONG_LO_0 0x9020
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#define TX_PKTS_TOO_LONG_HI_0 0x9024
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#define TX_PKTS_PROTECTED_SCx_LO_0(x) (0x9028 + (x * 8))
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#define TX_PKTS_PROTECTED_SCx_HI_0(x) (0x902C + (x * 8))
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#define RX_PKTS_NOTG_LO_0 0x90B0
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#define RX_PKTS_NOTG_HI_0 0x90B4
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#define RX_PKTS_UNTG_LO_0 0x90A8
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#define RX_PKTS_UNTG_HI_0 0x90AC
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#define RX_PKTS_BADTAG_LO_0 0x90B8
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#define RX_PKTS_BADTAG_HI_0 0x90BC
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#define RX_PKTS_NOSA_LO_0 0x90C0
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#define RX_PKTS_NOSA_HI_0 0x90C4
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#define RX_PKTS_NOSAERROR_LO_0 0x90C8
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#define RX_PKTS_NOSAERROR_HI_0 0x90CC
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#define RX_PKTS_OVRRUN_LO_0 0x90D0
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#define RX_PKTS_OVRRUN_HI_0 0x90D4
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#define RX_OCTETS_VLDTD_LO_0 0x90D8
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#define RX_OCTETS_VLDTD_HI_0 0x90DC
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#define RX_PKTS_LATE_SCx_LO_0(x) (0x90E0 + (x * 8))
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#define RX_PKTS_LATE_SCx_HI_0(x) (0x90E4 + (x * 8))
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#define RX_PKTS_NOTVALID_SCx_LO_0(x) (0x9160 + (x * 8))
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#define RX_PKTS_NOTVALID_SCx_HI_0(x) (0x9164 + (x * 8))
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#define RX_PKTS_OK_SCx_LO_0(x) (0x91E0 + (x * 8))
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#define RX_PKTS_OK_SCx_HI_0(x) (0x91E4 + (x * 8))
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#define MASCEC_GCM_KEYTABLE_CONFIG 0x0000
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#define MACSEC_GCM_KEYTABLE_DATA(x) (0x0004 + (x * 4))
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#define MACSEC_RX_ICV_ERR_CNTRL 0x4000
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#define MACSEC_INTERRUPT_COMMON_SR 0x4004
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#define MACSEC_TX_IMR 0x4008
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#define MACSEC_TX_ISR 0x400C
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#define MACSEC_RX_IMR 0x4048
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#define MACSEC_RX_ISR 0x404C
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#define MACSEC_INTERRUPT_MASK1_0 0x40A0
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#define MACSEC_TX_SC_PN_THRESHOLD_STATUS0_0 0x4018
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#define MACSEC_TX_SC_PN_THRESHOLD_STATUS1_0 0x401C
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#define MACSEC_TX_SC_PN_EXHAUSTED_STATUS0_0 0x4024
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#define MACSEC_TX_SC_PN_EXHAUSTED_STATUS1_0 0x4028
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#define MACSEC_TX_SC_ERROR_INTERRUPT_STATUS_0 0x402C
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#define MACSEC_RX_SC_PN_EXHAUSTED_STATUS0_0 0x405C
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#define MACSEC_RX_SC_PN_EXHAUSTED_STATUS1_0 0x4060
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#define MACSEC_RX_SC_REPLAY_ERROR_STATUS0_0 0x4090
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#define MACSEC_RX_SC_REPLAY_ERROR_STATUS1_0 0x4094
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#define MACSEC_STATS_CONFIG 0x9000
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#define MACSEC_STATS_CONTROL_0 0x900C
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#define MACSEC_TX_PKTS_UNTG_LO_0 0x9010
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#define MACSEC_TX_PKTS_UNTG_HI_0 0x9014
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#define MACSEC_TX_OCTETS_PRTCTD_LO_0 0x9018
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#define MACSEC_TX_OCTETS_PRTCTD_HI_0 0x901C
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#define MACSEC_TX_PKTS_TOO_LONG_LO_0 0x9020
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#define MACSEC_TX_PKTS_TOO_LONG_HI_0 0x9024
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#define MACSEC_TX_PKTS_PROTECTED_SCx_LO_0(x) (0x9028 + (x * 8))
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#define MACSEC_TX_PKTS_PROTECTED_SCx_HI_0(x) (0x902C + (x * 8))
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#define MACSEC_RX_PKTS_NOTG_LO_0 0x90B0
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#define MACSEC_RX_PKTS_NOTG_HI_0 0x90B4
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#define MACSEC_RX_PKTS_UNTG_LO_0 0x90A8
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#define MACSEC_RX_PKTS_UNTG_HI_0 0x90AC
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#define MACSEC_RX_PKTS_BADTAG_LO_0 0x90B8
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#define MACSEC_RX_PKTS_BADTAG_HI_0 0x90BC
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#define MACSEC_RX_PKTS_NOSA_LO_0 0x90C0
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#define MACSEC_RX_PKTS_NOSA_HI_0 0x90C4
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#define MACSEC_RX_PKTS_NOSAERROR_LO_0 0x90C8
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#define MACSEC_RX_PKTS_NOSAERROR_HI_0 0x90CC
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#define MACSEC_RX_PKTS_OVRRUN_LO_0 0x90D0
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#define MACSEC_RX_PKTS_OVRRUN_HI_0 0x90D4
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#define MACSEC_RX_OCTETS_VLDTD_LO_0 0x90D8
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#define MACSEC_RX_OCTETS_VLDTD_HI_0 0x90DC
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#define MACSEC_RX_PKTS_LATE_SCx_LO_0(x) (0x90E0 + (x * 8))
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#define MACSEC_RX_PKTS_LATE_SCx_HI_0(x) (0x90E4 + (x * 8))
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#define MACSEC_RX_PKTS_NOTVALID_SCx_LO_0(x) (0x9160 + (x * 8))
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#define MACSEC_RX_PKTS_NOTVALID_SCx_HI_0(x) (0x9164 + (x * 8))
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#define MACSEC_RX_PKTS_OK_SCx_LO_0(x) (0x91E0 + (x * 8))
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#define MACSEC_RX_PKTS_OK_SCx_HI_0(x) (0x91E4 + (x * 8))
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#define TX_INPKTS_CRCIN_NOTVALID_LO_0 0x9260
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#define TX_INPKTS_CRCIN_NOTVALID_HI_0 0x9264
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#define RX_INPKTS_CRCIN_NOTVALID_LO_0 0x9268
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#define RX_INPKTS_CRCIN_NOTVALID_HI_0 0x926C
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#define MACSEC_TX_INPKTS_CRCIN_NOTVALID_LO_0 0x9260
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#define MACSEC_TX_INPKTS_CRCIN_NOTVALID_HI_0 0x9264
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#define MACSEC_RX_INPKTS_CRCIN_NOTVALID_LO_0 0x9268
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#define MACSEC_RX_INPKTS_CRCIN_NOTVALID_HI_0 0x926C
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#define MACSEC_CONTROL0 0xD000
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#define MACSEC_LUT_CONFIG 0xD004
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#define MACSEC_LUT_DATA(x) (0xD008 + (x * 4))
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#define TX_BYP_LUT_VALID 0xD024
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#define TX_SCI_LUT_VALID 0xD028
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#define RX_BYP_LUT_VALID 0xD02C
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#define RX_SCI_LUT_VALID 0xD030
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#define MACSEC_TX_BYP_LUT_VALID 0xD024
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#define MACSEC_TX_SCI_LUT_VALID 0xD028
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#define MACSEC_RX_BYP_LUT_VALID 0xD02C
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#define MACSEC_RX_SCI_LUT_VALID 0xD030
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#define COMMON_IMR 0xD054
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#define COMMON_ISR 0xD058
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#define TX_SC_KEY_INVALID_STS0_0 0xD064
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#define TX_SC_KEY_INVALID_STS1_0 0xD068
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#define RX_SC_KEY_INVALID_STS0_0 0xD080
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#define RX_SC_KEY_INVALID_STS1_0 0xD084
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#define MACSEC_COMMON_IMR 0xD054
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#define MACSEC_COMMON_ISR 0xD058
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#define MACSEC_TX_SC_KEY_INVALID_STS0_0 0xD064
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#define MACSEC_TX_SC_KEY_INVALID_STS1_0 0xD068
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#define MACSEC_RX_SC_KEY_INVALID_STS0_0 0xD080
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#define MACSEC_RX_SC_KEY_INVALID_STS1_0 0xD084
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#define TX_DEBUG_CONTROL_0 0xD098
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#define TX_DEBUG_TRIGGER_EN_0 0xD09C
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#define TX_DEBUG_STATUS_0 0xD0C4
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#define DEBUG_BUF_CONFIG_0 0xD0C8
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#define DEBUG_BUF_DATA_0(x) (0xD0CC + (x * 4))
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#define RX_DEBUG_CONTROL_0 0xD0DC
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#define RX_DEBUG_TRIGGER_EN_0 0xD0E0
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#define RX_DEBUG_STATUS_0 0xD0F8
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#define MACSEC_TX_DEBUG_CONTROL_0 0xD098
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#define MACSEC_TX_DEBUG_TRIGGER_EN_0 0xD09C
|
||||
#define MACSEC_TX_DEBUG_STATUS_0 0xD0C4
|
||||
#define MACSEC_DEBUG_BUF_CONFIG_0 0xD0C8
|
||||
#define MACSEC_DEBUG_BUF_DATA_0(x) (0xD0CC + (x * 4))
|
||||
#define MACSEC_RX_DEBUG_CONTROL_0 0xD0DC
|
||||
#define MACSEC_RX_DEBUG_TRIGGER_EN_0 0xD0E0
|
||||
#define MACSEC_RX_DEBUG_STATUS_0 0xD0F8
|
||||
|
||||
#define MACSEC_CONTROL1 0xE000
|
||||
#define GCM_AES_CONTROL_0 0xE004
|
||||
#define TX_MTU_LEN 0xE008
|
||||
#define TX_SOT_DELAY 0xE010
|
||||
#define RX_MTU_LEN 0xE014
|
||||
#define RX_SOT_DELAY 0xE01C
|
||||
#define MACSEC_GCM_AES_CONTROL_0 0xE004
|
||||
#define MACSEC_TX_MTU_LEN 0xE008
|
||||
#define MACSEC_TX_SOT_DELAY 0xE010
|
||||
#define MACSEC_RX_MTU_LEN 0xE014
|
||||
#define MACSEC_RX_SOT_DELAY 0xE01C
|
||||
#define MACSEC_TX_DVLAN_CONTROL_0 0xE00C
|
||||
#define MACSEC_RX_DVLAN_CONTROL_0 0xE018
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup GCM_KEYTABLE_CONFIG register
|
||||
* @addtogroup MACSEC_GCM_KEYTABLE_CONFIG register
|
||||
*
|
||||
* @brief Bit definitions of GCM_KEYTABLE_CONFIG register
|
||||
* @brief Bit definitions of MACSEC_GCM_KEYTABLE_CONFIG register
|
||||
* @{
|
||||
*/
|
||||
#define KT_CONFIG_UPDATE OSI_BIT(31)
|
||||
#define KT_CONFIG_CTLR_SEL OSI_BIT(25)
|
||||
#define KT_CONFIG_RW OSI_BIT(24)
|
||||
#define KT_CONFIG_INDEX_MASK (OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
|
||||
#define MACSEC_KT_CONFIG_UPDATE OSI_BIT(31)
|
||||
#define MACSEC_KT_CONFIG_CTLR_SEL OSI_BIT(25)
|
||||
#define MACSEC_KT_CONFIG_RW OSI_BIT(24)
|
||||
#define MACSEC_KT_CONFIG_INDEX_MASK (OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
|
||||
OSI_BIT(1) | OSI_BIT(0))
|
||||
#define KT_ENTRY_VALID OSI_BIT(0)
|
||||
#define MACSEC_KT_ENTRY_VALID OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup GCM_KEYTABLE_DATA registers
|
||||
* @addtogroup MACSEC_GCM_KEYTABLE_DATA registers
|
||||
*
|
||||
* @brief Bit definitions of GCM_KEYTABLE_DATA register & helpful macros
|
||||
* @brief Bit definitions of MACSEC_GCM_KEYTABLE_DATA register & helpful macros
|
||||
* @{
|
||||
*/
|
||||
#define KT_ENTRY_VALID OSI_BIT(0)
|
||||
#define MACSEC_KT_DATA_REG_CNT 13
|
||||
#define MACSEC_KT_DATA_REG_SAK_CNT 8
|
||||
#define MACSEC_KT_DATA_REG_H_CNT 4
|
||||
@@ -149,13 +148,13 @@
|
||||
* @brief Bit definitions of MACSEC_LUT_CONFIG register
|
||||
* @{
|
||||
*/
|
||||
#define LUT_CONFIG_UPDATE OSI_BIT(31)
|
||||
#define LUT_CONFIG_CTLR_SEL OSI_BIT(25)
|
||||
#define LUT_CONFIG_RW OSI_BIT(24)
|
||||
#define LUT_CONFIG_LUT_SEL_MASK (OSI_BIT(18) | OSI_BIT(17) |\
|
||||
#define MACSEC_LUT_CONFIG_UPDATE OSI_BIT(31)
|
||||
#define MACSEC_LUT_CONFIG_CTLR_SEL OSI_BIT(25)
|
||||
#define MACSEC_LUT_CONFIG_RW OSI_BIT(24)
|
||||
#define MACSEC_LUT_CONFIG_LUT_SEL_MASK (OSI_BIT(18) | OSI_BIT(17) |\
|
||||
OSI_BIT(16))
|
||||
#define LUT_CONFIG_LUT_SEL_SHIFT 16
|
||||
#define LUT_CONFIG_INDEX_MASK (OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
|
||||
#define MACSEC_LUT_CONFIG_LUT_SEL_SHIFT 16
|
||||
#define MACSEC_LUT_CONFIG_INDEX_MASK (OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
|
||||
OSI_BIT(1) | OSI_BIT(0))
|
||||
/** @} */
|
||||
/**
|
||||
@@ -164,9 +163,9 @@
|
||||
* @brief Bit definitions of MACSEC_INTERRUPT_COMMON_STATUS register
|
||||
* @{
|
||||
*/
|
||||
#define COMMON_SR_SFTY_ERR OSI_BIT(2)
|
||||
#define COMMON_SR_RX OSI_BIT(1)
|
||||
#define COMMON_SR_TX OSI_BIT(0)
|
||||
#define MACSEC_COMMON_SR_SFTY_ERR OSI_BIT(2)
|
||||
#define MACSEC_COMMON_SR_RX OSI_BIT(1)
|
||||
#define MACSEC_COMMON_SR_TX OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
@@ -175,17 +174,17 @@
|
||||
* @brief Bit definitions of MACSEC_CONTROL0 register
|
||||
* @{
|
||||
*/
|
||||
#define TX_LKUP_MISS_NS_INTR OSI_BIT(24)
|
||||
#define RX_LKUP_MISS_NS_INTR OSI_BIT(23)
|
||||
#define VALIDATE_FRAMES_MASK (OSI_BIT(22) | OSI_BIT(21))
|
||||
#define VALIDATE_FRAMES_DIS 0x0
|
||||
#define VALIDATE_FRAMES_STRICT OSI_BIT(22)
|
||||
#define VALIDATE_FRAMES_CHECK OSI_BIT(21)
|
||||
#define RX_REPLAY_PROT_EN OSI_BIT(20)
|
||||
#define RX_LKUP_MISS_BYPASS OSI_BIT(19)
|
||||
#define RX_EN OSI_BIT(16)
|
||||
#define TX_LKUP_MISS_BYPASS OSI_BIT(3)
|
||||
#define TX_EN OSI_BIT(0)
|
||||
#define MACSEC_TX_LKUP_MISS_NS_INTR OSI_BIT(24)
|
||||
#define MACSEC_RX_LKUP_MISS_NS_INTR OSI_BIT(23)
|
||||
#define MACSEC_VALIDATE_FRAMES_MASK (OSI_BIT(22) | OSI_BIT(21))
|
||||
#define MACSEC_VALIDATE_FRAMES_DIS 0x0
|
||||
#define MACSEC_VALIDATE_FRAMES_STRICT OSI_BIT(22)
|
||||
#define MACSEC_VALIDATE_FRAMES_CHECK OSI_BIT(21)
|
||||
#define MACSEC_RX_REPLAY_PROT_EN OSI_BIT(20)
|
||||
#define MACSEC_RX_LKUP_MISS_BYPASS OSI_BIT(19)
|
||||
#define MACSEC_RX_EN OSI_BIT(16)
|
||||
#define MACSEC_TX_LKUP_MISS_BYPASS OSI_BIT(3)
|
||||
#define MACSEC_TX_EN OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
@@ -194,255 +193,236 @@
|
||||
* @brief Bit definitions of MACSEC_CONTROL1 register
|
||||
* @{
|
||||
*/
|
||||
#define LOOPBACK_MODE_EN OSI_BIT(31)
|
||||
#define RX_MTU_CHECK_EN OSI_BIT(16)
|
||||
#define TX_LUT_PRIO_BYP OSI_BIT(2)
|
||||
#define TX_MTU_CHECK_EN OSI_BIT(0)
|
||||
#define MACSEC_LOOPBACK_MODE_EN OSI_BIT(31)
|
||||
#define MACSEC_RX_MTU_CHECK_EN OSI_BIT(16)
|
||||
#define MACSEC_TX_LUT_PRIO_BYP OSI_BIT(2)
|
||||
#define MACSEC_TX_MTU_CHECK_EN OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup GCM_AES_CONTROL_0 register
|
||||
* @addtogroup MACSEC_GCM_AES_CONTROL_0 register
|
||||
*
|
||||
* @brief Bit definitions of GCM_AES_CONTROL_0 register
|
||||
* @brief Bit definitions of MACSEC_GCM_AES_CONTROL_0 register
|
||||
* @{
|
||||
*/
|
||||
#define RX_AES_MODE_MASK (OSI_BIT(17) | OSI_BIT(16))
|
||||
#define RX_AES_MODE_AES128 0x0
|
||||
#define RX_AES_MODE_AES256 OSI_BIT(17)
|
||||
#define TX_AES_MODE_MASK (OSI_BIT(1) | OSI_BIT(0))
|
||||
#define TX_AES_MODE_AES128 0x0
|
||||
#define TX_AES_MODE_AES256 OSI_BIT(1)
|
||||
#define MACSEC_RX_AES_MODE_MASK (OSI_BIT(17) | OSI_BIT(16))
|
||||
#define MACSEC_RX_AES_MODE_AES128 0x0
|
||||
#define MACSEC_RX_AES_MODE_AES256 OSI_BIT(17)
|
||||
#define MACSEC_TX_AES_MODE_MASK (OSI_BIT(1) | OSI_BIT(0))
|
||||
#define MACSEC_TX_AES_MODE_AES128 0x0
|
||||
#define MACSEC_TX_AES_MODE_AES256 OSI_BIT(1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup COMMON_IMR register
|
||||
* @addtogroup MACSEC_COMMON_IMR register
|
||||
*
|
||||
* @brief Bit definitions of MACSEC_INTERRUPT_MASK register
|
||||
* @{
|
||||
*/
|
||||
#define SECURE_REG_VIOL_INT_EN OSI_BIT(31)
|
||||
#define RX_UNINIT_KEY_SLOT_INT_EN OSI_BIT(17)
|
||||
#define RX_LKUP_MISS_INT_EN OSI_BIT(16)
|
||||
#define TX_UNINIT_KEY_SLOT_INT_EN OSI_BIT(1)
|
||||
#define TX_LKUP_MISS_INT_EN OSI_BIT(0)
|
||||
#define MACSEC_SECURE_REG_VIOL_INT_EN OSI_BIT(31)
|
||||
#define MACSEC_RX_UNINIT_KEY_SLOT_INT_EN OSI_BIT(17)
|
||||
#define MACSEC_RX_LKUP_MISS_INT_EN OSI_BIT(16)
|
||||
#define MACSEC_TX_UNINIT_KEY_SLOT_INT_EN OSI_BIT(1)
|
||||
#define MACSEC_TX_LKUP_MISS_INT_EN OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup TX_IMR register
|
||||
* @addtogroup MACSEC_TX_IMR register
|
||||
*
|
||||
* @brief Bit definitions of TX_INTERRUPT_MASK register
|
||||
* @{
|
||||
*/
|
||||
#define TX_DBG_BUF_CAPTURE_DONE_INT_EN OSI_BIT(22)
|
||||
#define TX_MTU_CHECK_FAIL_INT_EN OSI_BIT(19)
|
||||
#define TX_AES_GCM_BUF_OVF_INT_EN OSI_BIT(18)
|
||||
#define TX_SC_AN_NOT_VALID_INT_EN OSI_BIT(17)
|
||||
#define TX_MAC_CRC_ERROR_INT_EN OSI_BIT(16)
|
||||
#define TX_PN_EXHAUSTED_INT_EN OSI_BIT(1)
|
||||
#define TX_PN_THRSHLD_RCHD_INT_EN OSI_BIT(0)
|
||||
#define MACSEC_TX_DBG_BUF_CAPTURE_DONE_INT_EN OSI_BIT(22)
|
||||
#define MACSEC_TX_MTU_CHECK_FAIL_INT_EN OSI_BIT(19)
|
||||
#define MACSEC_TX_AES_GCM_BUF_OVF_INT_EN OSI_BIT(18)
|
||||
#define MACSEC_TX_SC_AN_NOT_VALID_INT_EN OSI_BIT(17)
|
||||
#define MACSEC_TX_MAC_CRC_ERROR_INT_EN OSI_BIT(16)
|
||||
#define MACSEC_TX_PN_EXHAUSTED_INT_EN OSI_BIT(1)
|
||||
#define MACSEC_TX_PN_THRSHLD_RCHD_INT_EN OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup RX_IMR register
|
||||
* @addtogroup MACSEC_RX_IMR register
|
||||
*
|
||||
* @brief Bit definitions of RX_INTERRUPT_MASK register
|
||||
* @{
|
||||
*/
|
||||
#define RX_DBG_BUF_CAPTURE_DONE_INT_EN OSI_BIT(22)
|
||||
#define RX_ICV_ERROR_INT_EN OSI_BIT(21)
|
||||
#define MACSEC_RX_DBG_BUF_CAPTURE_DONE_INT_EN OSI_BIT(22)
|
||||
#define MACSEC_RX_ICV_ERROR_INT_EN OSI_BIT(21)
|
||||
#define RX_REPLAY_ERROR_INT_EN OSI_BIT(20)
|
||||
#define RX_MTU_CHECK_FAIL_INT_EN OSI_BIT(19)
|
||||
#define RX_AES_GCM_BUF_OVF_INT_EN OSI_BIT(18)
|
||||
#define RX_MAC_CRC_ERROR_INT_EN OSI_BIT(16)
|
||||
#define RX_PN_EXHAUSTED_INT_EN OSI_BIT(1)
|
||||
#define MACSEC_RX_MTU_CHECK_FAIL_INT_EN OSI_BIT(19)
|
||||
#define MACSEC_RX_AES_GCM_BUF_OVF_INT_EN OSI_BIT(18)
|
||||
#define MACSEC_RX_MAC_CRC_ERROR_INT_EN OSI_BIT(16)
|
||||
#define MACSEC_RX_PN_EXHAUSTED_INT_EN OSI_BIT(1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup INTERRUPT_MASK1_0 register
|
||||
* @addtogroup MACSEC_INTERRUPT_MASK1_0 register
|
||||
*
|
||||
* @brief Bit definitions of INTERRUPT_MASK1_0 register
|
||||
* @brief Bit definitions of MACSEC_INTERRUPT_MASK1_0 register
|
||||
* @{
|
||||
*/
|
||||
#define SFTY_ERR_UNCORR_INT_EN OSI_BIT(0)
|
||||
#define MACSEC_SFTY_ERR_UNCORR_INT_EN OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup COMMON_ISR register
|
||||
* @addtogroup MACSEC_COMMON_ISR register
|
||||
*
|
||||
* @brief Bit definitions of MACSEC_INTERRUPT_STATUS register
|
||||
* @{
|
||||
*/
|
||||
#define SECURE_REG_VIOL OSI_BIT(31)
|
||||
#define RX_UNINIT_KEY_SLOT OSI_BIT(17)
|
||||
#define RX_LKUP_MISS OSI_BIT(16)
|
||||
#define TX_UNINIT_KEY_SLOT OSI_BIT(1)
|
||||
#define TX_LKUP_MISS OSI_BIT(0)
|
||||
#define MACSEC_SECURE_REG_VIOL OSI_BIT(31)
|
||||
#define MACSEC_RX_UNINIT_KEY_SLOT OSI_BIT(17)
|
||||
#define MACSEC_RX_LKUP_MISS OSI_BIT(16)
|
||||
#define MACSEC_TX_UNINIT_KEY_SLOT OSI_BIT(1)
|
||||
#define MACSEC_TX_LKUP_MISS OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup TX_ISR register
|
||||
* @addtogroup MACSEC_TX_ISR register
|
||||
*
|
||||
* @brief Bit definitions of TX_INTERRUPT_STATUS register
|
||||
* @{
|
||||
*/
|
||||
#define TX_DBG_BUF_CAPTURE_DONE OSI_BIT(22)
|
||||
#define TX_MTU_CHECK_FAIL OSI_BIT(19)
|
||||
#define TX_AES_GCM_BUF_OVF OSI_BIT(18)
|
||||
#define TX_SC_AN_NOT_VALID OSI_BIT(17)
|
||||
#define TX_MAC_CRC_ERROR OSI_BIT(16)
|
||||
#define TX_PN_EXHAUSTED OSI_BIT(1)
|
||||
#define TX_PN_THRSHLD_RCHD OSI_BIT(0)
|
||||
#define MACSEC_TX_DBG_BUF_CAPTURE_DONE OSI_BIT(22)
|
||||
#define MACSEC_TX_MTU_CHECK_FAIL OSI_BIT(19)
|
||||
#define MACSEC_TX_AES_GCM_BUF_OVF OSI_BIT(18)
|
||||
#define MACSEC_TX_SC_AN_NOT_VALID OSI_BIT(17)
|
||||
#define MACSEC_TX_MAC_CRC_ERROR OSI_BIT(16)
|
||||
#define MACSEC_TX_PN_EXHAUSTED OSI_BIT(1)
|
||||
#define MACSEC_TX_PN_THRSHLD_RCHD OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup RX_ISR register
|
||||
* @addtogroup MACSEC_RX_ISR register
|
||||
*
|
||||
* @brief Bit definitions of RX_INTERRUPT_STATUS register
|
||||
* @{
|
||||
*/
|
||||
#define RX_DBG_BUF_CAPTURE_DONE OSI_BIT(22)
|
||||
#define RX_ICV_ERROR OSI_BIT(21)
|
||||
#define RX_REPLAY_ERROR OSI_BIT(20)
|
||||
#define RX_MTU_CHECK_FAIL OSI_BIT(19)
|
||||
#define RX_AES_GCM_BUF_OVF OSI_BIT(18)
|
||||
#define RX_MAC_CRC_ERROR OSI_BIT(16)
|
||||
#define RX_PN_EXHAUSTED OSI_BIT(1)
|
||||
#define MACSEC_RX_DBG_BUF_CAPTURE_DONE OSI_BIT(22)
|
||||
#define MACSEC_RX_ICV_ERROR OSI_BIT(21)
|
||||
#define MACSEC_RX_REPLAY_ERROR OSI_BIT(20)
|
||||
#define MACSEC_RX_MTU_CHECK_FAIL OSI_BIT(19)
|
||||
#define MACSEC_RX_AES_GCM_BUF_OVF OSI_BIT(18)
|
||||
#define MACSEC_RX_MAC_CRC_ERROR OSI_BIT(16)
|
||||
#define MACSEC_RX_PN_EXHAUSTED OSI_BIT(1)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup STATS_CONTROL_0 register
|
||||
* @addtogroup MACSEC_STATS_CONTROL_0 register
|
||||
*
|
||||
* @brief Bit definitions of STATS_CONTROL_0 register
|
||||
* @brief Bit definitions of MACSEC_STATS_CONTROL_0 register
|
||||
* @{
|
||||
*/
|
||||
#define STATS_CONTROL0_RD_CPY OSI_BIT(3)
|
||||
#define STATS_CONTROL0_TK_CPY OSI_BIT(2)
|
||||
#define STATS_CONTROL0_CNT_RL_OVR_CPY OSI_BIT(1)
|
||||
#define STATS_CONTROL0_CNT_CLR OSI_BIT(0)
|
||||
#define MACSEC_STATS_CONTROL0_RD_CPY OSI_BIT(3)
|
||||
#define MACSEC_STATS_CONTROL0_TK_CPY OSI_BIT(2)
|
||||
#define MACSEC_STATS_CONTROL0_CNT_RL_OVR_CPY OSI_BIT(1)
|
||||
#define MACSEC_STATS_CONTROL0_CNT_CLR OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup DEBUG_BUF_CONFIG_0 register
|
||||
* @addtogroup MACSEC_DEBUG_BUF_CONFIG_0 register
|
||||
*
|
||||
* @brief Bit definitions of DEBUG_BUF_CONFIG_0 register
|
||||
* @brief Bit definitions of MACSEC_DEBUG_BUF_CONFIG_0 register
|
||||
* @{
|
||||
*/
|
||||
#define DEBUG_BUF_CONFIG_0_UPDATE OSI_BIT(31)
|
||||
#define DEBUG_BUF_CONFIG_0_CTLR_SEL OSI_BIT(25)
|
||||
#define DEBUG_BUF_CONFIG_0_RW OSI_BIT(24)
|
||||
#define DEBUG_BUF_CONFIG_0_IDX_MASK (OSI_BIT(0) | OSI_BIT(1) | \
|
||||
#define MACSEC_DEBUG_BUF_CONFIG_0_UPDATE OSI_BIT(31)
|
||||
#define MACSEC_DEBUG_BUF_CONFIG_0_CTLR_SEL OSI_BIT(25)
|
||||
#define MACSEC_DEBUG_BUF_CONFIG_0_RW OSI_BIT(24)
|
||||
#define MACSEC_DEBUG_BUF_CONFIG_0_IDX_MASK (OSI_BIT(0) | OSI_BIT(1) | \
|
||||
OSI_BIT(2) | OSI_BIT(3))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup TX_DEBUG_TRIGGER_EN_0 register
|
||||
* @addtogroup MACSEC_TX_DEBUG_TRIGGER_EN_0 register
|
||||
*
|
||||
* @brief Bit definitions of TX_DEBUG_TRIGGER_EN_0 register
|
||||
* @brief Bit definitions of MACSEC_TX_DEBUG_TRIGGER_EN_0 register
|
||||
* @{
|
||||
*/
|
||||
#define TX_DBG_CAPTURE OSI_BIT(10)
|
||||
#define TX_DBG_ICV_CORRUPT OSI_BIT(9)
|
||||
#define TX_DBG_CRC_CORRUPT OSI_BIT(8)
|
||||
#define TX_DBG_DATA_MATCH OSI_BIT(7)
|
||||
#define TX_DBG_LKUP_MATCH OSI_BIT(6)
|
||||
#define TX_DBG_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define TX_DBG_CRCIN_MATCH OSI_BIT(4)
|
||||
#define TX_DBG_ICV_MATCH OSI_BIT(3)
|
||||
#define TX_DBG_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define TX_DBG_AN_NOT_VALID OSI_BIT(1)
|
||||
#define TX_DBG_LKUP_MISS OSI_BIT(0)
|
||||
#define MACSEC_TX_DBG_CAPTURE OSI_BIT(10)
|
||||
#define MACSEC_TX_DBG_ICV_CORRUPT OSI_BIT(9)
|
||||
#define MACSEC_TX_DBG_CRC_CORRUPT OSI_BIT(8)
|
||||
#define MACSEC_TX_DBG_DATA_MATCH OSI_BIT(7)
|
||||
#define MACSEC_TX_DBG_LKUP_MATCH OSI_BIT(6)
|
||||
#define MACSEC_TX_DBG_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define MACSEC_TX_DBG_CRCIN_MATCH OSI_BIT(4)
|
||||
#define MACSEC_TX_DBG_ICV_MATCH OSI_BIT(3)
|
||||
#define MACSEC_TX_DBG_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define MACSEC_TX_DBG_AN_NOT_VALID OSI_BIT(1)
|
||||
#define MACSEC_TX_DBG_LKUP_MISS OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup TX_DEBUG_STATUS_0 register
|
||||
* @addtogroup MACSEC_TX_DEBUG_STATUS_0 register
|
||||
*
|
||||
* @brief Bit definitions of TX_DEBUG_STATUS_0 register
|
||||
* @brief Bit definitions of MACSEC_TX_DEBUG_STATUS_0 register
|
||||
* @{
|
||||
*/
|
||||
#define TX_DBG_STS_CAPTURE OSI_BIT(10)
|
||||
#define TX_DBG_STS_ICV_CORRUPT OSI_BIT(9)
|
||||
#define TX_DBG_STS_CRC_CORRUPT OSI_BIT(8)
|
||||
#define TX_DBG_STS_DATA_MATCH OSI_BIT(7)
|
||||
#define TX_DBG_STS_LKUP_MATCH OSI_BIT(6)
|
||||
#define TX_DBG_STS_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define TX_DBG_STS_CRCIN_MATCH OSI_BIT(4)
|
||||
#define TX_DBG_STS_ICV_MATCH OSI_BIT(3)
|
||||
#define TX_DBG_STS_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define TX_DBG_STS_AN_NOT_VALID OSI_BIT(1)
|
||||
#define TX_DBG_STS_LKUP_MISS OSI_BIT(0)
|
||||
#define MACSEC_TX_DBG_STS_CAPTURE OSI_BIT(10)
|
||||
#define MACSEC_TX_DBG_STS_ICV_CORRUPT OSI_BIT(9)
|
||||
#define MACSEC_TX_DBG_STS_CRC_CORRUPT OSI_BIT(8)
|
||||
#define MACSEC_TX_DBG_STS_DATA_MATCH OSI_BIT(7)
|
||||
#define MACSEC_TX_DBG_STS_LKUP_MATCH OSI_BIT(6)
|
||||
#define MACSEC_TX_DBG_STS_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define MACSEC_TX_DBG_STS_CRCIN_MATCH OSI_BIT(4)
|
||||
#define MACSEC_TX_DBG_STS_ICV_MATCH OSI_BIT(3)
|
||||
#define MACSEC_TX_DBG_STS_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define MACSEC_TX_DBG_STS_AN_NOT_VALID OSI_BIT(1)
|
||||
#define MACSEC_TX_DBG_STS_LKUP_MISS OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup RX_DEBUG_TRIGGER_EN_0 register
|
||||
* @addtogroup MACSEC_RX_DEBUG_TRIGGER_EN_0 register
|
||||
*
|
||||
* @brief Bit definitions of RX_DEBUG_TRIGGER_EN_0 register
|
||||
* @brief Bit definitions of MACSEC_RX_DEBUG_TRIGGER_EN_0 register
|
||||
* @{
|
||||
*/
|
||||
#define RX_DBG_CAPTURE OSI_BIT(10)
|
||||
#define RX_DBG_ICV_ERROR OSI_BIT(9)
|
||||
#define RX_DBG_CRC_CORRUPT OSI_BIT(8)
|
||||
#define RX_DBG_DATA_MATCH OSI_BIT(7)
|
||||
#define RX_DBG_BYP_LKUP_MATCH OSI_BIT(6)
|
||||
#define RX_DBG_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define RX_DBG_CRCIN_MATCH OSI_BIT(4)
|
||||
#define RX_DBG_REPLAY_ERR OSI_BIT(3)
|
||||
#define RX_DBG_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define RX_DBG_LKUP_MISS OSI_BIT(0)
|
||||
#define MACSEC_RX_DBG_CAPTURE OSI_BIT(10)
|
||||
#define MACSEC_RX_DBG_ICV_ERROR OSI_BIT(9)
|
||||
#define MACSEC_RX_DBG_CRC_CORRUPT OSI_BIT(8)
|
||||
#define MACSEC_RX_DBG_DATA_MATCH OSI_BIT(7)
|
||||
#define MACSEC_RX_DBG_BYP_LKUP_MATCH OSI_BIT(6)
|
||||
#define MACSEC_RX_DBG_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define MACSEC_RX_DBG_CRCIN_MATCH OSI_BIT(4)
|
||||
#define MACSEC_RX_DBG_REPLAY_ERR OSI_BIT(3)
|
||||
#define MACSEC_RX_DBG_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define MACSEC_RX_DBG_LKUP_MISS OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup RX_DEBUG_STATUS_0 register
|
||||
* @addtogroup MACSEC_RX_DEBUG_STATUS_0 register
|
||||
*
|
||||
* @brief Bit definitions of RX_DEBUG_STATUS_0 register
|
||||
* @brief Bit definitions of MACSEC_RX_DEBUG_STATUS_0 register
|
||||
* @{
|
||||
*/
|
||||
#define RX_DBG_STS_CAPTURE OSI_BIT(10)
|
||||
#define RX_DBG_STS_ICV_ERROR OSI_BIT(9)
|
||||
#define RX_DBG_STS_CRC_CORRUPT OSI_BIT(8)
|
||||
#define RX_DBG_STS_DATA_MATCH OSI_BIT(7)
|
||||
#define RX_DBG_STS_BYP_LKUP_MATCH OSI_BIT(6)
|
||||
#define RX_DBG_STS_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define RX_DBG_STS_CRCIN_MATCH OSI_BIT(4)
|
||||
#define RX_DBG_STS_REPLAY_ERR OSI_BIT(3)
|
||||
#define RX_DBG_STS_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define RX_DBG_STS_LKUP_MISS OSI_BIT(0)
|
||||
#define MACSEC_RX_DBG_STS_CAPTURE OSI_BIT(10)
|
||||
#define MACSEC_RX_DBG_STS_ICV_ERROR OSI_BIT(9)
|
||||
#define MACSEC_RX_DBG_STS_CRC_CORRUPT OSI_BIT(8)
|
||||
#define MACSEC_RX_DBG_STS_DATA_MATCH OSI_BIT(7)
|
||||
#define MACSEC_RX_DBG_STS_BYP_LKUP_MATCH OSI_BIT(6)
|
||||
#define MACSEC_RX_DBG_STS_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define MACSEC_RX_DBG_STS_CRCIN_MATCH OSI_BIT(4)
|
||||
#define MACSEC_RX_DBG_STS_REPLAY_ERR OSI_BIT(3)
|
||||
#define MACSEC_RX_DBG_STS_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define MACSEC_RX_DBG_STS_LKUP_MISS OSI_BIT(0)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup TX_DEBUG_STATUS_0 register
|
||||
* @addtogroup MACSEC_TX_DEBUG_CONTROL_0 register
|
||||
*
|
||||
* @brief Bit definitions of TX_DEBUG_STATUS_0 register
|
||||
* @brief Bit definitions of MACSEC_TX_DEBUG_CONTROL_0 register
|
||||
* @{
|
||||
*/
|
||||
#define TX_DBG_STS_CAPTURE OSI_BIT(10)
|
||||
#define TX_DBG_STS_ICV_CORRUPT OSI_BIT(9)
|
||||
#define TX_DBG_STS_CRC_CORRUPT OSI_BIT(8)
|
||||
#define TX_DBG_STS_DATA_MATCH OSI_BIT(7)
|
||||
#define TX_DBG_STS_LKUP_MATCH OSI_BIT(6)
|
||||
#define TX_DBG_STS_CRCOUT_MATCH OSI_BIT(5)
|
||||
#define TX_DBG_STS_CRCIN_MATCH OSI_BIT(4)
|
||||
#define TX_DBG_STS_ICV_MATCH OSI_BIT(3)
|
||||
#define TX_DBG_STS_KEY_NOT_VALID OSI_BIT(2)
|
||||
#define TX_DBG_STS_AN_NOT_VALID OSI_BIT(1)
|
||||
#define TX_DBG_STS_LKUP_MISS OSI_BIT(0)
|
||||
#define MACSEC_TX_DEBUG_CONTROL_0_START_CAP OSI_BIT(31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup TX_DEBUG_CONTROL_0 register
|
||||
* @addtogroup MACSEC_RX_DEBUG_CONTROL_0 register
|
||||
*
|
||||
* @brief Bit definitions of TX_DEBUG_CONTROL_0 register
|
||||
* @brief Bit definitions of MACSEC_RX_DEBUG_CONTROL_0 register
|
||||
* @{
|
||||
*/
|
||||
#define TX_DEBUG_CONTROL_0_START_CAP OSI_BIT(31)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @addtogroup RX_DEBUG_CONTROL_0 register
|
||||
*
|
||||
* @brief Bit definitions of RX_DEBUG_CONTROL_0 register
|
||||
* @{
|
||||
*/
|
||||
#define RX_DEBUG_CONTROL_0_START_CAP OSI_BIT(31)
|
||||
#define MACSEC_RX_DEBUG_CONTROL_0_START_CAP OSI_BIT(31)
|
||||
/** @} */
|
||||
|
||||
#define MTU_LENGTH_MASK 0xFFFF
|
||||
@@ -457,14 +437,14 @@
|
||||
* @brief Bit definitions of LUT_VALID registers
|
||||
* @{
|
||||
*/
|
||||
#define TX_BYP_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define TX_BYP_LUT_VALID_NONE 0x0
|
||||
#define TX_SCI_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define TX_SCI_LUT_VALID_NONE 0x0
|
||||
#define RX_BYP_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define RX_BYP_LUT_VALID_NONE 0x0
|
||||
#define RX_SCI_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define RX_SCI_LUT_VALID_NONE 0x0
|
||||
#define MACSEC_TX_BYP_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define MACSEC_TX_BYP_LUT_VALID_NONE 0x0
|
||||
#define MACSEC_TX_SCI_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define MACSEC_TX_SCI_LUT_VALID_NONE 0x0
|
||||
#define MACSEC_RX_BYP_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define MACSEC_RX_BYP_LUT_VALID_NONE 0x0
|
||||
#define MACSEC_RX_SCI_LUT_VALID_ENTRY(x) OSI_BIT(x)
|
||||
#define MACSEC_RX_SCI_LUT_VALID_NONE 0x0
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
@@ -476,60 +456,60 @@
|
||||
#define MACSEC_LUT_DATA_REG_CNT 7
|
||||
/* Bit Offsets for LUT DATA[x] registers for various lookup field masks */
|
||||
/* DA mask bits in LUT_DATA[1] register */
|
||||
#define LUT_DA_BYTE0_INACTIVE OSI_BIT(16)
|
||||
#define LUT_DA_BYTE1_INACTIVE OSI_BIT(17)
|
||||
#define LUT_DA_BYTE2_INACTIVE OSI_BIT(18)
|
||||
#define LUT_DA_BYTE3_INACTIVE OSI_BIT(19)
|
||||
#define LUT_DA_BYTE4_INACTIVE OSI_BIT(20)
|
||||
#define LUT_DA_BYTE5_INACTIVE OSI_BIT(21)
|
||||
#define MACSEC_LUT_DA_BYTE0_INACTIVE OSI_BIT(16)
|
||||
#define MACSEC_LUT_DA_BYTE1_INACTIVE OSI_BIT(17)
|
||||
#define MACSEC_LUT_DA_BYTE2_INACTIVE OSI_BIT(18)
|
||||
#define MACSEC_LUT_DA_BYTE3_INACTIVE OSI_BIT(19)
|
||||
#define MACSEC_LUT_DA_BYTE4_INACTIVE OSI_BIT(20)
|
||||
#define MACSEC_LUT_DA_BYTE5_INACTIVE OSI_BIT(21)
|
||||
/* SA mask bits in LUT_DATA[3] register */
|
||||
#define LUT_SA_BYTE0_INACTIVE OSI_BIT(6)
|
||||
#define LUT_SA_BYTE1_INACTIVE OSI_BIT(7)
|
||||
#define LUT_SA_BYTE2_INACTIVE OSI_BIT(8)
|
||||
#define LUT_SA_BYTE3_INACTIVE OSI_BIT(9)
|
||||
#define LUT_SA_BYTE4_INACTIVE OSI_BIT(10)
|
||||
#define LUT_SA_BYTE5_INACTIVE OSI_BIT(11)
|
||||
#define MACSEC_LUT_SA_BYTE0_INACTIVE OSI_BIT(6)
|
||||
#define MACSEC_LUT_SA_BYTE1_INACTIVE OSI_BIT(7)
|
||||
#define MACSEC_LUT_SA_BYTE2_INACTIVE OSI_BIT(8)
|
||||
#define MACSEC_LUT_SA_BYTE3_INACTIVE OSI_BIT(9)
|
||||
#define MACSEC_LUT_SA_BYTE4_INACTIVE OSI_BIT(10)
|
||||
#define MACSEC_LUT_SA_BYTE5_INACTIVE OSI_BIT(11)
|
||||
/* Ether type mask in LUT_DATA[3] register */
|
||||
#define LUT_ETHTYPE_INACTIVE OSI_BIT(28)
|
||||
#define MACSEC_LUT_ETHTYPE_INACTIVE OSI_BIT(28)
|
||||
/* VLAN PCP mask in LUT_DATA[4] register */
|
||||
#define LUT_VLAN_PCP_INACTIVE OSI_BIT(0)
|
||||
#define MACSEC_LUT_VLAN_PCP_INACTIVE OSI_BIT(0)
|
||||
/* VLAN ID mask in LUT_DATA[4] register */
|
||||
#define LUT_VLAN_ID_INACTIVE OSI_BIT(13)
|
||||
#define MACSEC_LUT_VLAN_ID_INACTIVE OSI_BIT(13)
|
||||
/* VLAN mask in LUT_DATA[4] register */
|
||||
#define LUT_VLAN_ACTIVE OSI_BIT(14)
|
||||
#define MACSEC_LUT_VLAN_ACTIVE OSI_BIT(14)
|
||||
/* Byte pattern masks in LUT_DATA[4] register */
|
||||
#define LUT_BYTE0_PATTERN_INACTIVE OSI_BIT(29)
|
||||
#define MACSEC_LUT_BYTE0_PATTERN_INACTIVE OSI_BIT(29)
|
||||
/* Byte pattern masks in LUT_DATA[5] register */
|
||||
#define LUT_BYTE1_PATTERN_INACTIVE OSI_BIT(12)
|
||||
#define LUT_BYTE2_PATTERN_INACTIVE OSI_BIT(27)
|
||||
#define MACSEC_LUT_BYTE1_PATTERN_INACTIVE OSI_BIT(12)
|
||||
#define MACSEC_LUT_BYTE2_PATTERN_INACTIVE OSI_BIT(27)
|
||||
/* Byte pattern masks in LUT_DATA[6] register */
|
||||
#define LUT_BYTE3_PATTERN_INACTIVE OSI_BIT(10)
|
||||
#define MACSEC_LUT_BYTE3_PATTERN_INACTIVE OSI_BIT(10)
|
||||
/* Preemptable packet in LUT_DATA[6] register */
|
||||
#define LUT_PREEMPT OSI_BIT(11)
|
||||
#define MACSEC_LUT_PREEMPT OSI_BIT(11)
|
||||
/* Preempt mask in LUT_DATA[6] register */
|
||||
#define LUT_PREEMPT_INACTIVE OSI_BIT(12)
|
||||
#define MACSEC_LUT_PREEMPT_INACTIVE OSI_BIT(12)
|
||||
/* Controlled port mask in LUT_DATA[6] register */
|
||||
#define LUT_CONTROLLED_PORT OSI_BIT(13)
|
||||
#define MACSEC_LUT_CONTROLLED_PORT OSI_BIT(13)
|
||||
/* DVLAN packet in LUT_DATA[6] register */
|
||||
#define BYP_LUT_DVLAN_PKT OSI_BIT(14)
|
||||
#define MACSEC_BYP_LUT_DVLAN_PKT OSI_BIT(14)
|
||||
/* DVLAN outer/inner tag select in LUT_DATA[6] register */
|
||||
#define BYP_LUT_DVLAN_OUTER_INNER_TAG_SEL OSI_BIT(15)
|
||||
/* AN valid bits for SCI LUT in LUT_DATA[6] register */
|
||||
#define LUT_AN0_VALID OSI_BIT(13)
|
||||
#define LUT_AN1_VALID OSI_BIT(14)
|
||||
#define LUT_AN2_VALID OSI_BIT(15)
|
||||
#define LUT_AN3_VALID OSI_BIT(16)
|
||||
#define MACSEC_LUT_AN0_VALID OSI_BIT(13)
|
||||
#define MACSEC_LUT_AN1_VALID OSI_BIT(14)
|
||||
#define MACSEC_LUT_AN2_VALID OSI_BIT(15)
|
||||
#define MACSEC_LUT_AN3_VALID OSI_BIT(16)
|
||||
/* DVLAN packet in LUT_DATA[6] register */
|
||||
#define TX_SCI_LUT_DVLAN_PKT OSI_BIT(21)
|
||||
#define MACSEC_TX_SCI_LUT_DVLAN_PKT OSI_BIT(21)
|
||||
/* DVLAN outer/inner tag select in LUT_DATA[6] register */
|
||||
#define TX_SCI_LUT_DVLAN_OUTER_INNER_TAG_SEL OSI_BIT(22)
|
||||
#define MACSEC_TX_SCI_LUT_DVLAN_OUTER_INNER_TAG_SEL OSI_BIT(22)
|
||||
/* SA State LUT entry valid in LUT_DATA[0] register */
|
||||
#define SA_STATE_LUT_ENTRY_VALID OSI_BIT(0)
|
||||
#define MACSEC_SA_STATE_LUT_ENTRY_VALID OSI_BIT(0)
|
||||
|
||||
/* Preemptable packet in LUT_DATA[2] register for Rx SCI */
|
||||
#define RX_SCI_LUT_PREEMPT OSI_BIT(8)
|
||||
#define MACSEC_RX_SCI_LUT_PREEMPT OSI_BIT(8)
|
||||
/* Preempt mask in LUT_DATA[2] register for Rx SCI */
|
||||
#define RX_SCI_LUT_PREEMPT_INACTIVE OSI_BIT(9)
|
||||
#define MACSEC_RX_SCI_LUT_PREEMPT_INACTIVE OSI_BIT(9)
|
||||
/** @} */
|
||||
|
||||
/* debug buffer data read/write length */
|
||||
|
||||
Reference in New Issue
Block a user