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osi: T26x: update delay for UPHY XPCS lane bringup

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- Update delay for 10G required when EQ is enabled.
 - Enable the EQ for 10G.
 - Update delay for eqos.

Bug 4790491

Change-Id: I63146b1a9ab03d5dbcdbc26e4d2a7ec48a15e497
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3270227
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
This commit is contained in:
Mahesh Patil
2024-12-17 18:50:34 -08:00
committed by mobile promotions
parent b5ed6001a7
commit 3a59f31c77
2 changed files with 52 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

59
osi/core/xpcs.c
View File

@@ -458,17 +458,23 @@ static nve32_t xpcs_uphy_lane_bring_up(struct osi_core_priv_data *osi_core,
T26X_XPCS_WRAP_UPHY_HW_INIT_CTRL
};
if ((osi_core->mac == OSI_MAC_HW_MGBE_T26X) || (osi_core->mac_ver == OSI_EQOS_MAC_5_40)) {
if (osi_core->mac == OSI_MAC_HW_MGBE_T26X) {
/* Delay added as per HW team suggestion which is
* of 100msec if equalizer is enabled for every
* iteration of a lane bring sequence. So 100 * 1000
* gives us a delay of 100msec for each retry of lane
* bringup */
retry = 1000U;
if (osi_core->uphy_gbe_mode == OSI_GBE_MODE_25G) {
/* Delay added as per HW team suggestion which is
* of 100msec if equalizer is enabled for every
* iteration of a lane bring sequence. So 100 * 1000
* gives us a delay of 100msec for each retry of lane
* bringup
*/
retry_delay = 100U;
}
retry_delay = 100U;
} else if (osi_core->mac_ver == OSI_EQOS_MAC_5_40) {
/* Delay added as per HW team suggestion which is
* of 10msec for eqos lane bring up. So 10 * 1000
* gives us a delay of 10msec for each retry of lane
* bringup */
retry = 1000U;
retry_delay = 10U;
} else {
/* do nothing */
}
val = osi_readla(osi_core,
@@ -884,6 +890,7 @@ fail:
nve32_t xpcs_init(struct osi_core_priv_data *osi_core)
{
void *xpcs_base = osi_core->xpcs_base;
nveu32_t value = 0;
nveu32_t ctrl = 0;
nve32_t ret = 0;
@@ -898,6 +905,38 @@ nve32_t xpcs_init(struct osi_core_priv_data *osi_core)
"xpcs_base_r_fec failed", 0ULL);
goto fail;
}
if ((osi_core->mac == OSI_MAC_HW_MGBE_T26X) &&
(osi_core->uphy_gbe_mode == OSI_GBE_MODE_10G)) {
/* Added below programming sequence from hw scripts */
value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_CONFIG_0);
value &= ~OSI_BIT(0);
osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_CONFIG_0);
osi_writela(osi_core, XPCS_10G_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_TX_CTRL_2);
osi_writela(osi_core, XPCS_10G_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_2);
osi_writela(osi_core, XPCS_10G_WRAP_UPHY_TX_CTRL_3_DATAREADY_DATAEN_DLY,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_TX_CTRL_3);
osi_writela(osi_core, XPCS_10G_WRAP_UPHY_RX_CTRL_3_CAL_DONE_DATA_EN_DLY,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_3);
osi_writela(osi_core,
XLGPCS_WRAP_UPHY_TO_CTRL2_EQ_DONE_TOV,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_T0_CTRL_2_0);
value = osi_readla(osi_core,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_5_0);
value |= XLGPCS_WRAP_UPHY_RX_CTRL5_RX_EQ_ENABLE;
osi_writela(osi_core, value,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_5_0);
}
if (xpcs_lane_bring_up(osi_core) < 0) {
ret = -1;

3
osi/core/xpcs.h
View File

@@ -131,6 +131,9 @@
#define XPCS_WRAP_UPHY_TX_CTRL_3_DATAREADY_DATAEN_DLY 0x82U
#define XPCS_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY 0xFBDU
#define XPCS_WRAP_UPHY_RX_CTRL_3_CAL_DONE_DATA_EN_DLY 0x78U
#define XPCS_10G_WRAP_UPHY_RX_CTRL_2_SLEEP_CAL_EN_DLY 0xCAAU
#define XPCS_10G_WRAP_UPHY_TX_CTRL_3_DATAREADY_DATAEN_DLY 0x50U
#define XPCS_10G_WRAP_UPHY_RX_CTRL_3_CAL_DONE_DATA_EN_DLY 0x32U
#define EQOS_XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8038
#define EQOS_XPCS_WRAP_UPHY_STATUS 0x8064