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osi: core: fix Doxygen warnings

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1) Fix Doxygen warnings
2) include debug.h code only when OSI_DEBUG
is defined

JIRA NET-570

Change-Id: I5d002b959925bec3898cc2faafe3f506b3c9bd22
Signed-off-by: Narayan Reddy<narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2847327
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Narayan Reddy
2023-01-23 01:03:54 +05:30
committed by mobile promotions
parent 2a82c10c8f
commit 3fff0cd9ba
17 changed files with 70 additions and 70 deletions
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5
include/osi_common.h
View File

@@ -153,9 +153,9 @@
/** @} */ /** @} */
/** /**
* @addtogroup Helper Helper MACROS * @addtogroup Generic helper MACROS
* *
* @brief EQOS generic helper MACROS. * @brief These are Generic helper macros used at various places.
* @{ * @{
*/ */
#define OSI_UCHAR_MAX (0xFFU) #define OSI_UCHAR_MAX (0xFFU)
@@ -253,6 +253,7 @@
#define OSI_DEBUG_TYPE_REG 2U #define OSI_DEBUG_TYPE_REG 2U
#define OSI_DEBUG_TYPE_STRUCTS 3U #define OSI_DEBUG_TYPE_STRUCTS 3U
#endif /* OSI_DEBUG */ #endif /* OSI_DEBUG */
/** @} */
/** /**
* @brief unused function attribute * @brief unused function attribute

6
include/osi_core.h
View File

@@ -155,7 +155,7 @@ typedef my_lint_64 nvel64_t;
/** @} */ /** @} */
/** /**
* @addtogroup Helper Helper MACROS * @addtogroup Helper MACROS
* *
* @brief EQOS generic helper MACROS. * @brief EQOS generic helper MACROS.
* @{ * @{
@@ -311,7 +311,7 @@ typedef my_lint_64 nvel64_t;
#define OSI_DELAY_1US 1U #define OSI_DELAY_1US 1U
/** /**
* @addtogroup PTP related information * @addtogroup PTP PTP related information
* *
* @brief PTP SSINC values * @brief PTP SSINC values
* @{ * @{
@@ -1396,8 +1396,6 @@ struct osi_core_priv_data {
* - Invokes EQOS MAC, MTL and common DMA register init code. * - Invokes EQOS MAC, MTL and common DMA register init code.
* *
* @param[in, out] osi_core: OSI core private data structure. * @param[in, out] osi_core: OSI core private data structure.
* @param[in] tx_fifo_size: OSI core private data structure.
* @param[in] rx_fifo_size: OSI core private data structure.
* *
* @pre * @pre
* - MAC should be out of reset. See osi_poll_for_mac_reset_complete() * - MAC should be out of reset. See osi_poll_for_mac_reset_complete()

9
include/osi_macsec.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -99,7 +99,7 @@
/** @} */ /** @} */
/** /**
* @addtogroup Generic table CONFIG register helpers macros * @addtogroup MACSEC-Generic table CONFIG register helpers macros
* *
* @brief Helper macros for generic table CONFIG register programming * @brief Helper macros for generic table CONFIG register programming
* @{ * @{
@@ -154,9 +154,9 @@
/** @} */ /** @} */
/** /**
* @addtogroup MACSEC Misc helper macro's * @addtogroup MACSEC related helper MACROs
* *
* @brief MACSEC Helper macro's * @brief MACSEC generic helper MACROs
* @{ * @{
*/ */
#define OSI_MACSEC_TX_EN OSI_BIT(0) #define OSI_MACSEC_TX_EN OSI_BIT(0)
@@ -644,6 +644,7 @@ nve32_t osi_macsec_en(struct osi_core_priv_data *const osi_core,
* *
* @param[in] osi_core: OSI core private data structure * @param[in] osi_core: OSI core private data structure
* @param[in] sc: Pointer to the sc that needs to be added/deleted/updated * @param[in] sc: Pointer to the sc that needs to be added/deleted/updated
* @param[in] enable: macsec enable/disable selection
* @param[in] ctlr: Controller selected * @param[in] ctlr: Controller selected
* @param[out] kt_idx: Pointer to the kt_index passed to OSD * @param[out] kt_idx: Pointer to the kt_index passed to OSD
* *

10
osi/common/common.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -26,7 +26,7 @@
#include <osi_common.h> #include <osi_common.h>
/** /**
* @addtogroup Generic helper macros * @addtogroup Generic helper MACROS
* *
* @brief These are Generic helper macros used at various places. * @brief These are Generic helper macros used at various places.
* @{ * @{
@@ -54,8 +54,9 @@
* a condition is met or a timeout occurs * a condition is met or a timeout occurs
* *
* @param[in] addr: Memory mapped address. * @param[in] addr: Memory mapped address.
* @param[in] fn: function to be used.
* @param[in] val: Variable to read the value. * @param[in] val: Variable to read the value.
* @param[in] cond: Break condition (usually involving @val). * @param[in] cond: Break condition.
* @param[in] delay_us: Maximum time to sleep between reads in us. * @param[in] delay_us: Maximum time to sleep between reads in us.
* @param[in] retry: Retry count. * @param[in] retry: Retry count.
@@ -240,7 +241,8 @@ static inline void osi_writela(OSI_UNUSED void *priv, nveu32_t val, void *addr)
* @brief validate_mac_ver_update_chans - Validates mac version and update chan * @brief validate_mac_ver_update_chans - Validates mac version and update chan
* *
* @param[in] mac_ver: MAC version read. * @param[in] mac_ver: MAC version read.
* @param[out] max_chans: Maximum channel number. * @param[out] num_max_chans: Maximum channel number.
* @param[out] l_mac_ver: local mac version.
* *
* @note MAC has to be out of reset. * @note MAC has to be out of reset.
* *

4
osi/common/mgbe_common.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -24,7 +24,7 @@
#define INCLUDED_MGBE_COMMON_H #define INCLUDED_MGBE_COMMON_H
/** /**
* @addtogroup MGBE-MAC MGBE MAC common HW feature registers * @addtogroup MGBE-MAC MAC register offsets
* *
* @{ * @{
*/ */

8
osi/core/core_common.c
View File

@@ -613,7 +613,7 @@ fail:
* @brief hw_est_read - indirect read the GCL to Software own list * @brief hw_est_read - indirect read the GCL to Software own list
* (SWOL) * (SWOL)
* *
* @param[in] base: MAC base IOVA address. * @param[in] osi_core: OSI core private data structure.
* @param[in] addr_val: Address offset for indirect write. * @param[in] addr_val: Address offset for indirect write.
* @param[in] data: Data to be written at offset. * @param[in] data: Data to be written at offset.
* @param[in] gcla: Gate Control List Address, 0 for ETS register. * @param[in] gcla: Gate Control List Address, 0 for ETS register.
@@ -677,6 +677,7 @@ err:
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] est: Configuration input argument. * @param[in] est: Configuration input argument.
* @param[in] btr: Base time register value.
* @param[in] mac: MAC index * @param[in] mac: MAC index
* *
* @note MAC should be init and started. see osi_start_mac() * @note MAC should be init and started. see osi_start_mac()
@@ -858,7 +859,7 @@ done:
* @brief hw_est_write - indirect write the GCL to Software own list * @brief hw_est_write - indirect write the GCL to Software own list
* (SWOL) * (SWOL)
* *
* @param[in] base: MAC base IOVA address. * @param[in] osi_core: OSI core private data structure.
* @param[in] addr_val: Address offset for indirect write. * @param[in] addr_val: Address offset for indirect write.
* @param[in] data: Data to be written at offset. * @param[in] data: Data to be written at offset.
* @param[in] gcla: Gate Control List Address, 0 for ETS register. * @param[in] gcla: Gate Control List Address, 0 for ETS register.
@@ -1732,7 +1733,8 @@ static void prepare_l4_port_register(const struct osi_l3_l4_filter *const l3_l4,
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] l3_l4: Pointer to l3 l4 filter structure (#osi_l3_l4_filter) * @param[in] l3_l4: Pointer to l3 l4 filter structure (#osi_l3_l4_filter)
* @param[out] l4_addr_reg: Pointer to L3 ADDR0 register value * @param[out] l3_addr1_reg: Pointer to L3 ADDR1 register value
* @param[out] ctr_reg: Pointer to L3L4 CTR register value
* *
* @note 1) MAC should be init and started. see osi_start_mac() * @note 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated * 2) osi_core->osd should be populated

4
osi/core/debug.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -20,6 +20,7 @@
* DEALINGS IN THE SOFTWARE. * DEALINGS IN THE SOFTWARE.
*/ */
#ifdef OSI_DEBUG
#ifndef INCLUDED_CORE_DEBUG_H #ifndef INCLUDED_CORE_DEBUG_H
#define INCLUDED_CORE_DEBUG_H #define INCLUDED_CORE_DEBUG_H
@@ -32,3 +33,4 @@ void core_reg_dump(struct osi_core_priv_data *osi_core);
void core_structs_dump(struct osi_core_priv_data *osi_core); void core_structs_dump(struct osi_core_priv_data *osi_core);
#endif /* INCLUDED_CORE_DEBUG_H*/ #endif /* INCLUDED_CORE_DEBUG_H*/
#endif /* OSI_DEBUG */

8
osi/core/eqos_core.c
View File

@@ -533,7 +533,7 @@ done:
* Algorithm: * Algorithm:
* *
* @param[in] osi_core: OSI core private data. * @param[in] osi_core: OSI core private data.
* @param[in] enabled: Flag to indicate feature is to be enabled/disabled. * @param[in] nve: Number of Valid Entries.
* *
* @note MAC should be init and started. see osi_start_mac() * @note MAC should be init and started. see osi_start_mac()
* *
@@ -1243,8 +1243,6 @@ static void eqos_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core)
* @param[in] osi_core: OSI core private data structure. Used params are * @param[in] osi_core: OSI core private data structure. Used params are
* - base, dcs_en, num_mtl_queues, mtl_queues, mtu, stip_vlan_tag, pause_frames, * - base, dcs_en, num_mtl_queues, mtl_queues, mtu, stip_vlan_tag, pause_frames,
* l3l4_filter_bitmask * l3l4_filter_bitmask
* @param[in] tx_fifo_size: MTL TX FIFO size. Max 11.
* @param[in] rx_fifo_size: MTL RX FIFO size. Max 11.
* *
* @pre * @pre
* - MAC should be out of reset. See osi_poll_for_mac_reset_complete() * - MAC should be out of reset. See osi_poll_for_mac_reset_complete()
@@ -1990,9 +1988,9 @@ static void eqos_config_mac_tx(struct osi_core_priv_data *const osi_core,
* @param[in] osi_core: OSI core private data structure. Used param base. * @param[in] osi_core: OSI core private data structure. Used param base.
* @param[out] value: nveu32_t pointer which has value read from register. * @param[out] value: nveu32_t pointer which has value read from register.
* @param[in] idx: Refer #osi_filter->index for details. * @param[in] idx: Refer #osi_filter->index for details.
* @param[in] dma_routing_enable: Refer #osi_filter->dma_routing for details.
* @param[in] dma_chan: Refer #osi_filter->dma_chan for details. * @param[in] dma_chan: Refer #osi_filter->dma_chan for details.
* @param[in] addr_mask: Refer #osi_filter->addr_mask for details. * @param[in] addr_mask: Refer #osi_filter->addr_mask for details.
* @param[in] src_dest: source/destination MAC address.
* *
* @pre * @pre
* - MAC should be initialized and started. see osi_start_mac() * - MAC should be initialized and started. see osi_start_mac()
@@ -2066,7 +2064,7 @@ static inline nve32_t eqos_update_mac_addr_helper(
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[out] value: nveu32_t pointer which has value read from register. * @param[out] value: nveu32_t pointer which has value read from register.
* @param[in] idx: filter index * @param[in] filter_idx: filter index
* @param[in] dma_routing_enable: dma channel routing enable(1) * @param[in] dma_routing_enable: dma channel routing enable(1)
* @param[in] dma_chan: dma channel number * @param[in] dma_chan: dma channel number
* *

6
osi/core/eqos_core.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -158,9 +158,9 @@
#define EQOS_MTL_FRP_IE2_DCH_SHIFT 24U #define EQOS_MTL_FRP_IE2_DCH_SHIFT 24U
#define EQOS_DMA_ISR_MTLIS OSI_BIT(16) #define EQOS_DMA_ISR_MTLIS OSI_BIT(16)
/** /**
* @addtogroup EQOS-MTL FRP Indirect Access register defines * @addtogroup EQOS-MTL-FRP FRP Indirect Access register defines
* *
* @brief EQOS MTL register offsets * @brief EQOS MTL FRP register defines
* @{ * @{
*/ */
#define EQOS_MTL_FRP_READ_UDELAY 1U #define EQOS_MTL_FRP_READ_UDELAY 1U

8
osi/core/frp.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -210,6 +210,7 @@ static void frp_entry_mode_parse(nveu8_t filter_mode,
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] frp_id: FRP ID to add. * @param[in] frp_id: FRP ID to add.
* @param[in] pos: FRP entry position.
* @param[in] match: Pointer to match data. * @param[in] match: Pointer to match data.
* @param[in] length: Match data length. * @param[in] length: Match data length.
* @param[in] offset: Actual match data offset position. * @param[in] offset: Actual match data offset position.
@@ -373,6 +374,7 @@ done:
* Algorithm: Update FRP table into HW. * Algorithm: Update FRP table into HW.
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] ops_p: Core operations data structure.
* *
* @retval 0 on success. * @retval 0 on success.
* @retval -1 on failure. * @retval -1 on failure.
@@ -602,6 +604,7 @@ static void frp_parse_mtype(struct osi_core_frp_cmd *const cmd)
* Algorithm: Parse give FRP delete command and update it on OSI data and HW. * Algorithm: Parse give FRP delete command and update it on OSI data and HW.
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] ops_p: Core operations data structure.
* @param[in] cmd: OSI FRP command structure. * @param[in] cmd: OSI FRP command structure.
* *
* @retval 0 on success. * @retval 0 on success.
@@ -675,6 +678,7 @@ done:
* Algorithm: Parse give FRP update command and update it on OSI data and HW. * Algorithm: Parse give FRP update command and update it on OSI data and HW.
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] ops_p: Core operations data structure.
* @param[in] cmd: OSI FRP command structure. * @param[in] cmd: OSI FRP command structure.
* *
* @retval 0 on success. * @retval 0 on success.
@@ -763,6 +767,7 @@ done:
* Algorithm: Parse give FRP Add command and update it on OSI data and HW. * Algorithm: Parse give FRP Add command and update it on OSI data and HW.
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] ops_p: Core operations data structure.
* @param[in] cmd: OSI FRP command structure. * @param[in] cmd: OSI FRP command structure.
* *
* @retval 0 on success. * @retval 0 on success.
@@ -840,6 +845,7 @@ done:
* Algorithm: Parse give FRP command and update it on OSI data and HW. * Algorithm: Parse give FRP command and update it on OSI data and HW.
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] ops_p: Core operations data structure.
* @param[in] cmd: OSI FRP command structure. * @param[in] cmd: OSI FRP command structure.
* *
* @retval 0 on success. * @retval 0 on success.

13
osi/core/ivc_core.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -91,8 +91,6 @@ static nve32_t ivc_handle_ioctl(struct osi_core_priv_data *osi_core,
* @brief ivc_core_init - EQOS MAC, MTL and common DMA Initialization * @brief ivc_core_init - EQOS MAC, MTL and common DMA Initialization
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] tx_fifo_size: MTL TX FIFO size
* @param[in] rx_fifo_size: MTL RX FIFO size
* *
* @retval 0 on success * @retval 0 on success
* @retval -1 on failure. * @retval -1 on failure.
@@ -303,10 +301,9 @@ static void ivc_macsec_read_mmc(struct osi_core_priv_data *const osi_core)
* @brief ivc_get_sc_lut_key_index - Macsec get Key_index * @brief ivc_get_sc_lut_key_index - Macsec get Key_index
* *
* @param[in] osi_core: OSI Core private data structure. * @param[in] osi_core: OSI Core private data structure.
* @param[in] sc: Secure Channel info. * @param[in] sci: Secure Channel info.
* @param[in] enable: enable or disable. * @param[out] key_index: Key table index to program SAK.
* @param[in] ctlr: Controller instance. * @param[in] ctlr: Controller instance.
* @param[[out] kt_idx: Key table index to program SAK.
* *
* @retval 0 on Success * @retval 0 on Success
* @retval -1 on Failure * @retval -1 on Failure
@@ -341,7 +338,7 @@ static nve32_t ivc_get_sc_lut_key_index(struct osi_core_priv_data *const osi_cor
* @param[in] sc: Secure Channel info. * @param[in] sc: Secure Channel info.
* @param[in] enable: enable or disable. * @param[in] enable: enable or disable.
* @param[in] ctlr: Controller instance. * @param[in] ctlr: Controller instance.
* @param[[out] kt_idx: Key table index to program SAK. * @param[out] kt_idx: Key table index to program SAK.
* *
* @retval 0 on Success * @retval 0 on Success
* @retval -1 on Failure * @retval -1 on Failure
@@ -556,7 +553,7 @@ static nve32_t ivc_macsec_deinit(struct osi_core_priv_data *const osi_core)
* @brief ivc_macsec_init -Initialize. * @brief ivc_macsec_init -Initialize.
* *
* @param[in] osi_core: OSI Core private data structure. * @param[in] osi_core: OSI Core private data structure.
* @param[in] genl_info: Generic netlink information structure. * @param[in] mtu: mtu to be set.
* *
* @retval 0 on Success * @retval 0 on Success
* @retval -1 on Failure * @retval -1 on Failure

4
osi/core/macsec.c
View File

@@ -4927,7 +4927,7 @@ static void copy_rev_order(nveu8_t *dst_buff, const nveu8_t *src_buff, nveu16_t
* - TraceID: *********** * - TraceID: ***********
* *
* @param[in] osi_core: OSI core private data structure. used param macsec_base * @param[in] osi_core: OSI core private data structure. used param macsec_base
* @param[in] error_mask: Error mask that indicate which LUTs need to be cleared * @param[in] mask: Error mask that indicate which LUTs need to be cleared
* @param[in] ctlr: Controller to be selected * @param[in] ctlr: Controller to be selected
* @param[in] sc: Pointer to the SC that was intended to be added * @param[in] sc: Pointer to the SC that was intended to be added
* *
@@ -5339,6 +5339,7 @@ exit:
* *
* @param[in] osi_core: OSI core private data structure. used param macsec_base * @param[in] osi_core: OSI core private data structure. used param macsec_base
* @param[in] sc: Pointer to the sc that need to be added/deleted/updated * @param[in] sc: Pointer to the sc that need to be added/deleted/updated
* @param[in] enable: enable or disable
* @param[in] ctlr: Controller to be selected * @param[in] ctlr: Controller to be selected
* @param[out] kt_idx: Key index to be passed to osd * @param[out] kt_idx: Key index to be passed to osd
* *
@@ -5899,6 +5900,7 @@ exit:
* *
* @param[in] osi_core: OSI core private data structure * @param[in] osi_core: OSI core private data structure
* @param[in] sc: Pointer to the sc that needs to be added/deleted/updated * @param[in] sc: Pointer to the sc that needs to be added/deleted/updated
* @param[in] enable: enable or disable
* @param[in] ctlr: Controller selected * @param[in] ctlr: Controller selected
* @param[out] kt_idx: Pointer to the kt_index passed to OSD * @param[out] kt_idx: Pointer to the kt_index passed to OSD
* *

12
osi/core/macsec.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -381,15 +381,7 @@
#define EQOS_MACSEC_SOT_DELAY 0x4EU #define EQOS_MACSEC_SOT_DELAY 0x4EU
/** /**
* @addtogroup TX/RX_BYP/SCI_LUT_VALID register * @addtogroup MACSEC-LUT TX/RX LUT bit fields in LUT_DATA registers
*
* @brief Bit definitions of LUT_VALID registers
* @{
*/
/** @} */
/**
* @addtogroup TX/RX LUT bit fields in LUT_DATA registers
* *
* @brief Helper macros for LUT data programming * @brief Helper macros for LUT data programming
* @{ * @{

27
osi/core/mgbe_core.c
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@@ -38,7 +38,7 @@
* Algorithm: Waits for waits for transfer busy bit to be cleared in * Algorithm: Waits for waits for transfer busy bit to be cleared in
* MAC Indirect address control register to complete operations. * MAC Indirect address control register to complete operations.
* *
* @param[in] addr: MGBE virtual base address. * @param[in] osi_core: osi core priv data structure
* *
* @note MAC needs to be out of reset and proper clock configured. * @note MAC needs to be out of reset and proper clock configured.
* *
@@ -75,7 +75,7 @@ static nve32_t mgbe_poll_for_mac_acrtl(struct osi_core_priv_data *osi_core)
* *
* Algorithm: writes MAC Indirect AC register * Algorithm: writes MAC Indirect AC register
* *
* @param[in] base: MGBE virtual base address. * @param[in] osi_core: osi core priv data structure
* @param[in] mc_no: MAC AC Mode Select number * @param[in] mc_no: MAC AC Mode Select number
* @param[in] addr_offset: MAC AC Address Offset. * @param[in] addr_offset: MAC AC Address Offset.
* @param[in] value: MAC AC register value * @param[in] value: MAC AC register value
@@ -134,7 +134,7 @@ static nve32_t mgbe_mac_indir_addr_write(struct osi_core_priv_data *osi_core,
* *
* Algorithm: Reads MAC Indirect AC register * Algorithm: Reads MAC Indirect AC register
* *
* @param[in] base: MGBE virtual base address. * @param[in] osi_core: osi core priv data structure
* @param[in] mc_no: MAC AC Mode Select number * @param[in] mc_no: MAC AC Mode Select number
* @param[in] addr_offset: MAC AC Address Offset. * @param[in] addr_offset: MAC AC Address Offset.
* @param[in] value: Pointer MAC AC register value * @param[in] value: Pointer MAC AC register value
@@ -387,7 +387,7 @@ fail:
* Algorithm: Waits for waits for transfer busy bit to be cleared in * Algorithm: Waits for waits for transfer busy bit to be cleared in
* L3_L4 address control register to complete filter register operations. * L3_L4 address control register to complete filter register operations.
* *
* @param[in] addr: MGBE virtual base address. * @param[in] osi_core: osi core priv data structure
* *
* @note MAC needs to be out of reset and proper clock configured. * @note MAC needs to be out of reset and proper clock configured.
* *
@@ -433,7 +433,7 @@ fail:
* *
* Algorithm: writes L3_L4 filter register * Algorithm: writes L3_L4 filter register
* *
* @param[in] base: MGBE virtual base address. * @param[in] osi_core: osi core priv data structure
* @param[in] filter_no: MGBE L3_L4 filter number * @param[in] filter_no: MGBE L3_L4 filter number
* @param[in] filter_type: MGBE L3_L4 filter register type. * @param[in] filter_type: MGBE L3_L4 filter register type.
* @param[in] value: MGBE L3_L4 filter register value * @param[in] value: MGBE L3_L4 filter register value
@@ -1119,8 +1119,8 @@ done:
* *
* Algorithm: * Algorithm:
* *
* @param[in] addr: MGBE virtual base address. * @param[in] osi_core: osi core priv data structure
* @param[in] enabled: Flag to indicate feature is to be enabled/disabled. * @param[in] nve: Number of Valid Entries.
* *
* @note MAC should be init and started. see osi_start_mac() * @note MAC should be init and started. see osi_start_mac()
* *
@@ -1171,9 +1171,8 @@ done:
* 6) Enable Rx Queues * 6) Enable Rx Queues
* 7) Enable TX Underflow Interrupt for MTL Q * 7) Enable TX Underflow Interrupt for MTL Q
* *
* @param[in] qinx: Queue number that need to be configured. * @param[in] osi_core: OSI core private data structure.
* @param[in] osi_core: OSI core private data. * @param[in] hw_qinx: Queue number that need to be configured.
* @param[in] tx_fifo: MTL TX queue size for a MTL queue.
* *
* @note MAC has to be out of reset. * @note MAC has to be out of reset.
* *
@@ -2172,7 +2171,6 @@ static inline nveu32_t get_free_ts_idx(struct core_local *l_core)
* MAC nve32_terrupts which includes speed, mode detection. * MAC nve32_terrupts which includes speed, mode detection.
* *
* @param[in] osi_core: OSI core private data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] dma_isr: DMA ISR register read value.
* *
* @note MAC nve32_terrupts need to be enabled * @note MAC nve32_terrupts need to be enabled
*/ */
@@ -2629,6 +2627,7 @@ fail:
* There is one status interrupt which says swich to SWOL complete. * There is one status interrupt which says swich to SWOL complete.
* *
* @param[in] osi_core: osi core priv data structure * @param[in] osi_core: osi core priv data structure
* @param[in] mtl_isr: MTL interrupt status value
* *
* @note MAC should be init and started. see osi_start_mac() * @note MAC should be init and started. see osi_start_mac()
*/ */
@@ -3644,8 +3643,7 @@ static nve32_t mgbe_get_hw_features(struct osi_core_priv_data *const osi_core,
* Algorithm: Read time stamp update value from TCR register until it is * Algorithm: Read time stamp update value from TCR register until it is
* equal to zero. * equal to zero.
* *
* @param[in] addr: Base address indicating the start of * @param[in] osi_core: OSI core private data structure.
* memory mapped IO region of the MAC.
* @param[in] mac_tcr: Address to store time stamp control register read value * @param[in] mac_tcr: Address to store time stamp control register read value
* *
* @note MAC should be init and started. see osi_start_mac() * @note MAC should be init and started. see osi_start_mac()
@@ -3681,8 +3679,7 @@ static inline nve32_t mgbe_poll_for_update_ts_complete(
* *
* Algorithm: Update MAC time with system time * Algorithm: Update MAC time with system time
* *
* @param[in] addr: Base address indicating the start of * @param[in] osi_core: OSI core private data structure.
* memory mapped IO region of the MAC.
* @param[in] sec: Seconds to be configured * @param[in] sec: Seconds to be configured
* @param[in] nsec: Nano seconds to be configured * @param[in] nsec: Nano seconds to be configured
* @param[in] add_sub: To decide on add/sub with system time * @param[in] add_sub: To decide on add/sub with system time

10
osi/core/mgbe_core.h
View File

@@ -249,9 +249,9 @@
OSI_BIT(5) | OSI_BIT(4)) OSI_BIT(5) | OSI_BIT(4))
/** /**
* @addtogroup MGBE-MTL FRP Indirect Access register defines * @addtogroup MGBE-MTL-FRP FRP Indirect Access register defines
* *
* @brief MGBE MTL register offsets * @brief MGBE MTL FRP register defines
* @{ * @{
*/ */
#define MGBE_MTL_FRP_READ_UDELAY 1U #define MGBE_MTL_FRP_READ_UDELAY 1U
@@ -390,7 +390,7 @@
/** /**
* @addtogroup MGBE MAC Mode Select Group * @addtogroup MGBE-MAC-MODE MAC Mode Select Group
* *
* @brief MGBE MAC Indirect Access control and status for * @brief MGBE MAC Indirect Access control and status for
* Mode Select type defines. * Mode Select type defines.
@@ -416,7 +416,7 @@
/** @} */ /** @} */
/** /**
* @addtogroup MGBE MAC L3L4 defines * @addtogroup MGBE-L3L4 MAC L3L4 defines
* *
* @brief MGBE L3L4 Address Control register * @brief MGBE L3L4 Address Control register
* IDDR filter filed type defines * IDDR filter filed type defines
@@ -742,7 +742,7 @@
#define TX_FIFO_SZ (((((128U * 1024U)/OSI_MGBE_MAX_NUM_QUEUES)) / 256U) - 1U) #define TX_FIFO_SZ (((((128U * 1024U)/OSI_MGBE_MAX_NUM_QUEUES)) / 256U) - 1U)
/** /**
* @addtogroup MGBE-MAC MGBE MAC HW feature registers * @addtogroup MGBE-MAC-HWFR MGBE MAC HW feature registers
* *
* @brief Helps in identifying the features that are set in MAC HW * @brief Helps in identifying the features that are set in MAC HW
* @{ * @{

2
osi/core/osi_core.c
View File

@@ -31,6 +31,7 @@ static struct core_local g_core[MAX_CORE_INSTANCES];
* @brief Function to validate function pointers. * @brief Function to validate function pointers.
* *
* @param[in] osi_core: OSI Core private data structure. * @param[in] osi_core: OSI Core private data structure.
* @param[in] if_ops_p: pointer to interface core operations.
* *
* @note * @note
* API Group: * API Group:
@@ -78,6 +79,7 @@ fail:
* @brief Function to validate input arguments of API. * @brief Function to validate input arguments of API.
* *
* @param[in] osi_core: OSI Core private data structure. * @param[in] osi_core: OSI Core private data structure.
* @param[in] l_core: Core local private data structure.
* *
* @note * @note
* API Group: * API Group:

4
osi/core/osi_hal.c
View File

@@ -813,7 +813,7 @@ static nve32_t l3l4_find_match(const struct core_local *const l_core,
* - Return -1 if parameter validation fails. * - Return -1 if parameter validation fails.
* - Return 0 on success. * - Return 0 on success.
* *
* @param[inout] l_core: OSI local core data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] l3_l4: Pointer to l3 l4 filter structure (#osi_l3_l4_filter) * @param[in] l3_l4: Pointer to l3 l4 filter structure (#osi_l3_l4_filter)
* *
* @pre * @pre
@@ -896,7 +896,7 @@ exit_func:
* - Store the filter into l_core->cfg.l3_l4[] and enable * - Store the filter into l_core->cfg.l3_l4[] and enable
* l3l4 filter if any of the filter index enabled currently. * l3l4 filter if any of the filter index enabled currently.
* *
* @param[inout] l_core: OSI local core data structure. * @param[in] osi_core: OSI core private data structure.
* @param[in] filter_no: pointer to filter number * @param[in] filter_no: pointer to filter number
* @param[in] l3_l4: Pointer to l3 l4 filter structure (#osi_l3_l4_filter) * @param[in] l3_l4: Pointer to l3 l4 filter structure (#osi_l3_l4_filter)
* *