diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c
index e2e1d28..a106c99 100644
--- a/osi/core/mgbe_core.c
+++ b/osi/core/mgbe_core.c
@@ -1200,8 +1200,8 @@ static nve32_t mgbe_configure_mtl_queue(struct osi_core_priv_data *osi_core,
 		FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(2U), FIFO_SZ(16U),
 	};
 	const nveu32_t tx_fifo_sz[OSI_MGBE_MAX_NUM_QUEUES] = {
-		FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U),
-		FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U), FIFO_SZ(12U),
+		TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ,
+		TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ, TX_FIFO_SZ,
 	};
 	const nveu32_t rfd_rfa[OSI_MGBE_MAX_NUM_QUEUES] = {
 		FULL_MINUS_32_K,
diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h
index 2be5f41..728c7ec 100644
--- a/osi/core/mgbe_core.h
+++ b/osi/core/mgbe_core.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -738,6 +738,9 @@
 /** @} */
 #endif /* !OSI_STRIPPED_LIB */
 
+/* TXQ Size 128KB is divided equally across 10 MTL Queues*/
+#define TX_FIFO_SZ	(((((128U * 1024U)/OSI_MGBE_MAX_NUM_QUEUES)) / 256U) - 1U)
+
 /**
  * @addtogroup MGBE-MAC MGBE MAC HW feature registers
  *