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osi: core: Update ethernet stats to VF osi core

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Issue:
When the ethernet server got enabled,
OSI core stats are not getting
updated to VF's.

Fix:
Add IOCTL to copy OSI core stats
into VF's OSI core structure.

Bug 3763499

Change-Id: Ib0a957ff90805b7e716d8f5994e0a65d63660c1e
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2808680
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mohan Thadikamalla
2022-11-14 15:10:14 +05:30
committed by Bhadram Varka
parent a84c9dafe3
commit 4cb630ef6e
8 changed files with 115 additions and 142 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
include/ivc_core.h
View File

@@ -35,14 +35,6 @@
*/ */
#define MAX_ARGS 10 #define MAX_ARGS 10
/*
*@brief All Stats
*/
struct osi_stats {
struct osi_mmc_counters mmc_s;
struct osi_tsn_stats tsn_s;
};
/** /**
* @brief IVC commands between OSD & OSI. * @brief IVC commands between OSD & OSI.
*/ */
@@ -151,13 +143,13 @@ typedef struct ivc_msg_common {
/** OSI HW features */ /** OSI HW features */
struct osi_hw_features hw_feat; struct osi_hw_features hw_feat;
/** MMC counters */ /** MMC counters */
struct osi_mmc_counters mmc; struct osi_mmc_counters mmc_s;
/** OSI stats counters */
struct osi_stats stats_s;
/** core argument structure */ /** core argument structure */
ivc_core_args init_args; ivc_core_args init_args;
/** ioctl command structure */ /** ioctl command structure */
struct osi_ioctl ioctl_data; struct osi_ioctl ioctl_data;
/** All stats */
struct osi_stats eth_stats;
#ifdef MACSEC_SUPPORT #ifdef MACSEC_SUPPORT
/** lut config */ /** lut config */
struct osi_macsec_lut_config lut_config; struct osi_macsec_lut_config lut_config;

36
include/mmc.h
View File

@@ -26,42 +26,6 @@
#include <nvethernet_type.h> #include <nvethernet_type.h>
#include "osi_common.h" #include "osi_common.h"
#ifndef OSI_STRIPPED_LIB
/**
* @brief osi_xtra_stat_counters - OSI core extra stat counters
*/
struct osi_xtra_stat_counters {
/** RX buffer unavailable irq count */
nveu64_t rx_buf_unavail_irq_n[OSI_MGBE_MAX_NUM_QUEUES];
/** Transmit Process Stopped irq count */
nveu64_t tx_proc_stopped_irq_n[OSI_MGBE_MAX_NUM_QUEUES];
/** Transmit Buffer Unavailable irq count */
nveu64_t tx_buf_unavail_irq_n[OSI_MGBE_MAX_NUM_QUEUES];
/** Receive Process Stopped irq count */
nveu64_t rx_proc_stopped_irq_n[OSI_MGBE_MAX_NUM_QUEUES];
/** Receive Watchdog Timeout irq count */
nveu64_t rx_watchdog_irq_n;
/** Fatal Bus Error irq count */
nveu64_t fatal_bus_error_irq_n;
/** rx skb allocation failure count */
nveu64_t re_alloc_rxbuf_failed[OSI_MGBE_MAX_NUM_QUEUES];
/** TX per channel interrupt count */
nveu64_t tx_normal_irq_n[OSI_MGBE_MAX_NUM_QUEUES];
/** TX per channel SW timer callback count */
nveu64_t tx_usecs_swtimer_n[OSI_MGBE_MAX_NUM_QUEUES];
/** RX per channel interrupt count */
nveu64_t rx_normal_irq_n[OSI_MGBE_MAX_NUM_QUEUES];
/** link connect count */
nveu64_t link_connect_count;
/** link disconnect count */
nveu64_t link_disconnect_count;
/** lock fail count node addition */
nveu64_t ts_lock_add_fail;
/** lock fail count node removal */
nveu64_t ts_lock_del_fail;
};
#endif /* !OSI_STRIPPED_LIB */
#ifdef MACSEC_SUPPORT #ifdef MACSEC_SUPPORT
/** /**
* @brief The structure hold macsec statistics counters * @brief The structure hold macsec statistics counters

33
include/nvethernetrm_export.h
View File

@@ -56,6 +56,9 @@
#define OSI_MTL_QUEUE_AVB 0x1U #define OSI_MTL_QUEUE_AVB 0x1U
#define OSI_MTL_QUEUE_ENABLE 0x2U #define OSI_MTL_QUEUE_ENABLE 0x2U
#define OSI_MTL_QUEUE_MODEMAX 0x3U #define OSI_MTL_QUEUE_MODEMAX 0x3U
#ifndef OSI_STRIPPED_LIB
#define OSI_MTL_MAX_NUM_QUEUES 10U
#endif
/** @} */ /** @} */
/** /**
@@ -181,9 +184,9 @@ struct osi_fpe_config {
}; };
/** /**
* @brief OSI Core TSN error stats structure * @brief OSI Core error stats structure
*/ */
struct osi_tsn_stats { struct osi_stats {
/** Constant Gate Control Error */ /** Constant Gate Control Error */
nveu64_t const_gate_ctr_err; nveu64_t const_gate_ctr_err;
/** Head-Of-Line Blocking due to Scheduling */ /** Head-Of-Line Blocking due to Scheduling */
@@ -198,6 +201,32 @@ struct osi_tsn_stats {
nveu64_t base_time_reg_err; nveu64_t base_time_reg_err;
/** Switch to Software Owned List Complete */ /** Switch to Software Owned List Complete */
nveu64_t sw_own_list_complete; nveu64_t sw_own_list_complete;
#ifndef OSI_STRIPPED_LIB
/** IP Header Error */
nveu64_t mgbe_ip_header_err;
/** Jabber time out Error */
nveu64_t mgbe_jabber_timeout_err;
/** Payload Checksum Error */
nveu64_t mgbe_payload_cs_err;
/** Under Flow Error */
nveu64_t mgbe_tx_underflow_err;
/** RX buffer unavailable irq count */
nveu64_t rx_buf_unavail_irq_n[OSI_MTL_MAX_NUM_QUEUES];
/** Transmit Process Stopped irq count */
nveu64_t tx_proc_stopped_irq_n[OSI_MTL_MAX_NUM_QUEUES];
/** Transmit Buffer Unavailable irq count */
nveu64_t tx_buf_unavail_irq_n[OSI_MTL_MAX_NUM_QUEUES];
/** Receive Process Stopped irq count */
nveu64_t rx_proc_stopped_irq_n[OSI_MTL_MAX_NUM_QUEUES];
/** Receive Watchdog Timeout irq count */
nveu64_t rx_watchdog_irq_n;
/** Fatal Bus Error irq count */
nveu64_t fatal_bus_error_irq_n;
/** lock fail count node addition */
nveu64_t ts_lock_add_fail;
/** lock fail count node removal */
nveu64_t ts_lock_del_fail;
#endif
}; };
/** /**

27
include/osi_core.h
View File

@@ -276,6 +276,7 @@ typedef my_lint_64 nvel64_t;
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
#define OSI_CMD_HSI_INJECT_ERR 55U #define OSI_CMD_HSI_INJECT_ERR 55U
#endif #endif
#define OSI_CMD_READ_STATS 56U
/** @} */ /** @} */
/** /**
@@ -1216,22 +1217,6 @@ struct core_padctrl {
nveu32_t pad_calibration_enable; nveu32_t pad_calibration_enable;
}; };
#ifndef OSI_STRIPPED_LIB
/**
* @brief OSI CORE packet error stats
*/
struct osi_core_pkt_err_stats {
/** IP Header Error */
nveu64_t mgbe_ip_header_err;
/** Jabber time out Error */
nveu64_t mgbe_jabber_timeout_err;
/** Payload Checksum Error */
nveu64_t mgbe_payload_cs_err;
/** Under Flow Error */
nveu64_t mgbe_tx_underflow_err;
};
#endif
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
/** /**
* @brief The OSI Core HSI private data structure. * @brief The OSI Core HSI private data structure.
@@ -1352,8 +1337,6 @@ struct osi_core_priv_data {
/** TQ:TC mapping */ /** TQ:TC mapping */
nveu32_t tc[OSI_MGBE_MAX_NUM_CHANS]; nveu32_t tc[OSI_MGBE_MAX_NUM_CHANS];
#ifndef OSI_STRIPPED_LIB #ifndef OSI_STRIPPED_LIB
/** xtra sw error counters */
struct osi_xtra_stat_counters xstats;
/** Memory mapped base address of HV window */ /** Memory mapped base address of HV window */
void *hv_base; void *hv_base;
/** csr clock is to program LPI 1 us tick timer register. /** csr clock is to program LPI 1 us tick timer register.
@@ -1382,8 +1365,8 @@ struct osi_core_priv_data {
* 1- Successful and can be used between P2P device * 1- Successful and can be used between P2P device
*/ */
nveu32_t fpe_ready; nveu32_t fpe_ready;
/** TSN stats counters */ /** MAC stats counters */
struct osi_tsn_stats tsn_stats; struct osi_stats stats;
/** eqos pad control structure */ /** eqos pad control structure */
struct core_padctrl padctrl; struct core_padctrl padctrl;
/** MDC clock rate */ /** MDC clock rate */
@@ -1409,10 +1392,6 @@ struct osi_core_priv_data {
nveu32_t phy_iface_mode; nveu32_t phy_iface_mode;
/** MGBE MAC instance ID's */ /** MGBE MAC instance ID's */
nveu32_t instance_id; nveu32_t instance_id;
#ifndef OSI_STRIPPED_LIB
/** Packet error stats */
struct osi_core_pkt_err_stats pkt_err_stats;
#endif
/** Ethernet controller MAC to MAC Time sync role /** Ethernet controller MAC to MAC Time sync role
* 1 - Primary interface, 2 - secondary interface, 0 - inactive interface * 1 - Primary interface, 2 - secondary interface, 0 - inactive interface
*/ */

55
osi/core/eqos_core.c
View File

@@ -1561,33 +1561,33 @@ static inline void update_dma_sr_stats(
nveu64_t val; nveu64_t val;
if ((dma_sr & EQOS_DMA_CHX_STATUS_RBU) == EQOS_DMA_CHX_STATUS_RBU) { if ((dma_sr & EQOS_DMA_CHX_STATUS_RBU) == EQOS_DMA_CHX_STATUS_RBU) {
val = osi_core->xstats.rx_buf_unavail_irq_n[qinx]; val = osi_core->stats.rx_buf_unavail_irq_n[qinx];
osi_core->xstats.rx_buf_unavail_irq_n[qinx] = osi_core->stats.rx_buf_unavail_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & EQOS_DMA_CHX_STATUS_TPS) == EQOS_DMA_CHX_STATUS_TPS) { if ((dma_sr & EQOS_DMA_CHX_STATUS_TPS) == EQOS_DMA_CHX_STATUS_TPS) {
val = osi_core->xstats.tx_proc_stopped_irq_n[qinx]; val = osi_core->stats.tx_proc_stopped_irq_n[qinx];
osi_core->xstats.tx_proc_stopped_irq_n[qinx] = osi_core->stats.tx_proc_stopped_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & EQOS_DMA_CHX_STATUS_TBU) == EQOS_DMA_CHX_STATUS_TBU) { if ((dma_sr & EQOS_DMA_CHX_STATUS_TBU) == EQOS_DMA_CHX_STATUS_TBU) {
val = osi_core->xstats.tx_buf_unavail_irq_n[qinx]; val = osi_core->stats.tx_buf_unavail_irq_n[qinx];
osi_core->xstats.tx_buf_unavail_irq_n[qinx] = osi_core->stats.tx_buf_unavail_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & EQOS_DMA_CHX_STATUS_RPS) == EQOS_DMA_CHX_STATUS_RPS) { if ((dma_sr & EQOS_DMA_CHX_STATUS_RPS) == EQOS_DMA_CHX_STATUS_RPS) {
val = osi_core->xstats.rx_proc_stopped_irq_n[qinx]; val = osi_core->stats.rx_proc_stopped_irq_n[qinx];
osi_core->xstats.rx_proc_stopped_irq_n[qinx] = osi_core->stats.rx_proc_stopped_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & EQOS_DMA_CHX_STATUS_RWT) == EQOS_DMA_CHX_STATUS_RWT) { if ((dma_sr & EQOS_DMA_CHX_STATUS_RWT) == EQOS_DMA_CHX_STATUS_RWT) {
val = osi_core->xstats.rx_watchdog_irq_n; val = osi_core->stats.rx_watchdog_irq_n;
osi_core->xstats.rx_watchdog_irq_n = osi_core->stats.rx_watchdog_irq_n =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & EQOS_DMA_CHX_STATUS_FBE) == EQOS_DMA_CHX_STATUS_FBE) { if ((dma_sr & EQOS_DMA_CHX_STATUS_FBE) == EQOS_DMA_CHX_STATUS_FBE) {
val = osi_core->xstats.fatal_bus_error_irq_n; val = osi_core->stats.fatal_bus_error_irq_n;
osi_core->xstats.fatal_bus_error_irq_n = osi_core->stats.fatal_bus_error_irq_n =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
} }
@@ -1634,15 +1634,15 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
/* increase counter write 1 back will clear */ /* increase counter write 1 back will clear */
if ((val & EQOS_MTL_EST_STATUS_CGCE) == EQOS_MTL_EST_STATUS_CGCE) { if ((val & EQOS_MTL_EST_STATUS_CGCE) == EQOS_MTL_EST_STATUS_CGCE) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.const_gate_ctr_err; stat_val = osi_core->stats.const_gate_ctr_err;
osi_core->tsn_stats.const_gate_ctr_err = osi_core->stats.const_gate_ctr_err =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
if ((val & EQOS_MTL_EST_STATUS_HLBS) == EQOS_MTL_EST_STATUS_HLBS) { if ((val & EQOS_MTL_EST_STATUS_HLBS) == EQOS_MTL_EST_STATUS_HLBS) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.head_of_line_blk_sch; stat_val = osi_core->stats.head_of_line_blk_sch;
osi_core->tsn_stats.head_of_line_blk_sch = osi_core->stats.head_of_line_blk_sch =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
/* Need to read MTL_EST_Sch_Error register and cleared */ /* Need to read MTL_EST_Sch_Error register and cleared */
sch_err = osi_readla(osi_core, (nveu8_t *)osi_core->base + sch_err = osi_readla(osi_core, (nveu8_t *)osi_core->base +
@@ -1651,8 +1651,8 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
temp = OSI_ENABLE; temp = OSI_ENABLE;
temp = temp << i; temp = temp << i;
if ((sch_err & temp) == temp) { if ((sch_err & temp) == temp) {
stat_val = osi_core->tsn_stats.hlbs_q[i]; stat_val = osi_core->stats.hlbs_q[i];
osi_core->tsn_stats.hlbs_q[i] = osi_core->stats.hlbs_q[i] =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
} }
@@ -1675,8 +1675,8 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
if ((val & EQOS_MTL_EST_STATUS_HLBF) == EQOS_MTL_EST_STATUS_HLBF) { if ((val & EQOS_MTL_EST_STATUS_HLBF) == EQOS_MTL_EST_STATUS_HLBF) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.head_of_line_blk_frm; stat_val = osi_core->stats.head_of_line_blk_frm;
osi_core->tsn_stats.head_of_line_blk_frm = osi_core->stats.head_of_line_blk_frm =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
/* Need to read MTL_EST_Frm_Size_Error register and cleared */ /* Need to read MTL_EST_Frm_Size_Error register and cleared */
frm_err = osi_readla(osi_core, (nveu8_t *)osi_core->base + frm_err = osi_readla(osi_core, (nveu8_t *)osi_core->base +
@@ -1685,8 +1685,8 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
temp = OSI_ENABLE; temp = OSI_ENABLE;
temp = temp << i; temp = temp << i;
if ((frm_err & temp) == temp) { if ((frm_err & temp) == temp) {
stat_val = osi_core->tsn_stats.hlbf_q[i]; stat_val = osi_core->stats.hlbf_q[i];
osi_core->tsn_stats.hlbf_q[i] = osi_core->stats.hlbf_q[i] =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
} }
@@ -1713,15 +1713,15 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
EQOS_MTL_EST_STATUS_BTRE) { EQOS_MTL_EST_STATUS_BTRE) {
osi_core->est_ready = OSI_ENABLE; osi_core->est_ready = OSI_ENABLE;
} }
stat_val = osi_core->tsn_stats.sw_own_list_complete; stat_val = osi_core->stats.sw_own_list_complete;
osi_core->tsn_stats.sw_own_list_complete = osi_core->stats.sw_own_list_complete =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
if ((val & EQOS_MTL_EST_STATUS_BTRE) == EQOS_MTL_EST_STATUS_BTRE) { if ((val & EQOS_MTL_EST_STATUS_BTRE) == EQOS_MTL_EST_STATUS_BTRE) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.base_time_reg_err; stat_val = osi_core->stats.base_time_reg_err;
osi_core->tsn_stats.base_time_reg_err = osi_core->stats.base_time_reg_err =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
} }
@@ -1818,7 +1818,8 @@ static void eqos_handle_hsi_intr(struct osi_core_priv_data *const osi_core)
* Algorithm: * Algorithm:
* - Reads DMA ISR register * - Reads DMA ISR register
* - Returns if calue is 0. * - Returns if calue is 0.
* - Handle Non-TI/RI interrupts for all MTL queues and increments #osi_core_priv_data->xstats * - Handle Non-TI/RI interrupts for all MTL queues and
* increments #osi_core_priv_data->stats
* based on error detected per cahnnel. * based on error detected per cahnnel.
* - Calls eqos_handle_mac_intrs() to handle MAC interrupts. * - Calls eqos_handle_mac_intrs() to handle MAC interrupts.
* - Refer to EQOS column of <<RM_10, (sequence diagram)>> for API details. * - Refer to EQOS column of <<RM_10, (sequence diagram)>> for API details.

20
osi/core/ivc_core.c
View File

@@ -64,18 +64,26 @@ static nve32_t ivc_handle_ioctl(struct osi_core_priv_data *osi_core,
ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg));
if (data->cmd == OSI_CMD_READ_MMC) { switch (data->cmd) {
case OSI_CMD_READ_MMC:
(void)osi_memcpy((void *)&osi_core->mmc, (void)osi_memcpy((void *)&osi_core->mmc,
(void *)&msg.data.mmc, (void *)&msg.data.mmc_s,
sizeof(struct osi_mmc_counters)); sizeof(struct osi_mmc_counters));
(void)osi_memcpy((void *)&osi_core->tsn_stats, break;
(void *)&msg.data.eth_stats.tsn_s,
sizeof(struct osi_tsn_stats)); case OSI_CMD_READ_STATS:
} else { (void)osi_memcpy((void *)&osi_core->stats,
(void *)&msg.data.stats_s,
sizeof(struct osi_stats));
break;
default:
(void)osi_memcpy((void *)data, (void)osi_memcpy((void *)data,
(void *)&msg.data.ioctl_data, (void *)&msg.data.ioctl_data,
sizeof(struct osi_ioctl)); sizeof(struct osi_ioctl));
break;
} }
return ret; return ret;
} }

68
osi/core/mgbe_core.c
View File

@@ -2771,23 +2771,23 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core,
MGBE_MAC_RX_TX_STS); MGBE_MAC_RX_TX_STS);
if ((tx_errors & MGBE_MAC_TX_TJT) == MGBE_MAC_TX_TJT) { if ((tx_errors & MGBE_MAC_TX_TJT) == MGBE_MAC_TX_TJT) {
/* increment Tx Jabber timeout stats */ /* increment Tx Jabber timeout stats */
osi_core->pkt_err_stats.mgbe_jabber_timeout_err = osi_core->stats.mgbe_jabber_timeout_err =
osi_update_stats_counter( osi_update_stats_counter(
osi_core->pkt_err_stats.mgbe_jabber_timeout_err, osi_core->stats.mgbe_jabber_timeout_err,
1UL); 1UL);
} }
if ((tx_errors & MGBE_MAC_TX_IHE) == MGBE_MAC_TX_IHE) { if ((tx_errors & MGBE_MAC_TX_IHE) == MGBE_MAC_TX_IHE) {
/* IP Header Error */ /* IP Header Error */
osi_core->pkt_err_stats.mgbe_ip_header_err = osi_core->stats.mgbe_ip_header_err =
osi_update_stats_counter( osi_update_stats_counter(
osi_core->pkt_err_stats.mgbe_ip_header_err, osi_core->stats.mgbe_ip_header_err,
1UL); 1UL);
} }
if ((tx_errors & MGBE_MAC_TX_PCE) == MGBE_MAC_TX_PCE) { if ((tx_errors & MGBE_MAC_TX_PCE) == MGBE_MAC_TX_PCE) {
/* Payload Checksum error */ /* Payload Checksum error */
osi_core->pkt_err_stats.mgbe_payload_cs_err = osi_core->stats.mgbe_payload_cs_err =
osi_update_stats_counter( osi_update_stats_counter(
osi_core->pkt_err_stats.mgbe_payload_cs_err, osi_core->stats.mgbe_payload_cs_err,
1UL); 1UL);
} }
} }
@@ -2800,9 +2800,9 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core,
/* mask return as initial value is returned always */ /* mask return as initial value is returned always */
(void)__sync_fetch_and_sub(&l_core->ts_lock, 1); (void)__sync_fetch_and_sub(&l_core->ts_lock, 1);
#ifndef OSI_STRIPPED_LIB #ifndef OSI_STRIPPED_LIB
osi_core->xstats.ts_lock_add_fail = osi_core->stats.ts_lock_add_fail =
osi_update_stats_counter( osi_update_stats_counter(
osi_core->xstats.ts_lock_add_fail, 1U); osi_core->stats.ts_lock_add_fail, 1U);
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
goto done; goto done;
} }
@@ -2873,28 +2873,28 @@ static inline void mgbe_update_dma_sr_stats(struct osi_core_priv_data *osi_core,
nveu64_t val; nveu64_t val;
if ((dma_sr & MGBE_DMA_CHX_STATUS_RBU) == MGBE_DMA_CHX_STATUS_RBU) { if ((dma_sr & MGBE_DMA_CHX_STATUS_RBU) == MGBE_DMA_CHX_STATUS_RBU) {
val = osi_core->xstats.rx_buf_unavail_irq_n[qinx]; val = osi_core->stats.rx_buf_unavail_irq_n[qinx];
osi_core->xstats.rx_buf_unavail_irq_n[qinx] = osi_core->stats.rx_buf_unavail_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & MGBE_DMA_CHX_STATUS_TPS) == MGBE_DMA_CHX_STATUS_TPS) { if ((dma_sr & MGBE_DMA_CHX_STATUS_TPS) == MGBE_DMA_CHX_STATUS_TPS) {
val = osi_core->xstats.tx_proc_stopped_irq_n[qinx]; val = osi_core->stats.tx_proc_stopped_irq_n[qinx];
osi_core->xstats.tx_proc_stopped_irq_n[qinx] = osi_core->stats.tx_proc_stopped_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & MGBE_DMA_CHX_STATUS_TBU) == MGBE_DMA_CHX_STATUS_TBU) { if ((dma_sr & MGBE_DMA_CHX_STATUS_TBU) == MGBE_DMA_CHX_STATUS_TBU) {
val = osi_core->xstats.tx_buf_unavail_irq_n[qinx]; val = osi_core->stats.tx_buf_unavail_irq_n[qinx];
osi_core->xstats.tx_buf_unavail_irq_n[qinx] = osi_core->stats.tx_buf_unavail_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & MGBE_DMA_CHX_STATUS_RPS) == MGBE_DMA_CHX_STATUS_RPS) { if ((dma_sr & MGBE_DMA_CHX_STATUS_RPS) == MGBE_DMA_CHX_STATUS_RPS) {
val = osi_core->xstats.rx_proc_stopped_irq_n[qinx]; val = osi_core->stats.rx_proc_stopped_irq_n[qinx];
osi_core->xstats.rx_proc_stopped_irq_n[qinx] = osi_core->stats.rx_proc_stopped_irq_n[qinx] =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
if ((dma_sr & MGBE_DMA_CHX_STATUS_FBE) == MGBE_DMA_CHX_STATUS_FBE) { if ((dma_sr & MGBE_DMA_CHX_STATUS_FBE) == MGBE_DMA_CHX_STATUS_FBE) {
val = osi_core->xstats.fatal_bus_error_irq_n; val = osi_core->stats.fatal_bus_error_irq_n;
osi_core->xstats.fatal_bus_error_irq_n = osi_core->stats.fatal_bus_error_irq_n =
osi_update_stats_counter(val, 1U); osi_update_stats_counter(val, 1U);
} }
} }
@@ -3196,9 +3196,9 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core,
/* Transmit Queue Underflow Interrupt Status */ /* Transmit Queue Underflow Interrupt Status */
if ((qstatus & MGBE_MTL_QINT_TXUNIFS) == MGBE_MTL_QINT_TXUNIFS) { if ((qstatus & MGBE_MTL_QINT_TXUNIFS) == MGBE_MTL_QINT_TXUNIFS) {
#ifndef OSI_STRIPPED_LIB #ifndef OSI_STRIPPED_LIB
osi_core->pkt_err_stats.mgbe_tx_underflow_err = osi_core->stats.mgbe_tx_underflow_err =
osi_update_stats_counter( osi_update_stats_counter(
osi_core->pkt_err_stats.mgbe_tx_underflow_err, osi_core->stats.mgbe_tx_underflow_err,
1UL); 1UL);
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
} }
@@ -3226,15 +3226,15 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core,
/* increase counter write 1 back will clear */ /* increase counter write 1 back will clear */
if ((val & MGBE_MTL_EST_STATUS_CGCE) == MGBE_MTL_EST_STATUS_CGCE) { if ((val & MGBE_MTL_EST_STATUS_CGCE) == MGBE_MTL_EST_STATUS_CGCE) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.const_gate_ctr_err; stat_val = osi_core->stats.const_gate_ctr_err;
osi_core->tsn_stats.const_gate_ctr_err = osi_core->stats.const_gate_ctr_err =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
if ((val & MGBE_MTL_EST_STATUS_HLBS) == MGBE_MTL_EST_STATUS_HLBS) { if ((val & MGBE_MTL_EST_STATUS_HLBS) == MGBE_MTL_EST_STATUS_HLBS) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.head_of_line_blk_sch; stat_val = osi_core->stats.head_of_line_blk_sch;
osi_core->tsn_stats.head_of_line_blk_sch = osi_core->stats.head_of_line_blk_sch =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
/* Need to read MTL_EST_Sch_Error register and cleared */ /* Need to read MTL_EST_Sch_Error register and cleared */
sch_err = osi_readla(osi_core, (nveu8_t *)osi_core->base + sch_err = osi_readla(osi_core, (nveu8_t *)osi_core->base +
@@ -3243,8 +3243,8 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core,
temp = OSI_ENABLE; temp = OSI_ENABLE;
temp = temp << i; temp = temp << i;
if ((sch_err & temp) == temp) { if ((sch_err & temp) == temp) {
stat_val = osi_core->tsn_stats.hlbs_q[i]; stat_val = osi_core->stats.hlbs_q[i];
osi_core->tsn_stats.hlbs_q[i] = osi_core->stats.hlbs_q[i] =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
} }
@@ -3263,8 +3263,8 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core,
if ((val & MGBE_MTL_EST_STATUS_HLBF) == MGBE_MTL_EST_STATUS_HLBF) { if ((val & MGBE_MTL_EST_STATUS_HLBF) == MGBE_MTL_EST_STATUS_HLBF) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.head_of_line_blk_frm; stat_val = osi_core->stats.head_of_line_blk_frm;
osi_core->tsn_stats.head_of_line_blk_frm = osi_core->stats.head_of_line_blk_frm =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
/* Need to read MTL_EST_Frm_Size_Error register and cleared */ /* Need to read MTL_EST_Frm_Size_Error register and cleared */
frm_err = osi_readla(osi_core, (nveu8_t *)osi_core->base + frm_err = osi_readla(osi_core, (nveu8_t *)osi_core->base +
@@ -3273,8 +3273,8 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core,
temp = OSI_ENABLE; temp = OSI_ENABLE;
temp = temp << i; temp = temp << i;
if ((frm_err & temp) == temp) { if ((frm_err & temp) == temp) {
stat_val = osi_core->tsn_stats.hlbf_q[i]; stat_val = osi_core->stats.hlbf_q[i];
osi_core->tsn_stats.hlbf_q[i] = osi_core->stats.hlbf_q[i] =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
} }
@@ -3302,15 +3302,15 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core,
MGBE_MTL_EST_STATUS_BTRE) { MGBE_MTL_EST_STATUS_BTRE) {
osi_core->est_ready = OSI_ENABLE; osi_core->est_ready = OSI_ENABLE;
} }
stat_val = osi_core->tsn_stats.sw_own_list_complete; stat_val = osi_core->stats.sw_own_list_complete;
osi_core->tsn_stats.sw_own_list_complete = osi_core->stats.sw_own_list_complete =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
} }
if ((val & MGBE_MTL_EST_STATUS_BTRE) == MGBE_MTL_EST_STATUS_BTRE) { if ((val & MGBE_MTL_EST_STATUS_BTRE) == MGBE_MTL_EST_STATUS_BTRE) {
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
stat_val = osi_core->tsn_stats.base_time_reg_err; stat_val = osi_core->stats.base_time_reg_err;
osi_core->tsn_stats.base_time_reg_err = osi_core->stats.base_time_reg_err =
osi_update_stats_counter(stat_val, 1U); osi_update_stats_counter(stat_val, 1U);
osi_core->est_ready = OSI_DISABLE; osi_core->est_ready = OSI_DISABLE;
} }

4
osi/core/osi_hal.c
View File

@@ -1537,9 +1537,9 @@ static inline nve32_t get_tx_ts(struct osi_core_priv_data *osi_core,
/* mask return as initial value is returned always */ /* mask return as initial value is returned always */
(void)__sync_fetch_and_sub(&l_core->ts_lock, 1); (void)__sync_fetch_and_sub(&l_core->ts_lock, 1);
#ifndef OSI_STRIPPED_LIB #ifndef OSI_STRIPPED_LIB
osi_core->xstats.ts_lock_del_fail = osi_core->stats.ts_lock_del_fail =
osi_update_stats_counter( osi_update_stats_counter(
osi_core->xstats.ts_lock_del_fail, 1U); osi_core->stats.ts_lock_del_fail, 1U);
#endif #endif
goto done; goto done;
} }