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nvethernetrm: fix review CG and DG comments

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- Include header gaurds using INCLUDED_
- Move static inline function to private
  header file.
- Move private macro to private header

Bug 200681427

Change-Id: I810184e077a5642f727e47b9280d3fb9659abd74
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2455014
(cherry picked from commit b3afc7a112460d7f92d8ef0fbe8727c7acd9ec44)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2457307
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
rakesh goyal
2020-12-04 13:14:20 +05:30
committed by mobile promotions
parent 670622893f
commit 56b160f12e
21 changed files with 387 additions and 324 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
include/mmc.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef MMC_H
#define MMC_H
#ifndef INCLUDED_MMC_H
#define INCLUDED_MMC_H
/**
* @brief osi_mmc_counters - The structure to hold RMON counter values
*/

6
include/osd.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef OSD_H
#define OSD_H
#ifndef INCLUDED_OSD_H
#define INCLUDED_OSD_H
#include "../osi/common/type.h"
@@ -148,4 +148,4 @@ void osd_log(void *priv,
nveu32_t type,
const nve8_t *err,
nveul64_t loga);
#endif
#endif /* INCLUDED_OSD_H */

187
include/osi_common.h
View File

@@ -20,10 +20,11 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef OSI_COMMON_H
#define OSI_COMMON_H
#ifndef INCLUDED_OSI_COMMON_H
#define INCLUDED_OSI_COMMON_H
#include "../osi/common/type.h"
/**
* @addtogroup Helper Helper MACROS
*
@@ -157,7 +158,6 @@
#define OSI_NONE 0U
#define OSI_DISABLE 0U
#define OSI_BIT(nr) ((nveu32_t)1 << (nr))
#define OSI_EQOS_MAC_4_10 0x41U
@@ -567,185 +567,6 @@ struct osi_hw_features {
nveu32_t num_tbs_ch;
};
/**
* @brief osi_lock_init - Initialize lock to unlocked state.
*
* @note
* Algorithm:
* - Set lock to unlocked state.
*
* @param[in] lock - Pointer to lock to be initialized
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*/
static inline void osi_lock_init(nveu32_t *lock)
{
*lock = OSI_UNLOCKED;
}
/**
* @brief osi_lock_irq_enabled - Spin lock. Busy loop till lock is acquired.
*
* @note
* Algorithm:
* - Atomic compare and swap operation till lock is held.
*
* @param[in] lock - Pointer to lock to be acquired.
*
* @note
* - Does not disable irq. Do not call this API to acquire any
* lock that is shared between top/bottom half. It will result in deadlock.
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
static inline void osi_lock_irq_enabled(nveu32_t *lock)
{
/* __sync_val_compare_and_swap(lock, old value, new value) returns the
* old value if successful.
*/
while (__sync_val_compare_and_swap(lock, OSI_UNLOCKED, OSI_LOCKED) !=
OSI_UNLOCKED) {
/* Spinning.
* Will deadlock if any ISR tried to lock again.
*/
}
}
/**
* @brief osi_unlock_irq_enabled - Release lock.
*
* @note
* Algorithm:
* - Atomic compare and swap operation to release lock.
*
* @param[in] lock - Pointer to lock to be released.
*
* @note
* - Does not disable irq. Do not call this API to release any
* lock that is shared between top/bottom half.
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
static inline void osi_unlock_irq_enabled(nveu32_t *lock)
{
if (__sync_val_compare_and_swap(lock, OSI_LOCKED, OSI_UNLOCKED) !=
OSI_LOCKED) {
/* Do nothing. Already unlocked */
}
}
/**
* @brief osi_readl - Read a memory mapped register.
*
* @param[in] addr: Memory mapped address.
*
* @pre Physical address has to be memory mapped.
*
* @return Data from memory mapped register - success.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*/
static inline nveu32_t osi_readl(void *addr)
{
return *(volatile nveu32_t *)addr;
}
/**
* @brief osi_writel - Write to a memory mapped register.
*
* @param[in] val: Value to be written.
* @param[in] addr: Memory mapped address.
*
* @pre Physical address has to be memory mapped.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*/
static inline void osi_writel(nveu32_t val, void *addr)
{
*(volatile nveu32_t *)addr = val;
}
/**
* @brief is_valid_mac_version - Check if read MAC IP is valid or not.
*
* @param[in] mac_ver: MAC version read.
*
* @note MAC has to be out of reset.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*
* @retval 0 - for not Valid MAC
* @retval 1 - for Valid MAC
*/
static inline nve32_t is_valid_mac_version(nveu32_t mac_ver)
{
if ((mac_ver == OSI_EQOS_MAC_4_10) ||
(mac_ver == OSI_EQOS_MAC_5_00) ||
(mac_ver == OSI_EQOS_MAC_5_10)) {
return 1;
}
return 0;
}
/**
* @brief osi_update_stats_counter - update value by increment passed
* as parameter
*
* @note
* Algorithm:
* - Check for boundary and return sum
*
* @param[in] last_value: last value of stat counter
* @param[in] incr: increment value
*
* @note Input parameter should be only nveu64_t type
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @return nveu64_t value
*/
static inline nveu64_t osi_update_stats_counter(nveu64_t last_value,
nveu64_t incr)
{
nveu64_t temp = last_value + incr;
if (temp < last_value) {
/* Stats overflow, so reset it to zero */
return 0UL;
}
return temp;
}
/**
* @brief common_get_mac_version - Reading MAC version
*
@@ -798,4 +619,4 @@ void common_get_hw_features(void *base, struct osi_hw_features *hw_feat);
* - De-initialization: No
*/
void osi_memset(void *s, nveu32_t c, nveu64_t count);
#endif /* OSI_COMMON_H */
#endif /* INCLUDED_OSI_COMMON_H */

8
include/osi_core.h
View File

@@ -20,10 +20,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef OSI_CORE_H
#define OSI_CORE_H
#ifndef INCLUDED_OSI_CORE_H
#define INCLUDED_OSI_CORE_H
#include "osi_common.h"
#include "../osi/common/common.h"
#include "mmc.h"
#include "../osi/common/type.h"
@@ -2020,4 +2020,4 @@ nve32_t osi_set_mdc_clk_rate(struct osi_core_priv_data *const osi_core,
nve32_t osi_config_mac_loopback(struct osi_core_priv_data *const osi_core,
const nveu32_t lb_mode);
#endif /* !OSI_STRIPPED_LIB */
#endif /* OSI_CORE_H */
#endif /* INCLUDED_OSI_CORE_H */

8
include/osi_dma.h
View File

@@ -20,10 +20,10 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef OSI_DMA_H
#define OSI_DMA_H
#ifndef INCLUDED_OSI_DMA_H
#define INCLUDED_OSI_DMA_H
#include "osi_common.h"
#include "../osi/common/common.h"
#include "osi_dma_txrx.h"
/**
@@ -1419,4 +1419,4 @@ nve32_t osi_clear_rx_pkt_err_stats(struct osi_dma_priv_data *osi_dma);
*/
nve32_t osi_txring_empty(struct osi_dma_priv_data *osi_dma, nveu32_t chan);
#endif /* !OSI_STRIPPED_LIB */
#endif /* OSI_DMA_H */
#endif /* INCLUDED_OSI_DMA_H */

107
include/osi_dma_txrx.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef OSI_DMA_TXRX_H
#define OSI_DMA_TXRX_H
#ifndef INCLUDED_OSI_DMA_TXRX_H
#define INCLUDED_OSI_DMA_TXRX_H
/**
* @addtogroup EQOS_Help Descriptor Helper MACROS
@@ -53,105 +53,4 @@
#define DECR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (RX_DESC_CNT - 1U))
#endif /* !OSI_STRIPPED_LIB */
/** @} */
/**
* @addtogroup EQOS_RxDesc Receive Descriptors bit fields
*
* @brief These macros are used to check the value in specific bit fields of
* the descriptor. The fields in the descriptor are mapped as
* defined in the HW manual
* @{
*/
#define RDES3_OWN OSI_BIT(31)
#define RDES3_CTXT OSI_BIT(30)
#define RDES3_IOC OSI_BIT(30)
#define RDES3_B1V OSI_BIT(24)
#define RDES3_LD OSI_BIT(28)
#define RDES3_FD OSI_BIT(29)
#define RDES3_ERR_CRC OSI_BIT(24)
#define RDES3_ERR_GP OSI_BIT(23)
#define RDES3_ERR_WD OSI_BIT(22)
#define RDES3_ERR_ORUN OSI_BIT(21)
#define RDES3_ERR_RE OSI_BIT(20)
#define RDES3_ERR_DRIB OSI_BIT(19)
#define RDES3_PKT_LEN 0x00007fffU
#define RDES3_LT (OSI_BIT(16) | OSI_BIT(17) | OSI_BIT(18))
#define RDES3_LT_VT OSI_BIT(18)
#define RDES3_LT_DVT (OSI_BIT(16) | OSI_BIT(18))
#define RDES3_RS0V OSI_BIT(25)
#define RDES3_RS1V OSI_BIT(26)
#define RDES0_OVT 0x0000FFFFU
#define RDES1_TSA OSI_BIT(14)
#define RDES1_TD OSI_BIT(15)
#define RDES1_IPCE OSI_BIT(7)
#define RDES1_IPCB OSI_BIT(6)
#define RDES1_IPV6 OSI_BIT(5)
#define RDES1_IPV4 OSI_BIT(4)
#define RDES1_IPHE OSI_BIT(3)
#define RDES1_PT_TCP OSI_BIT(1)
#define RDES1_PT_UDP OSI_BIT(0)
/** @} */
/** Error Summary bits for Received packet */
#define RDES3_ES_BITS \
(RDES3_ERR_CRC | RDES3_ERR_GP | RDES3_ERR_WD | \
RDES3_ERR_ORUN | RDES3_ERR_RE | RDES3_ERR_DRIB)
/**
* @addtogroup EQOS_TxDesc Transmit Descriptors bit fields
*
* @brief These macros are used to check the value in specific bit fields of
* the descriptor. The fields in the descriptor are mapped as
* defined in the HW manual
* @{
*/
#define TDES2_IOC OSI_BIT(31)
#define TDES2_MSS_MASK 0x3FFFU
#define TDES3_OWN OSI_BIT(31)
#define TDES3_CTXT OSI_BIT(30)
#define TDES3_TCMSSV OSI_BIT(26)
#define TDES3_FD OSI_BIT(29)
#define TDES3_LD OSI_BIT(28)
#define TDES3_TSE OSI_BIT(18)
#define TDES3_HW_CIC_ALL (OSI_BIT(16) | OSI_BIT(17))
#define TDES3_HW_CIC_IP_ONLY (OSI_BIT(16))
#define TDES3_VT_MASK 0xFFFFU
#define TDES3_THL_MASK 0xFU
#define TDES3_TPL_MASK 0x3FFFFU
#define TDES3_PL_MASK 0x7FFFU
#define TDES3_THL_SHIFT 19U
#define TDES3_VLTV OSI_BIT(16)
#define TDES3_TTSS OSI_BIT(17)
/* Tx Errors */
#define TDES3_IP_HEADER_ERR OSI_BIT(0)
#define TDES3_UNDER_FLOW_ERR OSI_BIT(2)
#define TDES3_EXCESSIVE_DEF_ERR OSI_BIT(3)
#define TDES3_EXCESSIVE_COL_ERR OSI_BIT(8)
#define TDES3_LATE_COL_ERR OSI_BIT(9)
#define TDES3_NO_CARRIER_ERR OSI_BIT(10)
#define TDES3_LOSS_CARRIER_ERR OSI_BIT(11)
#define TDES3_PL_CHK_SUM_ERR OSI_BIT(12)
#define TDES3_PKT_FLUSH_ERR OSI_BIT(13)
#define TDES3_JABBER_TIMEO_ERR OSI_BIT(14)
/* VTIR = 0x2 (Insert a VLAN tag with the tag value programmed in the
* MAC_VLAN_Incl register or context descriptor.)
*/
#define TDES2_VTIR ((nveu32_t)0x2 << 14U)
#define TDES2_TTSE ((nveu32_t)0x1 << 30U)
/** @} */
/** Error Summary bits for Transmitted packet */
#define TDES3_ES_BITS (TDES3_IP_HEADER_ERR | \
TDES3_UNDER_FLOW_ERR | \
TDES3_EXCESSIVE_DEF_ERR | \
TDES3_EXCESSIVE_COL_ERR | \
TDES3_LATE_COL_ERR | \
TDES3_NO_CARRIER_ERR | \
TDES3_LOSS_CARRIER_ERR | \
TDES3_PL_CHK_SUM_ERR | \
TDES3_PKT_FLUSH_ERR | \
TDES3_JABBER_TIMEO_ERR)
#endif /* OSI_DMA_TXRX_H */
#endif /* INCLUDED_OSI_DMA_TXRX_H */

205
osi/common/common.h Normal file
View File

@@ -0,0 +1,205 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef INCLUDED_COMMON_H
#define INCLUDED_COMMON_H
#include <osi_common.h>
/**
* @brief osi_lock_init - Initialize lock to unlocked state.
*
* @note
* Algorithm:
* - Set lock to unlocked state.
*
* @param[in] lock - Pointer to lock to be initialized
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*/
static inline void osi_lock_init(nveu32_t *lock)
{
*lock = OSI_UNLOCKED;
}
/**
* @brief osi_lock_irq_enabled - Spin lock. Busy loop till lock is acquired.
*
* @note
* Algorithm:
* - Atomic compare and swap operation till lock is held.
*
* @param[in] lock - Pointer to lock to be acquired.
*
* @note
* - Does not disable irq. Do not call this API to acquire any
* lock that is shared between top/bottom half. It will result in deadlock.
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
static inline void osi_lock_irq_enabled(nveu32_t *lock)
{
/* __sync_val_compare_and_swap(lock, old value, new value) returns the
* old value if successful.
*/
while (__sync_val_compare_and_swap(lock, OSI_UNLOCKED, OSI_LOCKED) !=
OSI_UNLOCKED) {
/* Spinning.
* Will deadlock if any ISR tried to lock again.
*/
}
}
/**
* @brief osi_unlock_irq_enabled - Release lock.
*
* @note
* Algorithm:
* - Atomic compare and swap operation to release lock.
*
* @param[in] lock - Pointer to lock to be released.
*
* @note
* - Does not disable irq. Do not call this API to release any
* lock that is shared between top/bottom half.
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
static inline void osi_unlock_irq_enabled(nveu32_t *lock)
{
if (__sync_val_compare_and_swap(lock, OSI_LOCKED, OSI_UNLOCKED) !=
OSI_LOCKED) {
/* Do nothing. Already unlocked */
}
}
/**
* @brief osi_readl - Read a memory mapped register.
*
* @param[in] addr: Memory mapped address.
*
* @pre Physical address has to be memory mapped.
*
* @return Data from memory mapped register - success.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*/
static inline nveu32_t osi_readl(void *addr)
{
return *(volatile nveu32_t *)addr;
}
/**
* @brief osi_writel - Write to a memory mapped register.
*
* @param[in] val: Value to be written.
* @param[in] addr: Memory mapped address.
*
* @pre Physical address has to be memory mapped.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
*/
static inline void osi_writel(nveu32_t val, void *addr)
{
*(volatile nveu32_t *)addr = val;
}
/**
* @brief is_valid_mac_version - Check if read MAC IP is valid or not.
*
* @param[in] mac_ver: MAC version read.
*
* @note MAC has to be out of reset.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*
* @retval 0 - for not Valid MAC
* @retval 1 - for Valid MAC
*/
static inline nve32_t is_valid_mac_version(nveu32_t mac_ver)
{
if ((mac_ver == OSI_EQOS_MAC_4_10) ||
(mac_ver == OSI_EQOS_MAC_5_00) ||
(mac_ver == OSI_EQOS_MAC_5_10)) {
return 1;
}
return 0;
}
/**
* @brief osi_update_stats_counter - update value by increment passed
* as parameter
*
* @note
* Algorithm:
* - Check for boundary and return sum
*
* @param[in] last_value: last value of stat counter
* @param[in] incr: increment value
*
* @note Input parameter should be only nveu64_t type
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @return nveu64_t value
*/
static inline nveu64_t osi_update_stats_counter(nveu64_t last_value,
nveu64_t incr)
{
nveu64_t temp = last_value + incr;
if (temp < last_value) {
/* Stats overflow, so reset it to zero */
return 0UL;
}
return temp;
}
#endif

1
osi/common/eqos_common.c
View File

@@ -21,6 +21,7 @@
*/
#include "eqos_common.h"
#include "../osi/common/common.h"
nveul64_t eqos_get_systime_from_mac(void *addr)
{

6
osi/common/eqos_common.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef EQOS_COMMON_H
#define EQOS_COMMON_H
#ifndef INCLUDED_EQOS_COMMON_H
#define INCLUDED_EQOS_COMMON_H
#include <local_common.h>
@@ -80,4 +80,4 @@ nveul64_t eqos_get_systime_from_mac(void *addr);
* @retval OSI_DISABLE otherwise.
*/
nveu32_t eqos_is_mac_enabled(void *addr);
#endif /* EQOS_COMMON_H */
#endif /* INCLUDED_EQOS_COMMON_H */

2
osi/common/osi_common.c
View File

@@ -22,7 +22,7 @@
#include <osd.h>
#include "eqos_common.h"
#include "local_common.h"
#include "../osi/common/common.h"
void common_get_hw_features(void *base, struct osi_hw_features *hw_feat)
{

2
osi/common/type.h
View File

@@ -40,4 +40,4 @@ typedef my_int8_t nve8_t;
typedef my_uint8_t nveu8_t;
typedef my_ulint_64 nveul64_t;
typedef my_uint64_t nveu64_t;
#endif
#endif /* INCLUDED_TYPE_H */

8
osi/core/eqos_core.c
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <osi_common.h>
#include "../osi/common/common.h"
#include <osi_core.h>
#include <osd.h>
#include "eqos_core.h"
@@ -2673,7 +2673,7 @@ static nve32_t eqos_config_l4_filters(
* equal to zero.
*
* @param[in] osi_core: OSI core private data structure.
* @param[inout] mac_tcr: Address to store time stamp control register read
* @param[in, out] mac_tcr: Address to store time stamp control register read
* value
*
* @pre MAC should be initialized and started. see osi_start_mac()
@@ -2785,7 +2785,7 @@ static nve32_t eqos_set_systime_to_mac(
* equal to zero.
*
* @param[in] osi_core: OSI core private data structure.
* @param[inout] mac_tcr: Address to store time stamp control register read
* @param[in, out] mac_tcr: Address to store time stamp control register read
* value
*
* @pre MAC should be initialized and started. see osi_start_mac()
@@ -2888,7 +2888,7 @@ static nve32_t eqos_config_addend(struct osi_core_priv_data *const osi_core,
* equal to zero.
*
* @param[in] osi_core: OSI core private data structure.
* @param[inout] mac_tcr: Address to store time stamp control register read
* @param[in, out] mac_tcr: Address to store time stamp control register read
* value
*
* @pre MAC should be initialized and started. see osi_start_mac()

6
osi/core/eqos_core.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef EQOS_CORE_H_
#define EQOS_CORE_H_
#ifndef INCLUDED_EQOS_CORE_H
#define INCLUDED_EQOS_CORE_H
/**
* @addtogroup EQOS-FC Flow Control Threshold Macros
@@ -622,4 +622,4 @@ struct core_func_safety {
#define EQOS_MAX_BAK_IDX ((EQOS_PAD_AUTO_CAL_CFG_BAK_IDX + 1U))
#endif /* !OSI_STRIPPED_LIB */
/** @} */
#endif
#endif /* INCLUDED_EQOS_CORE_H */

2
osi/core/eqos_mmc.c
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <osi_common.h>
#include "../osi/common/common.h"
#include <osi_core.h>
#include <osd.h>
#include "eqos_mmc.h"

6
osi/core/eqos_mmc.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef EQOS_MMC_H_
#define EQOS_MMC_H_
#ifndef INCLUDED_EQOS_MMC_H
#define INCLUDED_EQOS_MMC_H
/**
* @addtogroup EQOS-MMC MMC HW register offsets
@@ -117,4 +117,4 @@
void eqos_read_mmc(struct osi_core_priv_data *osi_core);
void eqos_reset_mmc(struct osi_core_priv_data *osi_core);
#endif
#endif /* INCLUDED_EQOS_MMC_H */

2
osi/dma/eqos_dma.c
View File

@@ -20,7 +20,7 @@
* DEALINGS IN THE SOFTWARE.
*/
#include <osi_common.h>
#include "../osi/common/common.h"
#include "osi_dma_local.h"
#include "eqos_dma.h"
#include "../osi/common/type.h"

6
osi/dma/eqos_dma.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef EQOS_DMA_H_
#define EQOS_DMA_H_
#ifndef INCLUDED_EQOS_DMA_H
#define INCLUDED_EQOS_DMA_H
/**
* @addtogroup EQOS AXI Clock defines
@@ -189,4 +189,4 @@ void *eqos_get_dma_safety_config(void);
* @returns Pointer to DMA channel operations structure
*/
struct osi_dma_chan_ops *eqos_get_dma_chan_ops(void);
#endif
#endif /* INCLUDED_EQOS_DMA_H */

126
osi/dma/hw_desc.h Normal file
View File

@@ -0,0 +1,126 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef INCLUDED_HW_DESC_H
#define INCLUDED_HW_DESC_H
/**
* @addtogroup EQOS_RxDesc Receive Descriptors bit fields
*
* @brief These macros are used to check the value in specific bit fields of
* the descriptor. The fields in the descriptor are mapped as
* defined in the HW manual
* @{
*/
#define RDES3_OWN OSI_BIT(31)
#define RDES3_CTXT OSI_BIT(30)
#define RDES3_IOC OSI_BIT(30)
#define RDES3_B1V OSI_BIT(24)
#define RDES3_LD OSI_BIT(28)
#define RDES3_FD OSI_BIT(29)
#define RDES3_ERR_CRC OSI_BIT(24)
#define RDES3_ERR_GP OSI_BIT(23)
#define RDES3_ERR_WD OSI_BIT(22)
#define RDES3_ERR_ORUN OSI_BIT(21)
#define RDES3_ERR_RE OSI_BIT(20)
#define RDES3_ERR_DRIB OSI_BIT(19)
#define RDES3_PKT_LEN 0x00007fffU
#define RDES3_LT (OSI_BIT(16) | OSI_BIT(17) | OSI_BIT(18))
#define RDES3_LT_VT OSI_BIT(18)
#define RDES3_LT_DVT (OSI_BIT(16) | OSI_BIT(18))
#define RDES3_RS0V OSI_BIT(25)
#define RDES3_RS1V OSI_BIT(26)
#define RDES0_OVT 0x0000FFFFU
#define RDES1_TSA OSI_BIT(14)
#define RDES1_TD OSI_BIT(15)
#define RDES1_IPCE OSI_BIT(7)
#define RDES1_IPCB OSI_BIT(6)
#define RDES1_IPV6 OSI_BIT(5)
#define RDES1_IPV4 OSI_BIT(4)
#define RDES1_IPHE OSI_BIT(3)
#define RDES1_PT_TCP OSI_BIT(1)
#define RDES1_PT_UDP OSI_BIT(0)
/** @} */
/** Error Summary bits for Received packet */
#define RDES3_ES_BITS \
(RDES3_ERR_CRC | RDES3_ERR_GP | RDES3_ERR_WD | \
RDES3_ERR_ORUN | RDES3_ERR_RE | RDES3_ERR_DRIB)
/**
* @addtogroup EQOS_TxDesc Transmit Descriptors bit fields
*
* @brief These macros are used to check the value in specific bit fields of
* the descriptor. The fields in the descriptor are mapped as
* defined in the HW manual
* @{
*/
#define TDES2_IOC OSI_BIT(31)
#define TDES2_MSS_MASK 0x3FFFU
#define TDES3_OWN OSI_BIT(31)
#define TDES3_CTXT OSI_BIT(30)
#define TDES3_TCMSSV OSI_BIT(26)
#define TDES3_FD OSI_BIT(29)
#define TDES3_LD OSI_BIT(28)
#define TDES3_TSE OSI_BIT(18)
#define TDES3_HW_CIC_ALL (OSI_BIT(16) | OSI_BIT(17))
#define TDES3_HW_CIC_IP_ONLY (OSI_BIT(16))
#define TDES3_VT_MASK 0xFFFFU
#define TDES3_THL_MASK 0xFU
#define TDES3_TPL_MASK 0x3FFFFU
#define TDES3_PL_MASK 0x7FFFU
#define TDES3_THL_SHIFT 19U
#define TDES3_VLTV OSI_BIT(16)
#define TDES3_TTSS OSI_BIT(17)
/* Tx Errors */
#define TDES3_IP_HEADER_ERR OSI_BIT(0)
#define TDES3_UNDER_FLOW_ERR OSI_BIT(2)
#define TDES3_EXCESSIVE_DEF_ERR OSI_BIT(3)
#define TDES3_EXCESSIVE_COL_ERR OSI_BIT(8)
#define TDES3_LATE_COL_ERR OSI_BIT(9)
#define TDES3_NO_CARRIER_ERR OSI_BIT(10)
#define TDES3_LOSS_CARRIER_ERR OSI_BIT(11)
#define TDES3_PL_CHK_SUM_ERR OSI_BIT(12)
#define TDES3_PKT_FLUSH_ERR OSI_BIT(13)
#define TDES3_JABBER_TIMEO_ERR OSI_BIT(14)
/* VTIR = 0x2 (Insert a VLAN tag with the tag value programmed in the
* MAC_VLAN_Incl register or context descriptor.)
*/
#define TDES2_VTIR ((nveu32_t)0x2 << 14U)
#define TDES2_TTSE ((nveu32_t)0x1 << 30U)
/** @} */
/** Error Summary bits for Transmitted packet */
#define TDES3_ES_BITS (TDES3_IP_HEADER_ERR | \
TDES3_UNDER_FLOW_ERR | \
TDES3_EXCESSIVE_DEF_ERR | \
TDES3_EXCESSIVE_COL_ERR | \
TDES3_LATE_COL_ERR | \
TDES3_NO_CARRIER_ERR | \
TDES3_LOSS_CARRIER_ERR | \
TDES3_PL_CHK_SUM_ERR | \
TDES3_PKT_FLUSH_ERR | \
TDES3_JABBER_TIMEO_ERR)
#endif /* INCLUDED_HW_DESC_H */

1
osi/dma/osi_dma.c
View File

@@ -23,6 +23,7 @@
#include "osi_dma_local.h"
#include <osd.h>
#include <local_common.h>
#include "hw_desc.h"
nve32_t osi_init_dma_ops(struct osi_dma_priv_data *osi_dma)
{

6
osi/dma/osi_dma_local.h
View File

@@ -21,8 +21,8 @@
*/
#ifndef OSI_DMA_LOCAL_H
#define OSI_DMA_LOCAL_H
#ifndef INCLUDED_OSI_DMA_LOCAL_H
#define INCLUDED_OSI_DMA_LOCAL_H
#include <osi_dma.h>
#include "eqos_dma.h"
@@ -65,4 +65,4 @@ nve32_t dma_desc_init(struct osi_dma_priv_data *osi_dma);
#define BOOLEAN_FALSE (0U != 0U)
#define L32(data) ((data) & 0xFFFFFFFFU)
#define H32(data) (((data) & 0xFFFFFFFF00000000UL) >> 32UL)
#endif /* OSI_DMA_LOCAL_H */
#endif /* INCLUDED_OSI_DMA_LOCAL_H */

10
osi/dma/osi_dma_txrx.c
View File

@@ -24,6 +24,7 @@
#include "osi_dma_local.h"
#include <osi_dma_txrx.h>
#include "../osi/common/type.h"
#include "hw_desc.h"
/**
* @brief get_rx_csum - Get the Rx checksum from descriptor if valid
@@ -223,8 +224,17 @@ static nve32_t get_rx_hwstamp(struct osi_dma_priv_data *osi_dma,
return ret;
}
if (OSI_NSEC_PER_SEC > (OSI_ULLONG_MAX / context_desc->rdes1)) {
/* Will not hit this case */
} else if ((OSI_ULLONG_MAX -
(context_desc->rdes1 * OSI_NSEC_PER_SEC)) <
context_desc->rdes0) {
/* Will not hit this case */
} else {
rx_pkt_cx->ns = context_desc->rdes0 +
(OSI_NSEC_PER_SEC * context_desc->rdes1);
}
if (rx_pkt_cx->ns < context_desc->rdes0) {
/* Will not hit this case */
return -1;