mirror of
git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
synced 2025-12-24 02:22:16 +03:00
nvethernetrm: mgbe: Add XDCS support
Enable multiple DMA Channels routing support for MC/BC MAC Address with XDCS. Bug 200565911 Change-Id: I7c9f9347361dd72e68696846a0a59e2e241e20c9 Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
This commit is contained in:
committed by
Bhadram Varka
parent
b5a12c85e6
commit
57847505ed
@@ -274,6 +274,8 @@ struct osi_filter {
|
||||
nveu32_t addr_mask;
|
||||
/** src_dest: SA(1) or DA(0) */
|
||||
nveu32_t src_dest;
|
||||
/** indicates one hot encoded DMA receive channels to program */
|
||||
nveu32_t dma_chansel;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -1000,6 +1002,8 @@ struct osi_core_priv_data {
|
||||
unsigned int fpe_ready;
|
||||
/** TSN stats counters */
|
||||
struct osi_tsn_stats tsn_stats;
|
||||
/** MC packets Multiple DMA channel selection flags */
|
||||
nveu32_t mc_dmasel;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
Reference in New Issue
Block a user