diff --git a/osi/core/core_common.c b/osi/core/core_common.c index 8b93162..c79e39e 100644 --- a/osi/core/core_common.c +++ b/osi/core/core_common.c @@ -196,6 +196,24 @@ fail: } +nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core, + const nveu32_t qinx) +{ + void *addr = osi_core->base; + nveu32_t tx_op_mode_val = 0U; + nveu32_t value; + const nveu32_t tx_op_mode[2] = { EQOS_MTL_CHX_TX_OP_MODE(qinx), + MGBE_MTL_CHX_TX_OP_MODE(qinx)}; + + /* Read Tx Q Operating Mode Register and flush TxQ */ + value = osi_readla(osi_core, ((nveu8_t *)addr + tx_op_mode[osi_core->mac])); + value |= MTL_QTOMR_FTQ; + osi_writela(osi_core, value, ((nveu8_t *)addr + tx_op_mode[osi_core->mac])); + + /* Poll Until FTQ bit resets for Successful Tx Q flush */ + return poll_check(osi_core, ((nveu8_t *)addr + tx_op_mode[osi_core->mac]), + MTL_QTOMR_FTQ, &tx_op_mode_val); +} /** * @brief hw_est_read - indirect read the GCL to Software own list diff --git a/osi/core/core_common.h b/osi/core/core_common.h index 3dd0efa..c0c7185 100644 --- a/osi/core/core_common.h +++ b/osi/core/core_common.h @@ -39,6 +39,7 @@ #define MTL_EST_CONTROL_EEST OSI_BIT(0) #define MTL_EST_STATUS_SWOL OSI_BIT(7) #define DMA_MODE_SWR OSI_BIT(0) +#define MTL_QTOMR_FTQ OSI_BIT(0) /** * @addtogroup typedef related info @@ -64,4 +65,6 @@ void hw_start_mac(struct osi_core_priv_data *const osi_core); void hw_stop_mac(struct osi_core_priv_data *const osi_core); nve32_t hw_set_mode(struct osi_core_priv_data *const osi_core, const nve32_t mode); nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t speed); +nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core, + const nveu32_t qinx); #endif /* INCLUDED_CORE_COMMON_H */ diff --git a/osi/core/core_local.h b/osi/core/core_local.h index 8dc99af..f5983c7 100644 --- a/osi/core/core_local.h +++ b/osi/core/core_local.h @@ -203,9 +203,6 @@ struct core_ops { /** Called periodically to read and validate safety critical * registers against last written value */ nve32_t (*validate_regs)(struct osi_core_priv_data *const osi_core); - /** Called to flush MTL Tx queue */ - nve32_t (*flush_mtl_tx_queue)(struct osi_core_priv_data *const osi_core, - const nveu32_t qinx); /** Called to set av parameter */ nve32_t (*set_avb_algorithm)(struct osi_core_priv_data *const osi_core, const struct osi_core_avb_algorithm *const avb); diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c index f0fd3b4..b4d95bd 100644 --- a/osi/core/eqos_core.c +++ b/osi/core/eqos_core.c @@ -857,81 +857,6 @@ calibration_failed: } #endif /* UPDATED_PAD_CAL */ -/** - * @brief eqos_flush_mtl_tx_queue - Flush MTL Tx queue - * - * @note - * Algorithm: - * - Validate qinx for maximum value of OSI_EQOS_MAX_NUM_QUEUES and return -1 if fails. - * - Configure EQOS_MTL_CHX_TX_OP_MODE to flush corresponding MTL queue. - * - Wait on EQOS_MTL_QTOMR_FTQ_LPOS bit set for a loop of 1000 with a sleep of - * 1 milli second between itertions. - * - return 0 if EQOS_MTL_QTOMR_FTQ_LPOS is set else -1. - * - SWUD_ID: ETHERNET_NVETHERNETRM_006_2 - * - * @param[in] osi_core: OSI core private data structure. Used param base, osd_ops.msleep. - * @param[in] qinx: MTL queue index. Max value is OSI_EQOS_MAX_NUM_QUEUES-1. - * - * @note - * - MAC should out of reset and clocks enabled. - * - hw core initialized. see osi_hw_core_init(). - * - * @note - * API Group: - * - Initialization: Yes - * - Run time: No - * - De-initialization: No - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t eqos_flush_mtl_tx_queue( - struct osi_core_priv_data *const osi_core, - const nveu32_t qinx) -{ - void *addr = osi_core->base; - nveu32_t retry = RETRY_COUNT; - nveu32_t count; - nveu32_t value; - nve32_t cond = COND_NOT_MET; - - if (qinx >= OSI_EQOS_MAX_NUM_QUEUES) { - OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID, - "flush_mtl_tx_queue: invalid input\n", 0ULL); - return -1; - } - - /* Read Tx Q Operating Mode Register and flush TxQ */ - value = osi_readla(osi_core, (nveu8_t *)addr + - EQOS_MTL_CHX_TX_OP_MODE(qinx)); - value |= EQOS_MTL_QTOMR_FTQ; - eqos_core_safety_writel(osi_core, value, (nveu8_t *)addr + - EQOS_MTL_CHX_TX_OP_MODE(qinx), - EQOS_MTL_CH0_TX_OP_MODE_IDX + qinx); - - /* Poll Until FTQ bit resets for Successful Tx Q flush */ - count = 0; - while (cond == COND_NOT_MET) { - if (count > retry) { - OSI_CORE_ERR(OSI_NULL, OSI_LOG_ARG_INVALID, - "Poll FTQ bit timeout\n", 0ULL); - return -1; - } - - count++; - osi_core->osd_ops.msleep(1); - - value = osi_readla(osi_core, (nveu8_t *)addr + - EQOS_MTL_CHX_TX_OP_MODE(qinx)); - - if ((value & EQOS_MTL_QTOMR_FTQ_LPOS) == 0U) { - cond = COND_MET; - } - } - - return 0; -} - /** * @brief update_ehfc_rfa_rfd - Update EHFC, RFD and RSA values * @@ -1080,7 +1005,7 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t qinx, nveu32_t value = 0; nve32_t ret = 0; - ret = eqos_flush_mtl_tx_queue(osi_core, qinx); + ret = hw_flush_mtl_tx_queue(osi_core, qinx); if (ret < 0) { return ret; } @@ -6655,7 +6580,6 @@ void eqos_init_core_ops(struct core_ops *ops) ops->config_arp_offload = eqos_config_arp_offload; ops->config_ptp_offload = eqos_config_ptp_offload; ops->validate_regs = eqos_validate_core_regs; - ops->flush_mtl_tx_queue = eqos_flush_mtl_tx_queue; ops->set_avb_algorithm = eqos_set_avb_algorithm; ops->get_avb_algorithm = eqos_get_avb_algorithm; ops->config_vlan_filtering = eqos_config_vlan_filtering; diff --git a/osi/core/eqos_core.h b/osi/core/eqos_core.h index 7c46457..55cbf42 100644 --- a/osi/core/eqos_core.h +++ b/osi/core/eqos_core.h @@ -228,7 +228,6 @@ #define EQOS_MMC_CNTRL_RSTONRD OSI_BIT(2) #define EQOS_MMC_CNTRL_CNTPRST OSI_BIT(4) #define EQOS_MMC_CNTRL_CNTPRSTLVL OSI_BIT(5) -#define EQOS_MTL_QTOMR_FTQ OSI_BIT(0) #define EQOS_MTL_TSF OSI_BIT(1) #define EQOS_MTL_TXQEN OSI_BIT(3) #define EQOS_MTL_RSF OSI_BIT(5) @@ -280,7 +279,6 @@ #define EQOS_MAC_RQC1R_PTPQ_SHIFT 4U #define EQOS_MAC_PPS_CTL_PPSCTRL0 (OSI_BIT(3) | OSI_BIT(2) |\ OSI_BIT(1) | OSI_BIT(0)) -#define EQOS_MTL_QTOMR_FTQ_LPOS OSI_BIT(0) #define EQOS_DMA_ISR_MTLIS OSI_BIT(16) #define EQOS_DMA_ISR_MACIS OSI_BIT(17) diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c index ef820f5..65b7159 100644 --- a/osi/core/mgbe_core.c +++ b/osi/core/mgbe_core.c @@ -1637,60 +1637,6 @@ static int mgbe_config_ptp_rxq(struct osi_core_priv_data *const osi_core, return 0; } -/** - * @brief mgbe_flush_mtl_tx_queue - Flush MTL Tx queue - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] qinx: MTL queue index. - * - * @note 1) MAC should out of reset and clocks enabled. - * 2) hw core initialized. see osi_hw_core_init(). - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t mgbe_flush_mtl_tx_queue( - struct osi_core_priv_data *const osi_core, - const nveu32_t qinx) -{ - void *addr = osi_core->base; - nveu32_t retry = 1000; - nveu32_t count; - nveu32_t value; - nve32_t cond = 1; - - if (qinx >= OSI_MGBE_MAX_NUM_QUEUES) { - return -1; - } - - /* Read Tx Q Operating Mode Register and flush TxQ */ - value = osi_readla(osi_core, (nveu8_t *)addr + - MGBE_MTL_CHX_TX_OP_MODE(qinx)); - value |= MGBE_MTL_QTOMR_FTQ; - osi_writela(osi_core, value, (nveu8_t *)addr + - MGBE_MTL_CHX_TX_OP_MODE(qinx)); - - /* Poll Until FTQ bit resets for Successful Tx Q flush */ - count = 0; - while (cond == 1) { - if (count > retry) { - return -1; - } - - count++; - - value = osi_readla(osi_core, (nveu8_t *)addr + - MGBE_MTL_CHX_TX_OP_MODE(qinx)); - if ((value & MGBE_MTL_QTOMR_FTQ_LPOS) == OSI_NONE) { - cond = 0; - } else { - osi_core->osd_ops.msleep(1); - } - } - - return 0; -} - /** * @brief mgbe_config_mac_loopback - Configure MAC to support loopback * @@ -2266,7 +2212,7 @@ static nve32_t mgbe_configure_mtl_queue(nveu32_t qinx, * Setting related to CBS will come here for TC. * default: 0x0 SP */ - ret = mgbe_flush_mtl_tx_queue(osi_core, qinx); + ret = hw_flush_mtl_tx_queue(osi_core, qinx); if (ret < 0) { return ret; } @@ -6044,7 +5990,6 @@ void mgbe_init_core_ops(struct core_ops *ops) ops->handle_common_intr = mgbe_handle_common_intr; ops->pad_calibrate = mgbe_pad_calibrate; ops->set_mdc_clk_rate = mgbe_set_mdc_clk_rate; - ops->flush_mtl_tx_queue = mgbe_flush_mtl_tx_queue; ops->config_mac_loopback = mgbe_config_mac_loopback; ops->set_avb_algorithm = mgbe_set_avb_algorithm; ops->get_avb_algorithm = mgbe_get_avb_algorithm, diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h index 4e0405c..9676fc4 100644 --- a/osi/core/mgbe_core.h +++ b/osi/core/mgbe_core.h @@ -385,8 +385,6 @@ #define MGBE_MTL_TX_OP_MODE_TXQEN (OSI_BIT(3) | OSI_BIT(2)) #define MGBE_MTL_TX_OP_MODE_TXQEN_SHIFT 2U #define MGBE_MTL_CHX_TX_OP_MODE_Q2TC_SH 8U -#define MGBE_MTL_QTOMR_FTQ OSI_BIT(0) -#define MGBE_MTL_QTOMR_FTQ_LPOS OSI_BIT(0) #define MGBE_MTL_TSF OSI_BIT(1) #define MGBE_MTL_TXQEN OSI_BIT(3) #define MGBE_MTL_RSF OSI_BIT(5)