nv-tegra-mirror/nvethernetrm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/kernel/nvethernetrm.git synced 2025-12-22 09:12:10 +03:00
Code Issues Packages Projects Releases Wiki Activity

xpcs: Revert RX EQ training changes

Browse Source 
Revert RX EQ training changes done via SW override method
This will be taken care along with UPHY RX lane bringup through
SW override method

Bug 5087758

Change-Id: If5d0cf86b60324782aa430f55e759e934e77ba35
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3399510
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Revanth Kumar Uppala
2025-07-04 08:28:38 +00:00
committed by mobile promotions
parent fddedb16a8
commit 6f0373c303
2 changed files with 0 additions and 172 deletions
Download Patch File Download Diff File Expand all files Collapse all files

136
osi/core/xpcs.c
View File

@@ -575,136 +575,6 @@ fail:
return ret; return ret;
} }
/**
* @brief xpcs_rx_eq_sw_override - Execute RX EQ training
*
* Algorithm: This routine executes RX EQ training through
* sw override method.
*
* @param[in] osi_core: OSI core data structure.
*
* @retval 0 on success
* @retval -1 on failure.
*/
nve32_t xpcs_rx_eq_sw_override(struct osi_core_priv_data *osi_core)
{
nveu32_t val = 0;
nve32_t ret = 0;
nveu32_t count;
nve32_t cond;
nveu32_t rx_eq_retry = RETRY_COUNT;
osi_writela(osi_core, XPCS_WRAP_UPHY_RX_CTRL_12_0_SLEEP_DLY,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_12_0);
val = osi_readla(osi_core,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_12_0);
if (val != XPCS_WRAP_UPHY_RX_CTRL_12_0_SLEEP_DLY) {
ret = -1;
goto fail;
}
val = osi_readla(osi_core,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
val |= XPCS_WRAP_UPHY_RX_CTRL_0_0_PRE_RX_EQ_MASK_1;
val &= ~(XPCS_WRAP_UPHY_RX_CTRL_0_0_PRE_RX_EQ_MASK_2);
osi_writela(osi_core, val,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
val = osi_readla(osi_core,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
/* Enable RX_SW_OVRD */
val |= XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_SW_OVRD;
osi_writela(osi_core, val,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
/* wait 1 second */
osi_core->osd_ops.usleep(OSI_DELAY_1000000US);
val = osi_readla(osi_core,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
/* RX_EQ_RESET */
val |= XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_EQ_RESET;
osi_writela(osi_core, val,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
cond = COND_NOT_MET;
count = 0;
while (cond == COND_NOT_MET) {
val = osi_readla(osi_core,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
if ((val & XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_EQ_RESET) != 0) {
if (count > rx_eq_retry) {
ret = -1;
OSI_CORE_INFO(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"RX_EQ_RESET failed\n", 0ULL);
goto fail; // RX_EQ_RESET failed
}
count++;
osi_core->osd_ops.udelay(OSI_DELAY_2US);
} else {
cond = COND_MET;
}
}
/* wait 1 second */
osi_core->osd_ops.usleep(OSI_DELAY_1000000US);
/* RX_EQ_TRAIN_EN */
val |= XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_EQ_TRAIN_EN;
osi_writela(osi_core, val,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
/* Poll until bit 11 clears or timeout */
cond = COND_NOT_MET;
count = 0;
while (cond == COND_NOT_MET) {
val = osi_readla(osi_core,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
if ((val & XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_EQ_TRAIN_EN) != 0) {
if (count > rx_eq_retry) {
ret = -1;
OSI_CORE_INFO(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"RX_EQ_TRAIN_EN failed\n", 0ULL);
goto fail; // RX_EQ_TRAIN_EN failed
}
count++;
osi_core->osd_ops.usleep(OSI_DELAY_500US);
} else {
cond = COND_MET;
}
}
/* Disable RX_SW_OVRD */
val &= ~XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_SW_OVRD;
osi_writela(osi_core, val,
(nveu8_t *)osi_core->xpcs_base +
T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0);
/* wait 2 micro seconds */
osi_core->osd_ops.udelay(OSI_DELAY_2US);
fail:
return ret;
}
/** /**
* @brief xpcs_lane_bring_up - Bring up UPHY Tx/Rx lanes * @brief xpcs_lane_bring_up - Bring up UPHY Tx/Rx lanes
* *
@@ -900,12 +770,6 @@ step10:
"PCS block lock SUCCESS\n", 0ULL); "PCS block lock SUCCESS\n", 0ULL);
} }
if (osi_core->pcs_rx_eq_sw_ovrd_en == OSI_RX_EQ_SW_OVRD) {
if (xpcs_rx_eq_sw_override(osi_core)) {
ret = -1;
}
}
fail: fail:
return ret; return ret;
} }

36
osi/core/xpcs.h
View File

@@ -71,8 +71,6 @@
#define T26X_XPCS_WRAP_UPHY_RX_CTRL_2 0x8040 #define T26X_XPCS_WRAP_UPHY_RX_CTRL_2 0x8040
#define T26X_XPCS_WRAP_UPHY_RX_CTRL_3 0x8044 #define T26X_XPCS_WRAP_UPHY_RX_CTRL_3 0x8044
#define T26X_XPCS_WRAP_UPHY_TIMEOUT_CONTROL_0_0 0x8070 #define T26X_XPCS_WRAP_UPHY_TIMEOUT_CONTROL_0_0 0x8070
#define T26X_XPCS_WRAP_UPHY_RX_CTRL_0_0 0x8034
#define T26X_XPCS_WRAP_UPHY_RX_CTRL_12_0 0x8058
/** @} */ /** @} */
@@ -197,13 +195,6 @@
#define XPCS_SR_PMA_KR_FEC_CTRL_FEC_EN OSI_BIT(0) #define XPCS_SR_PMA_KR_FEC_CTRL_FEC_EN OSI_BIT(0)
#define XPCS_SR_PMA_KR_FEC_CTRL_EN_ERR_IND OSI_BIT(1) #define XPCS_SR_PMA_KR_FEC_CTRL_EN_ERR_IND OSI_BIT(1)
#define XPCS_WRAP_UPHY_RX_CTRL_0_0_PRE_RX_EQ_MASK_1 OSI_BIT(0) | OSI_BIT(10)
#define XPCS_WRAP_UPHY_RX_CTRL_0_0_PRE_RX_EQ_MASK_2 OSI_BIT(4) | OSI_BIT(5) | OSI_BIT(6) | OSI_BIT(7)
#define XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_EQ_TRAIN_EN OSI_BIT(11)
#define XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_EQ_RESET OSI_BIT(12)
#define XPCS_WRAP_UPHY_RX_CTRL_0_0_RX_SW_OVRD OSI_BIT(31)
#define XPCS_WRAP_UPHY_RX_CTRL_12_0_SLEEP_DLY 0x200U
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
#define XPCS_WRAP_INTERRUPT_CONTROL 0x8048 #define XPCS_WRAP_INTERRUPT_CONTROL 0x8048
#define T26X_XPCS_WRAP_INTERRUPT_CONTROL 0x8084 #define T26X_XPCS_WRAP_INTERRUPT_CONTROL 0x8084
@@ -336,31 +327,4 @@ static inline nve32_t xpcs_write_safety(struct osi_core_priv_data *osi_core,
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
return ret; return ret;
} }
/**
* @brief
* Description: Execute RX EQ training through SW Override method.
*
* @param[in] osi_core: A pointer to the osi_core_priv_data structure
* * Range: A non-null pointer to NVETHERNETRM_PIF$osi_core_priv_data structure.
* * Refer NVETHERNETRM_PIF$osi_core_priv_data
*
* @usage
* - Allowed context for the API call
* - Interrupt handler: No
* - Signal handler: No
* - Thread safe: No
* - Async/Sync: Sync
* - Required Privileges: None
* - API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*
* @return
* 0 on success
* -1 on failure
*
*/
nve32_t xpcs_rx_eq_sw_override(struct osi_core_priv_data *osi_core);
#endif /* INCLUDED_XPCS_H_ */ #endif /* INCLUDED_XPCS_H_ */