From 7b29b58c95ae2a38afb2ef0ccb06d1db15cff43e Mon Sep 17 00:00:00 2001 From: Bhadram Varka Date: Wed, 25 Aug 2021 19:30:28 -0700 Subject: [PATCH] Revert "osi: eqos: mgbe: program SID through HV window" This reverts commit b16c09af3b0cd4ba0d068613bb81912df05225fa. Reason for revert: Created regression for AV + L Bug 3358505 Bug 200761024 Change-Id: I31fbd921f9655cd62073918be9d4151f5cc29f8b Signed-off-by: Bhadram Varka Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584378 Reviewed-by: Narayan Reddy Reviewed-by: Srinivas Ramachandran Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions --- include/osi_core.h | 2 -- osi/core/eqos_core.c | 30 ++++++++---------------------- osi/core/eqos_core.h | 15 --------------- osi/core/mgbe_core.c | 15 +-------------- osi/core/mgbe_core.h | 24 ------------------------ 5 files changed, 9 insertions(+), 77 deletions(-) diff --git a/include/osi_core.h b/include/osi_core.h index 60db8ae..d2d920d 100644 --- a/include/osi_core.h +++ b/include/osi_core.h @@ -1145,8 +1145,6 @@ struct core_padctrl { struct osi_core_priv_data { /** Memory mapped base address of MAC IP */ void *base; - /** Memory mapped base address of HV window */ - void *hv_base; /** Memory mapped base address of DMA window of MAC IP */ void *dma_base; /** Memory mapped base address of XPCS IP */ diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c index b2830d4..43739e3 100644 --- a/osi/core/eqos_core.c +++ b/osi/core/eqos_core.c @@ -2113,29 +2113,15 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core, osi_writela(osi_core, EQOS_MMC_CNTRL_CNTRST, (nveu8_t *)osi_core->base + EQOS_MMC_CNTRL); - if (osi_core->use_virtualization == OSI_DISABLE) { - if ((osi_core->hv_base != OSI_NULL) && - (osi_core->mac_ver == OSI_EQOS_MAC_5_30)) { - osi_writela(osi_core, EQOS_5_30_ASID_CTRL_VAL, - (nveu8_t *)osi_core->hv_base + - EQOS_AXI_ASID_CTRL); + /* AXI ASID CTRL for channel 0 to 3 */ + osi_writela(osi_core, EQOS_AXI_ASID_CTRL_VAL, + (nveu8_t *)osi_core->base + EQOS_AXI_ASID_CTRL); - osi_writela(osi_core, EQOS_5_30_ASID1_CTRL_VAL, - (nveu8_t *)osi_core->hv_base + - EQOS_AXI_ASID1_CTRL); - } else { - /* AXI ASID CTRL for channel 0 to 3 */ - osi_writela(osi_core, EQOS_AXI_ASID_CTRL_VAL, - (nveu8_t *)osi_core->base + - EQOS_AXI_ASID_CTRL); - - /* AXI ASID1 CTRL for channel 4 to 7 */ - if (osi_core->mac_ver > OSI_EQOS_MAC_5_00) { - osi_writela(osi_core, EQOS_AXI_ASID1_CTRL_VAL, - (nveu8_t *)osi_core->base + - EQOS_AXI_ASID1_CTRL); - } - } + /* AXI ASID1 CTRL for channel 4 to 7 */ + if (osi_core->mac_ver > OSI_EQOS_MAC_5_00) { + osi_writela(osi_core, EQOS_AXI_ASID1_CTRL_VAL, + (nveu8_t *)osi_core->base + + EQOS_AXI_ASID1_CTRL); } /* Mapping MTL Rx queue and DMA Rx channel */ diff --git a/osi/core/eqos_core.h b/osi/core/eqos_core.h index ce58e8e..02bc699 100644 --- a/osi/core/eqos_core.h +++ b/osi/core/eqos_core.h @@ -492,21 +492,6 @@ (TEGRA_SID_EQOS_CH6) |\ (TEGRA_SID_EQOS_CH5) |\ (TEGRA_SID_EQOS)) -#define EQOS_5_30_SID (nveu32_t)0x3U -#define EQOS_5_30_SID_CH3 ((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_24) -#define EQOS_5_30_SID_CH2 ((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_16) -#define EQOS_5_30_SID_CH1 ((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_8) -#define EQOS_5_30_ASID_CTRL_VAL ((EQOS_5_30_SID_CH3) |\ - (EQOS_5_30_SID_CH2) |\ - (EQOS_5_30_SID_CH1) |\ - (EQOS_5_30_SID)) -#define EQOS_5_30_SID_CH7 ((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_24) -#define EQOS_5_30_SID_CH6 ((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_16) -#define EQOS_5_30_SID_CH5 ((EQOS_5_30_SID) << EQOS_ASID_CTRL_SHIFT_8) -#define EQOS_5_30_ASID1_CTRL_VAL ((EQOS_5_30_SID_CH7) |\ - (EQOS_5_30_SID_CH6) |\ - (EQOS_5_30_SID_CH5) |\ - (EQOS_5_30_SID)) #define EQOS_MMC_INTR_DISABLE 0xFFFFFFFFU /* MAC FPE control/statusOSI_BITmap */ diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c index c7c7366..fb2e54f 100644 --- a/osi/core/mgbe_core.c +++ b/osi/core/mgbe_core.c @@ -3062,20 +3062,7 @@ static void mgbe_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core) } } - if ((osi_core->use_virtualization == OSI_DISABLE) && - (osi_core->hv_base != OSI_NULL)) { - osi_writela(osi_core, MGBE_ASID_CTRL_VAL, - (nveu8_t *)osi_core->hv_base + - MGBE_WRAP_AXI_ASID0_CTRL); - - osi_writela(osi_core, MGBE_ASID1_CTRL_VAL, - (nveu8_t *)osi_core->hv_base + - MGBE_WRAP_AXI_ASID1_CTRL); - - osi_writela(osi_core, MGBE_ASID2_CTRL_VAL, - (nveu8_t *)osi_core->hv_base + - MGBE_WRAP_AXI_ASID2_CTRL); - } + osi_writel(0xD, (nveu8_t *)osi_core->base + 0x8400); } diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h index bf8be2d..b606811 100644 --- a/osi/core/mgbe_core.h +++ b/osi/core/mgbe_core.h @@ -122,9 +122,6 @@ * @brief MGBE Wrapper register offsets * @{ */ -#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400 -#define MGBE_WRAP_AXI_ASID1_CTRL 0x8404 -#define MGBE_WRAP_AXI_ASID2_CTRL 0x8408 #define MGBE_WRAP_COMMON_INTR_ENABLE 0x8704 #define MGBE_WRAP_COMMON_INTR_STATUS 0x8708 #define MGBE_VIRT_INTR_APB_CHX_CNTRL(x) (0x8200U + ((x) * 4U)) @@ -673,27 +670,6 @@ #define MGBE_MAC_EXT_CNF_EIPG 0x1U /* TX timestamp */ #define MGBE_MAC_TSS_TXTSC OSI_BIT(15) -#define MGBE_SID_SHIFT_24 24U -#define MGBE_SID_SHIFT_16 16U -#define MGBE_SID_SHIFT_8 8U -#define MGBE_SID (nveu32_t)0x6U -#define MGBE_SID_CH3 ((MGBE_SID) << MGBE_SID_SHIFT_24) -#define MGBE_SID_CH2 ((MGBE_SID) << MGBE_SID_SHIFT_16) -#define MGBE_SID_CH1 ((MGBE_SID) << MGBE_SID_SHIFT_8) -#define MGBE_ASID_CTRL_VAL ((MGBE_SID_CH3) |\ - (MGBE_SID_CH2) |\ - (MGBE_SID_CH1) |\ - (MGBE_SID)) -#define MGBE_SID_CH7 ((MGBE_SID) << MGBE_SID_SHIFT_24) -#define MGBE_SID_CH6 ((MGBE_SID) << MGBE_SID_SHIFT_16) -#define MGBE_SID_CH5 ((MGBE_SID) << MGBE_SID_SHIFT_8) -#define MGBE_ASID1_CTRL_VAL ((MGBE_SID_CH7) |\ - (MGBE_SID_CH6) |\ - (MGBE_SID_CH5) |\ - (MGBE_SID)) -#define MGBE_SID_CH9 ((MGBE_SID) << MGBE_SID_SHIFT_8) -#define MGBE_ASID2_CTRL_VAL ((MGBE_SID_CH9) |\ - (MGBE_SID)) /** @} */ /**