diff --git a/osi/core/core_common.c b/osi/core/core_common.c
index 2d4e494..1c1e569 100644
--- a/osi/core/core_common.c
+++ b/osi/core/core_common.c
@@ -1435,14 +1435,49 @@ done:
 	return ret;
 }
 
+static nveu32_t speed_index(nve32_t speed)
+{
+	nveu32_t ret;
+
+	switch (speed) {
+	case OSI_SPEED_10:
+		ret = OSI_SPEED_10_INX;
+		break;
+	case OSI_SPEED_100:
+		ret =  OSI_SPEED_100_INX;
+		break;
+	case OSI_SPEED_1000:
+		ret = OSI_SPEED_1000_INX;
+		break;
+	case OSI_SPEED_2500:
+		ret = OSI_SPEED_2500_INX;
+		break;
+	case OSI_SPEED_5000:
+		ret = OSI_SPEED_5000_INX;
+		break;
+	case OSI_SPEED_10000:
+		ret = OSI_SPEED_10000_INX;
+		break;
+	case OSI_SPEED_25000:
+		ret = OSI_SPEED_25000_INX;
+		break;
+	default:
+		ret = OSI_SPEED_10000_INX;
+		break;
+	}
+
+	return ret;
+}
 static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_core,
 					struct osi_fpe_config *const fpe)
 {
 	nveu32_t i = 0U;
+	nveu32_t index = 0;
 	nveu32_t val = 0U;
 	nveu32_t temp = 0U, temp1 = 0U;
 	nveu32_t temp_shift = 0U;
 	nve32_t ret = 0;
+
 	const nveu32_t MTL_FPE_CTS[OSI_MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_CTS,
 						MGBE_MTL_FPE_CTS,
 						MGBE_MTL_FPE_CTS};
@@ -1464,6 +1499,9 @@ static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_cor
 	const nveu32_t MTL_FPE_ADV[OSI_MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_ADV,
 						MGBE_MTL_FPE_ADV,
 						MGBE_MTL_FPE_ADV};
+	const nveu32_t MTL_FPE_HADV_VAL[OSI_SPEED_MAX_INX] = {FPE_1G_HADV, FPE_1G_HADV,
+						FPE_1G_HADV, FPE_10G_HADV, FPE_10G_HADV,
+						FPE_10G_HADV, FPE_25G_HADV};
 
 	val = osi_readla(osi_core, (nveu8_t *)osi_core->base + MTL_FPE_CTS[osi_core->mac]);
 	val &= ~MTL_FPE_CTS_PEC;
@@ -1513,8 +1551,8 @@ static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_cor
 
 	val = osi_readla(osi_core, (nveu8_t *)osi_core->base + (MTL_FPE_ADV[osi_core->mac]));
 	val &= ~MTL_FPE_ADV_HADV_MASK;
-	//(minimum_fragment_size +IPG/EIPG + Preamble) *.8 ~98ns for10G
-	val |= MTL_FPE_ADV_HADV_VAL;
+	index = speed_index(osi_core->speed);
+	val |= MTL_FPE_HADV_VAL[index];
 	osi_writela(osi_core, val, (nveu8_t *)osi_core->base + (MTL_FPE_ADV[osi_core->mac]));
 
 	if (osi_core->mac == OSI_MAC_HW_MGBE) {
diff --git a/osi/core/core_common.h b/osi/core/core_common.h
index 2efc57c..64c3370 100644
--- a/osi/core/core_common.h
+++ b/osi/core/core_common.h
@@ -129,6 +129,32 @@
 #define MAC_RX_FLW_CTRL			0x0090
 #define MAC_RX_FLW_CTRL_RFE		OSI_BIT(0)
 
+/**
+ * @addtogroup FPE HADV register value
+ *
+ * @brief Defines the supported speeds
+ * and the corresponding HADV value for
+ * hardware according to the ASIC recommendations.
+ * The HADV value is a speed-dependent parameter.
+ * The speed index is used to map the HADV
+ * for hardware during initialization.
+ *
+ * @{
+ */
+#define OSI_SPEED_10_INX	0U
+#define OSI_SPEED_100_INX	1U
+#define OSI_SPEED_1000_INX	2U
+#define OSI_SPEED_2500_INX	3U
+#define OSI_SPEED_5000_INX	4U
+#define OSI_SPEED_10000_INX	5U
+#define OSI_SPEED_25000_INX	6U
+#define OSI_SPEED_MAX_INX	7U
+
+#define FPE_1G_HADV			0x380U
+#define FPE_10G_HADV		0x59U
+#define FPE_25G_HADV		0x23U
+/** @} */
+
 #ifdef HSI_SUPPORT
 /**
  * @addtogroup MMC HW register offsets