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nvethernetrm: update OSI_PAUSE_FRAMES_ENABLE macro

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Update OSI_PAUSE_FRAMES_ENABLE as per the updated
DT-bindings.

Bug 3529804

Change-Id: Ice290ef85c370956cec2a7b29cc0b6f82ac39093
Signed-off-by: Diptanshu Jamgade <djamgade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2790122
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Diptanshu Jamgade
2022-10-11 17:23:53 +05:30
committed by Bhadram Varka
parent 1ea653fc42
commit 8bb1b24f59
2 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/osi_common.h
View File

@@ -91,7 +91,7 @@
* @brief EQOS generic helper MACROS. * @brief EQOS generic helper MACROS.
* @{ * @{
*/ */
#define OSI_PAUSE_FRAMES_ENABLE 0U #define OSI_PAUSE_FRAMES_ENABLE 1U
#define OSI_PTP_REQ_CLK_FREQ 250000000U #define OSI_PTP_REQ_CLK_FREQ 250000000U
#define OSI_FLOW_CTRL_DISABLE 0U #define OSI_FLOW_CTRL_DISABLE 0U
#define OSI_ADDRESS_32BIT 0 #define OSI_ADDRESS_32BIT 0

10
include/osi_core.h
View File

@@ -869,7 +869,7 @@ struct core_backup {
*/ */
struct osi_ptp_config { struct osi_ptp_config {
/** PTP filter parameters bit fields. /** PTP filter parameters bit fields.
* *
* Enable Timestamp, Fine Timestamp, 1 nanosecond accuracy * Enable Timestamp, Fine Timestamp, 1 nanosecond accuracy
* are enabled by default. * are enabled by default.
* *
@@ -896,7 +896,7 @@ struct osi_ptp_config {
* Select PTP packets for Taking Snapshots (OSI_BIT(16) + OSI_BIT(17)) * Select PTP packets for Taking Snapshots (OSI_BIT(16) + OSI_BIT(17))
* *
* AV 802.1AS Mode Enable OSI_BIT(28) * AV 802.1AS Mode Enable OSI_BIT(28)
* *
* if ptp_filter is set to Zero then Time stamping is disabled */ * if ptp_filter is set to Zero then Time stamping is disabled */
nveu32_t ptp_filter; nveu32_t ptp_filter;
/** seconds to be updated to MAC */ /** seconds to be updated to MAC */
@@ -1304,7 +1304,7 @@ struct osi_core_priv_data {
nveu32_t mtu; nveu32_t mtu;
/** Ethernet MAC address */ /** Ethernet MAC address */
nveu8_t mac_addr[OSI_ETH_ALEN]; nveu8_t mac_addr[OSI_ETH_ALEN];
/** DT entry to enable(0) or disable(1) pause frame support */ /** DT entry to enable(1) or disable(0) pause frame support */
nveu32_t pause_frames; nveu32_t pause_frames;
/** Current flow control settings */ /** Current flow control settings */
nveu32_t flow_ctrl; nveu32_t flow_ctrl;
@@ -1394,7 +1394,7 @@ struct osi_core_priv_data {
/** /**
* @brief osi_hw_core_init - EQOS MAC, MTL and common DMA initialization. * @brief osi_hw_core_init - EQOS MAC, MTL and common DMA initialization.
* *
* @note * @note
* Algorithm: * Algorithm:
* - Invokes EQOS MAC, MTL and common DMA register init code. * - Invokes EQOS MAC, MTL and common DMA register init code.
@@ -1466,7 +1466,7 @@ nve32_t osi_hw_core_deinit(struct osi_core_priv_data *const osi_core);
/** /**
* @brief osi_common_isr - Common ISR. * @brief osi_common_isr - Common ISR.
* *
* @note * @note
* Algorithm: * Algorithm:
* - Takes care of handling the common interrupts accordingly as per * - Takes care of handling the common interrupts accordingly as per