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osi: T264 VDMA feature and bring up changes

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Bug 4043836

Ported from the change -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896005

Change-Id: Iabbbde0d2733f04bba5d7128e7b8ac5956605424
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3149288
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
This commit is contained in:
Mahesh Patil
2023-03-30 21:55:19 +00:00
committed by mobile promotions
parent d28da6a10b
commit 8c7f7328e8
18 changed files with 1134 additions and 392 deletions
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19
osi/core/common.h
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@@ -45,9 +45,21 @@
#define MAC_CORE_VER_TYPE_MGBE 2U
/**
* @brief Maximum number of supported MAC IP types (EQOS and MGBE)
* @addtogroup MGBE PBL settings.
*
* @brief Values defined for PBL settings
* @{
*/
#define MAX_MAC_IP_TYPES 2U
/* Tx Queue size is 128KB */
#define MGBE_TXQ_SIZE 131072U
/* Rx Queue size is 192KB */
#define MGBE_RXQ_SIZE 196608U
/* MAX PBL value */
#define MGBE_DMA_CHX_MAX_PBL 256U
#define MGBE_DMA_CHX_MAX_PBL_VAL 0x200000U
/* AXI Data width */
#define MGBE_AXI_DATAWIDTH 128U
/** @} */
/**
* @brief osi_readl_poll_timeout - Periodically poll an address until
@@ -277,9 +289,12 @@ static inline nve32_t validate_mac_ver_update_chans(nveu32_t mac_ver,
ret = 1;
break;
case OSI_MGBE_MAC_3_10:
//TBD: T264 uFPGA reports mac version 3.2
case OSI_MGBE_MAC_3_20:
#ifndef OSI_STRIPPED_LIB
case OSI_MGBE_MAC_4_00:
#endif /* !OSI_STRIPPED_LIB */
//TBD: T264 number of dma channels?
*num_max_chans = OSI_MGBE_MAX_NUM_CHANS;
*l_mac_ver = MAC_CORE_VER_TYPE_MGBE;
ret = 1;