mirror of
git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
synced 2025-12-22 09:12:10 +03:00
osi: T264 VDMA feature and bring up changes
Bug 4043836 Ported from the change - https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896005 Change-Id: Iabbbde0d2733f04bba5d7128e7b8ac5956605424 Signed-off-by: Mahesh Patil <maheshp@nvidia.com> Signed-off-by: Michael Hsu <mhsu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3149288 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Tested-by: Bhadram Varka <vbhadram@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com> Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
This commit is contained in:
Mahesh Patil
committed by
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parent
d28da6a10b
commit
8c7f7328e8
305
osi/core/xpcs.c
305
osi/core/xpcs.c
@@ -45,6 +45,11 @@ static inline nve32_t xpcs_poll_for_an_complete(struct osi_core_priv_data *osi_c
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nve32_t cond = 1;
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nve32_t ret = 0;
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if (osi_core->pre_sil == 0x1U) {
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//TBD: T264 increase retry for uFPGA
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retry = 10000;
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}
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/* 14. Poll for AN complete */
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cond = 1;
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count = 0;
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@@ -279,27 +284,43 @@ static nve32_t xpcs_uphy_lane_bring_up(struct osi_core_priv_data *osi_core,
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nveu32_t val = 0;
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nveu32_t count;
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nve32_t ret = 0;
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const nveu32_t uphy_status_reg[OSI_MAX_MAC_IP_TYPES] = {
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0,
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XPCS_WRAP_UPHY_STATUS,
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T26X_XPCS_WRAP_UPHY_STATUS
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};
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const nveu32_t uphy_init_ctrl_reg[OSI_MAX_MAC_IP_TYPES] = {
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0,
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XPCS_WRAP_UPHY_HW_INIT_CTRL,
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T26X_XPCS_WRAP_UPHY_HW_INIT_CTRL
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};
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val = osi_readla(osi_core,
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(nveu8_t *)xpcs_base + XPCS_WRAP_UPHY_STATUS);
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if ((val & XPCS_WRAP_UPHY_STATUS_TX_P_UP_STATUS) !=
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XPCS_WRAP_UPHY_STATUS_TX_P_UP_STATUS) {
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(nveu8_t *)xpcs_base + uphy_status_reg[osi_core->mac]);
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if ((lane_init_en == XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) &&
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((val & XPCS_WRAP_UPHY_STATUS_TX_P_UP_STATUS) ==
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XPCS_WRAP_UPHY_STATUS_TX_P_UP_STATUS)) {
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goto done;
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} else {
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val = osi_readla(osi_core,
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(nveu8_t *)xpcs_base + XPCS_WRAP_UPHY_HW_INIT_CTRL);
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(nveu8_t *)xpcs_base +
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uphy_init_ctrl_reg[osi_core->mac]);
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val |= lane_init_en;
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osi_writela(osi_core, val,
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(nveu8_t *)xpcs_base + XPCS_WRAP_UPHY_HW_INIT_CTRL);
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(nveu8_t *)xpcs_base +
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uphy_init_ctrl_reg[osi_core->mac]);
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count = 0;
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while (cond == COND_NOT_MET) {
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if (count > retry) {
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ret = -1;
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goto fail;
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goto done;
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}
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count++;
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val = osi_readla(osi_core,
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(nveu8_t *)xpcs_base + XPCS_WRAP_UPHY_HW_INIT_CTRL);
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(nveu8_t *)xpcs_base +
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uphy_init_ctrl_reg[osi_core->mac]);
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if ((val & lane_init_en) == OSI_NONE) {
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/* exit loop */
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cond = COND_MET;
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@@ -313,7 +334,7 @@ static nve32_t xpcs_uphy_lane_bring_up(struct osi_core_priv_data *osi_core,
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}
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}
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fail:
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done:
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return ret;
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}
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@@ -335,6 +356,11 @@ static nve32_t xpcs_check_pcs_lock_status(struct osi_core_priv_data *osi_core)
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nveu32_t val = 0;
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nveu32_t count;
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nve32_t ret = 0;
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const nveu32_t uphy_irq_sts_reg[OSI_MAX_MAC_IP_TYPES] = {
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0,
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XPCS_WRAP_INTERRUPT_STATUS,
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T26X_XPCS_WRAP_INTERRUPT_STATUS
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};
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count = 0;
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while (cond == COND_NOT_MET) {
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@@ -345,7 +371,8 @@ static nve32_t xpcs_check_pcs_lock_status(struct osi_core_priv_data *osi_core)
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count++;
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val = osi_readla(osi_core,
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(nveu8_t *)xpcs_base + XPCS_WRAP_IRQ_STATUS);
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(nveu8_t *)xpcs_base +
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uphy_irq_sts_reg[osi_core->mac]);
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if ((val & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS) ==
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XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS) {
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/* exit loop */
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@@ -361,7 +388,8 @@ static nve32_t xpcs_check_pcs_lock_status(struct osi_core_priv_data *osi_core)
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}
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/* Clear the status */
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osi_writela(osi_core, val, (nveu8_t *)xpcs_base + XPCS_WRAP_IRQ_STATUS);
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osi_writela(osi_core, val, (nveu8_t *)xpcs_base +
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uphy_irq_sts_reg[osi_core->mac]);
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fail:
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return ret;
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}
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@@ -394,145 +422,153 @@ static nve32_t xpcs_lane_bring_up(struct osi_core_priv_data *osi_core)
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goto fail;
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}
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if (l_core->lane_powered_up == OSI_ENABLE) {
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goto step10;
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}
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step1 RX_SW_OVRD */
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_SW_OVRD;
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step2 RX_IDDQ */
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val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_IDDQ);
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step2 AUX_RX_IDDQ */
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val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_AUX_RX_IDDQ);
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step3: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step4 RX_SLEEP */
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_SLEEP);
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step5: wait for 1usec, HW recommended value is 500nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step6 RX_CAL_EN */
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CAL_EN;
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step7 poll for Rx cal enable */
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cond = COND_NOT_MET;
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count = 0;
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while (cond == COND_NOT_MET) {
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if (count > retry) {
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if (osi_core->mac == OSI_MAC_HW_MGBE_T26X) {
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if (xpcs_uphy_lane_bring_up(osi_core,
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XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN) < 0) {
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OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
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"UPHY RX lane bring-up failed\n", 0ULL);
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ret = -1;
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goto fail;
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}
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count++;
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} else {
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if (l_core->lane_powered_up == OSI_ENABLE) {
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goto step10;
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}
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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if ((val & XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CAL_EN) == 0U) {
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cond = COND_MET;
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} else {
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/* Maximum wait delay as per HW team is 100 usec.
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* But most of the time as per experiments it takes
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* around 14usec to satisy the condition, so add a
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* minimum delay of 14usec and loop it for 7times.
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* With this 14usec delay condition gets satifies
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* in first iteration itself.
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*/
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osi_core->osd_ops.udelay(200U);
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/* Step1 RX_SW_OVRD */
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_SW_OVRD;
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step2 RX_IDDQ */
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val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_IDDQ);
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step2 AUX_RX_IDDQ */
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val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_AUX_RX_IDDQ);
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step3: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step4 RX_SLEEP */
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_SLEEP);
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step5: wait for 1usec, HW recommended value is 500nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step6 RX_CAL_EN */
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CAL_EN;
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osi_writela(osi_core, val,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step7 poll for Rx cal enable */
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cond = COND_NOT_MET;
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count = 0;
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while (cond == COND_NOT_MET) {
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if (count > retry) {
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ret = -1;
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goto fail;
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}
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count++;
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val = osi_readla(osi_core,
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(nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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if ((val & XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CAL_EN) == 0U) {
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cond = COND_MET;
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} else {
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/* Maximum wait delay as per HW team is 100 usec.
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* But most of the time as per experiments it takes
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* around 14usec to satisy the condition, so add a
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* minimum delay of 14usec and loop it for 7times.
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* With this 14usec delay condition gets satifies
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* in first iteration itself.
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*/
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osi_core->osd_ops.udelay(200U);
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}
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}
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}
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/* Step8: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step8: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step9 RX_DATA_EN */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_DATA_EN;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step9 RX_DATA_EN */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_DATA_EN;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* set lane_powered_up to OSI_ENABLE */
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l_core->lane_powered_up = OSI_ENABLE;
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/* set lane_powered_up to OSI_ENABLE */
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l_core->lane_powered_up = OSI_ENABLE;
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step10:
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/* Step10 reset RX_PCS_PHY_RDY */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val &= ~XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_PCS_PHY_RDY;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step10 reset RX_PCS_PHY_RDY */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val &= ~XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_PCS_PHY_RDY;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step11: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step11: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step12 RX_CDR_RESET */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CDR_RESET;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step12 RX_CDR_RESET */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CDR_RESET;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step13: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step13: wait for 1usec, HW recommended value is 50nsec minimum */
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osi_core->osd_ops.udelay(1U);
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/* Step14 RX_PCS_PHY_RDY */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_PCS_PHY_RDY;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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/* Step14: wait for 30ms */
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osi_core->osd_ops.udelay(30000U);
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/* Step14 RX_PCS_PHY_RDY */
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val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
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val |= XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_PCS_PHY_RDY;
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osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
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XPCS_WRAP_UPHY_RX_CONTROL_0_0);
|
||||
/* Step14: wait for 30ms */
|
||||
osi_core->osd_ops.udelay(30000U);
|
||||
|
||||
/* Step15 RX_CDR_RESET */
|
||||
val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
|
||||
XPCS_WRAP_UPHY_RX_CONTROL_0_0);
|
||||
val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CDR_RESET);
|
||||
osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
|
||||
XPCS_WRAP_UPHY_RX_CONTROL_0_0);
|
||||
/* Step15 RX_CDR_RESET */
|
||||
val = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
|
||||
XPCS_WRAP_UPHY_RX_CONTROL_0_0);
|
||||
val &= ~(XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CDR_RESET);
|
||||
osi_writela(osi_core, val, (nveu8_t *)osi_core->xpcs_base +
|
||||
XPCS_WRAP_UPHY_RX_CONTROL_0_0);
|
||||
|
||||
/* Step16: wait for 30ms */
|
||||
osi_core->osd_ops.udelay(30000U);
|
||||
/* Step16: wait for 30ms */
|
||||
osi_core->osd_ops.udelay(30000U);
|
||||
}
|
||||
|
||||
if (xpcs_check_pcs_lock_status(osi_core) < 0) {
|
||||
if (l_core->lane_status == OSI_ENABLE) {
|
||||
@@ -633,12 +669,15 @@ nve32_t xpcs_init(struct osi_core_priv_data *osi_core)
|
||||
nveu32_t ctrl = 0;
|
||||
nve32_t ret = 0;
|
||||
|
||||
|
||||
if (xpcs_lane_bring_up(osi_core) < 0) {
|
||||
ret = -1;
|
||||
goto fail;
|
||||
if (osi_core->pre_sil == 0x1U) {
|
||||
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
|
||||
"Pre-silicon, skipping lane bring up", 0ULL);
|
||||
} else {
|
||||
if (xpcs_lane_bring_up(osi_core) < 0) {
|
||||
ret = -1;
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
|
||||
/* Switching to USXGMII Mode based on
|
||||
* XPCS programming guideline 7.6
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user