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osi:core: Address review comments on HSI changes

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Bug 3590939
Change-Id: Id54b61871d5152c58376781c421077c62174bc2f
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2801135
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sanath Kumar Gampa
2022-11-01 15:05:46 +05:30
committed by Bhadram Varka
parent 038f231851
commit 9dea491138
5 changed files with 43 additions and 39 deletions
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20
include/osi_core.h
View File

@@ -101,7 +101,7 @@ typedef my_lint_64 nvel64_t;
#define OSI_INSTANCE_ID_MGBE1 1
#define OSI_INSTANCE_ID_MGBE2 2
#define OSI_INSTANCE_ID_MGBE3 3
#define OSI_INSTANCE_ID_EQOS0 4
#define OSI_INSTANCE_ID_EQOS 4
#endif /* !OSI_STRIPPED_LIB */
@@ -361,9 +361,9 @@ typedef my_lint_64 nvel64_t;
#ifdef HSI_SUPPORT
/**
* @addtogroup hsi_err_code_idx
* @addtogroup osi_hsi_err_code_idx
*
* @brief data index for hsi_err_code array
* @brief data index for osi_hsi_err_code array
* @{
*/
#define UE_IDX 0U
@@ -379,8 +379,8 @@ typedef my_lint_64 nvel64_t;
#define MACSEC_REG_VIOL_ERR_IDX 3U
/** @} */
extern nveu32_t hsi_err_code[][2];
extern nveu16_t hsi_reporter_id[];
extern nveu32_t osi_hsi_err_code[][2];
extern nveu16_t osi_hsi_reporter_id[];
/**
* @addtogroup HSI_TIME_THRESHOLD
@@ -402,7 +402,7 @@ extern nveu16_t hsi_reporter_id[];
* @brief Maximum number of different mac error code
* HSI_SW_ERR_CODE + Two (Corrected and Uncorrected error code)
*/
#define HSI_MAX_MAC_ERROR_CODE 7U
#define OSI_HSI_MAX_MAC_ERROR_CODE 7U
/**
* @brief Maximum number of different macsec error code
@@ -1249,9 +1249,9 @@ struct osi_hsi_data {
/** HSI reporter ID */
nveu16_t reporter_id;
/** HSI error codes */
nveu32_t err_code[HSI_MAX_MAC_ERROR_CODE];
nveu32_t err_code[OSI_HSI_MAX_MAC_ERROR_CODE];
/** HSI MAC report count threshold based error */
nveu32_t report_count_err[HSI_MAX_MAC_ERROR_CODE];
nveu32_t report_count_err[OSI_HSI_MAX_MAC_ERROR_CODE];
/** Indicates if error reporting to FSI is pending */
nveu32_t report_err;
/** HSI MACSEC error codes */
@@ -1278,6 +1278,10 @@ struct osi_hsi_data {
nveu64_t tx_frame_err_count;
/** tx frame error count threshold hit */
nveu64_t tx_frame_err_threshold;
/** Rx UDP error injection count */
nveu64_t inject_udp_err_count;
/** Rx CRC error injection count */
nveu64_t inject_crc_err_count;
};
#endif

8
osi/core/core_common.c
View File

@@ -1429,13 +1429,13 @@ void hsi_common_error_inject(struct osi_core_priv_data *osi_core,
{
switch (error_code) {
case OSI_INBOUND_BUS_CRC_ERR:
osi_core->mmc.mmc_rx_crc_error =
osi_update_stats_counter(osi_core->mmc.mmc_rx_crc_error,
osi_core->hsi.inject_crc_err_count =
osi_update_stats_counter(osi_core->hsi.inject_crc_err_count,
osi_core->hsi.err_count_threshold);
break;
case OSI_RECEIVE_CHECKSUM_ERR:
osi_core->mmc.mmc_rx_udp_err =
osi_update_stats_counter(osi_core->mmc.mmc_rx_udp_err,
osi_core->hsi.inject_udp_err_count =
osi_update_stats_counter(osi_core->hsi.inject_udp_err_count,
osi_core->hsi.err_count_threshold);
break;
case OSI_MACSEC_RX_CRC_ERR:

6
osi/core/eqos_core.c
View File

@@ -1000,7 +1000,7 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core,
if (enable == OSI_ENABLE) {
osi_core->hsi.enabled = OSI_ENABLE;
osi_core->hsi.reporter_id = hsi_reporter_id[osi_core->instance_id];
osi_core->hsi.reporter_id = osi_hsi_reporter_id[osi_core->instance_id];
/* T23X-EQOS_HSIv2-19: Enabling of Consistency Monitor for TX Frame Errors */
value = osi_readla(osi_core,
@@ -1960,7 +1960,7 @@ static void eqos_handle_hsi_intr(struct osi_core_priv_data *const osi_core)
if (((val & EQOS_REGISTER_PARITY_ERR) == EQOS_REGISTER_PARITY_ERR) ||
((val & EQOS_CORE_UNCORRECTABLE_ERR) == EQOS_CORE_UNCORRECTABLE_ERR)) {
osi_core->hsi.err_code[UE_IDX] =
hsi_err_code[osi_core->instance_id][UE_IDX];
osi_hsi_err_code[osi_core->instance_id][UE_IDX];
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[UE_IDX] = OSI_ENABLE;
/* Disable the interrupt */
@@ -1973,7 +1973,7 @@ static void eqos_handle_hsi_intr(struct osi_core_priv_data *const osi_core)
}
if ((val & EQOS_CORE_CORRECTABLE_ERR) == EQOS_CORE_CORRECTABLE_ERR) {
osi_core->hsi.err_code[CE_IDX] =
hsi_err_code[osi_core->instance_id][CE_IDX];
osi_hsi_err_code[osi_core->instance_id][CE_IDX];
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.ce_count =
osi_update_stats_counter(osi_core->hsi.ce_count, 1UL);

10
osi/core/mgbe_core.c
View File

@@ -2153,7 +2153,7 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
if (enable == OSI_ENABLE) {
osi_core->hsi.enabled = OSI_ENABLE;
osi_core->hsi.reporter_id = hsi_reporter_id[osi_core->instance_id];
osi_core->hsi.reporter_id = osi_hsi_reporter_id[osi_core->instance_id];
/* T23X-MGBE_HSIv2-12:Initialization of Transaction Timeout in PCS */
/* T23X-MGBE_HSIv2-11:Initialization of Watchdog Timer */
@@ -3526,7 +3526,7 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
if (((val & MGBE_REGISTER_PARITY_ERR) == MGBE_REGISTER_PARITY_ERR) ||
((val & MGBE_CORE_UNCORRECTABLE_ERR) == MGBE_CORE_UNCORRECTABLE_ERR)) {
osi_core->hsi.err_code[UE_IDX] =
hsi_err_code[osi_core->instance_id][UE_IDX];
osi_hsi_err_code[osi_core->instance_id][UE_IDX];
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[UE_IDX] = OSI_ENABLE;
/* Disable the interrupt */
@@ -3539,7 +3539,7 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
}
if ((val & MGBE_CORE_CORRECTABLE_ERR) == MGBE_CORE_CORRECTABLE_ERR) {
osi_core->hsi.err_code[CE_IDX] =
hsi_err_code[osi_core->instance_id][CE_IDX];
osi_hsi_err_code[osi_core->instance_id][CE_IDX];
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.ce_count =
osi_update_stats_counter(osi_core->hsi.ce_count, 1UL);
@@ -3578,7 +3578,7 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
XPCS_WRAP_INTERRUPT_STATUS);
if (((val & XPCS_CORE_UNCORRECTABLE_ERR) == XPCS_CORE_UNCORRECTABLE_ERR) ||
((val & XPCS_REGISTER_PARITY_ERR) == XPCS_REGISTER_PARITY_ERR)) {
osi_core->hsi.err_code[UE_IDX] = hsi_err_code[osi_core->instance_id][UE_IDX];
osi_core->hsi.err_code[UE_IDX] = osi_hsi_err_code[osi_core->instance_id][UE_IDX];
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[UE_IDX] = OSI_ENABLE;
/* Disable uncorrectable interrupts */
@@ -3590,7 +3590,7 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
XPCS_WRAP_INTERRUPT_CONTROL);
}
if ((val & XPCS_CORE_CORRECTABLE_ERR) == XPCS_CORE_CORRECTABLE_ERR) {
osi_core->hsi.err_code[CE_IDX] = hsi_err_code[osi_core->instance_id][CE_IDX];
osi_core->hsi.err_code[CE_IDX] = osi_hsi_err_code[osi_core->instance_id][CE_IDX];
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.ce_count =
osi_update_stats_counter(osi_core->hsi.ce_count, 1UL);

8
osi/core/osi_core.c
View File

@@ -27,9 +27,9 @@
#ifdef HSI_SUPPORT
/**
* @brief hsi_err_code - Array of error code
* @brief osi_hsi_err_code - Array of error code
*/
nveu32_t hsi_err_code[][2] = {
nveu32_t osi_hsi_err_code[][2] = {
{OSI_HSI_MGBE0_UE_CODE, OSI_HSI_MGBE0_CE_CODE},
{OSI_HSI_MGBE1_UE_CODE, OSI_HSI_MGBE1_CE_CODE},
{OSI_HSI_MGBE2_UE_CODE, OSI_HSI_MGBE2_CE_CODE},
@@ -38,9 +38,9 @@ nveu32_t hsi_err_code[][2] = {
};
/**
* @brief hsi_reporter_id - Array of reporter_id
* @brief osi_hsi_reporter_id - Array of reporter_id
*/
nveu16_t hsi_reporter_id[] = {
nveu16_t osi_hsi_reporter_id[] = {
OSI_HSI_MGBE0_REPORTER_ID,
OSI_HSI_MGBE1_REPORTER_ID,
OSI_HSI_MGBE2_REPORTER_ID,