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osi:dma: Fix below Cert errors

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CERT INT30-C
CERT INT08-C

Jira NET-2907

Change-Id: I4d08f3e3142a2721b9bfb0de1b21fc44dbaafcc7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3314573
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
This commit is contained in:
Sanath Kumar Gampa
2025-03-06 04:43:09 +00:00
committed by mobile promotions
parent c8e1bd95a2
commit 9ffb4bb396
1 changed files with 7 additions and 11 deletions
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18
osi/dma/osi_dma_txrx.c
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@@ -234,11 +234,13 @@ static inline nveu32_t compltd_rx_desc_cnt(struct osi_dma_priv_data *osi_dma,
/* completed desc write back offset */ /* completed desc write back offset */
rx_desc_wr_idx = ((value >> MGBE_RX_DESC_WR_RNG_RWDC_SHIFT ) & rx_desc_wr_idx = ((value >> MGBE_RX_DESC_WR_RNG_RWDC_SHIFT ) &
(osi_dma->rx_ring_sz - 1U)); (osi_dma->rx_ring_sz - 1U));
//If we remove this check we are seeing perf issues on mgbe3_0 of Ferrix if (rx_desc_wr_idx >= rx_ring->cur_rx_idx) {
// if (rx_desc_wr_idx >= rx_ring->cur_rx_idx) {
descr_compltd = (rx_desc_wr_idx - rx_ring->cur_rx_idx) & descr_compltd = (rx_desc_wr_idx - rx_ring->cur_rx_idx) &
(osi_dma->rx_ring_sz - 1U); (osi_dma->rx_ring_sz - 1U);
// } } else {
descr_compltd = ((rx_desc_wr_idx + osi_dma->rx_ring_sz) -
rx_ring->cur_rx_idx) & (osi_dma->rx_ring_sz - 1U);
}
} }
/* offset/index start from 0, so add 1 to get final count */ /* offset/index start from 0, so add 1 to get final count */
descr_compltd = (((descr_compltd) & ((nveu32_t)0x7FFFFFFFU)) + (1U)); descr_compltd = (((descr_compltd) & ((nveu32_t)0x7FFFFFFFU)) + (1U));
@@ -1315,10 +1317,7 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
for (i = 0; i < desc_cnt; i++) { for (i = 0; i < desc_cnt; i++) {
/* Increase the desc count for first descriptor */ /* Increase the desc count for first descriptor */
if (tx_ring->desc_cnt == UINT_MAX) { if (tx_ring->desc_cnt == UINT_MAX) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID, tx_ring->desc_cnt = 0U;
"dma_txrx: Reached Max Desc count\n", 0ULL);
ret = -1;
break;
} }
tx_ring->desc_cnt++; tx_ring->desc_cnt++;
@@ -1336,10 +1335,7 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
} }
if (tx_ring->desc_cnt == UINT_MAX) { if (tx_ring->desc_cnt == UINT_MAX) {
OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID, tx_ring->desc_cnt = 0U;
"dma_txrx: Reached Max Desc count\n", 0ULL);
ret = -1;
goto fail;
} }
/* Mark it as LAST descriptor */ /* Mark it as LAST descriptor */
last_desc->tdes3 |= TDES3_LD; last_desc->tdes3 |= TDES3_LD;