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osi: core: eqos pad calibration reg offsets

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Make eqos pad calibration reg ETHER_QOS_AUTO_CAL_CONFIG_0 offsets
AUTO_CAL_PD_OFFSET and 	AUTO_CAL_PU_OFFSET configurable as per
customer boards tuning

Bug 3846183

Change-Id: Ic305ced0d8324d7b9f5a03ffa7d6c21f7a12d9e5
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2805651
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Mahesh Patil
2022-11-08 22:42:11 -08:00
committed by Bhadram Varka
parent e2cf4313dc
commit a0afcf8463
3 changed files with 19 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/osi_core.h
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@@ -174,6 +174,8 @@ typedef my_lint_64 nvel64_t;
#define OSI_CHAN_ANY 0xFFU #define OSI_CHAN_ANY 0xFFU
#define OSI_DFLT_MTU_SIZE 1500U #define OSI_DFLT_MTU_SIZE 1500U
#define OSI_MTU_SIZE_9000 9000U #define OSI_MTU_SIZE_9000 9000U
/* Reg ETHER_QOS_AUTO_CAL_CONFIG_0[AUTO_CAL_PD/PU_OFFSET] max value */
#define OSI_PAD_CAL_CONFIG_PD_PU_OFFSET_MAX 0x1FU
#ifndef OSI_STRIPPED_LIB #ifndef OSI_STRIPPED_LIB
/* HW supports 8 Hash table regs, but eqos_validate_core_regs only checks 4 */ /* HW supports 8 Hash table regs, but eqos_validate_core_regs only checks 4 */
@@ -1191,6 +1193,10 @@ struct core_padctrl {
nveu32_t is_pad_cal_in_progress; nveu32_t is_pad_cal_in_progress;
/** This flag set/reset using priv ioctl and DT entry */ /** This flag set/reset using priv ioctl and DT entry */
nveu32_t pad_calibration_enable; nveu32_t pad_calibration_enable;
/** Reg ETHER_QOS_AUTO_CAL_CONFIG_0[AUTO_CAL_PD_OFFSET] value */
nveu32_t pad_auto_cal_pd_offset;
/** Reg ETHER_QOS_AUTO_CAL_CONFIG_0[AUTO_CAL_PU_OFFSET] value */
nveu32_t pad_auto_cal_pu_offset;
}; };
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT

11
osi/core/eqos_core.c
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@@ -186,9 +186,14 @@ static nve32_t eqos_pad_calibrate(struct osi_core_priv_data *const osi_core)
/* 3. Set AUTO_CAL_ENABLE and AUTO_CAL_START in /* 3. Set AUTO_CAL_ENABLE and AUTO_CAL_START in
* reg ETHER_QOS_AUTO_CAL_CONFIG_0. * reg ETHER_QOS_AUTO_CAL_CONFIG_0.
* Set pad_auto_cal pd/pu offset values
*/ */
value = osi_readla(osi_core, value = osi_readla(osi_core,
(nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG);
value &= ~EQOS_PAD_CRTL_PU_OFFSET_MASK;
value &= ~EQOS_PAD_CRTL_PD_OFFSET_MASK;
value |= osi_core->padctrl.pad_auto_cal_pu_offset;
value |= (osi_core->padctrl.pad_auto_cal_pd_offset << 8U);
value |= EQOS_PAD_AUTO_CAL_CFG_START | value |= EQOS_PAD_AUTO_CAL_CFG_START |
EQOS_PAD_AUTO_CAL_CFG_ENABLE; EQOS_PAD_AUTO_CAL_CFG_ENABLE;
osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG);
@@ -276,9 +281,15 @@ static nve32_t eqos_pad_calibrate(struct osi_core_priv_data *const osi_core)
osi_core->osd_ops.usleep_range(1, 3); osi_core->osd_ops.usleep_range(1, 3);
/* 3. Set AUTO_CAL_ENABLE and AUTO_CAL_START in /* 3. Set AUTO_CAL_ENABLE and AUTO_CAL_START in
* reg ETHER_QOS_AUTO_CAL_CONFIG_0. * reg ETHER_QOS_AUTO_CAL_CONFIG_0.
* Set pad_auto_cal pd/pu offset values
*/ */
value = osi_readla(osi_core, value = osi_readla(osi_core,
(nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG);
value &= ~EQOS_PAD_CRTL_PU_OFFSET_MASK;
value &= ~EQOS_PAD_CRTL_PD_OFFSET_MASK;
value |= osi_core->padctrl.pad_auto_cal_pu_offset;
value |= (osi_core->padctrl.pad_auto_cal_pd_offset << 8U);
value |= EQOS_PAD_AUTO_CAL_CFG_START | value |= EQOS_PAD_AUTO_CAL_CFG_START |
EQOS_PAD_AUTO_CAL_CFG_ENABLE; EQOS_PAD_AUTO_CAL_CFG_ENABLE;
osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG); osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG);

2
osi/core/eqos_core.h
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@@ -349,6 +349,8 @@
#define EQOS_PAD_AUTO_CAL_CFG_START OSI_BIT(31) #define EQOS_PAD_AUTO_CAL_CFG_START OSI_BIT(31)
#define EQOS_PAD_AUTO_CAL_STAT_ACTIVE OSI_BIT(31) #define EQOS_PAD_AUTO_CAL_STAT_ACTIVE OSI_BIT(31)
#define EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD OSI_BIT(31) #define EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD OSI_BIT(31)
#define EQOS_PAD_CRTL_PD_OFFSET_MASK 0x1F00U
#define EQOS_PAD_CRTL_PU_OFFSET_MASK 0x1FU
#define EQOS_MCR_IPC OSI_BIT(27) #define EQOS_MCR_IPC OSI_BIT(27)
#define EQOS_MMC_CNTRL_CNTRST OSI_BIT(0) #define EQOS_MMC_CNTRL_CNTRST OSI_BIT(0)
#define EQOS_MMC_CNTRL_RSTONRD OSI_BIT(2) #define EQOS_MMC_CNTRL_RSTONRD OSI_BIT(2)