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osi: core: mgbe: Enable HSI for TXESIE interrupt

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Issue:
Need HSI support for TXESIE interrupt

Fix:
Handle TXESIE interrupt for safety builds
and update HSI CE counters

Bug 3846917

Change-Id: Ie431f4b166d8adb524fba74e0da80570aa162bf1
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2827634
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mohan Thadikamalla
2022-11-23 14:56:32 +05:30
committed by mobile promotions
parent 6a8f317407
commit a114ece241
2 changed files with 36 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

48
osi/core/mgbe_core.c
View File

@@ -2181,11 +2181,13 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core)
struct core_local *l_core = (struct core_local *)(void *)osi_core; struct core_local *l_core = (struct core_local *)(void *)osi_core;
nveu32_t mac_isr = 0; nveu32_t mac_isr = 0;
nveu32_t mac_ier = 0; nveu32_t mac_ier = 0;
#ifndef OSI_STRIPPED_LIB
nveu32_t tx_errors = 0; nveu32_t tx_errors = 0;
#endif /* !OSI_STRIPPED_LIB */ nveu8_t *base = (nveu8_t *)osi_core->base;
#ifdef HSI_SUPPORT
nveu64_t tx_frame_err = 0;
#endif
mac_isr = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_ISR); mac_isr = osi_readla(osi_core, base + MGBE_MAC_ISR);
/* Check for Link status change interrupt */ /* Check for Link status change interrupt */
if ((mac_isr & MGBE_MAC_ISR_LSI) == OSI_ENABLE) { if ((mac_isr & MGBE_MAC_ISR_LSI) == OSI_ENABLE) {
@@ -2199,19 +2201,19 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core)
} }
} }
mac_ier = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_IER); mac_ier = osi_readla(osi_core, base + MGBE_MAC_IER);
if (((mac_isr & MGBE_MAC_IMR_FPEIS) == MGBE_MAC_IMR_FPEIS) && if (((mac_isr & MGBE_MAC_IMR_FPEIS) == MGBE_MAC_IMR_FPEIS) &&
((mac_ier & MGBE_IMR_FPEIE) == MGBE_IMR_FPEIE)) { ((mac_ier & MGBE_IMR_FPEIE) == MGBE_IMR_FPEIE)) {
mgbe_handle_mac_fpe_intrs(osi_core); mgbe_handle_mac_fpe_intrs(osi_core);
} }
#ifndef OSI_STRIPPED_LIB
/* Check for any MAC Transmit Error Status Interrupt */ /* Check for any MAC Transmit Error Status Interrupt */
if ((mac_isr & MGBE_IMR_TXESIE) == MGBE_IMR_TXESIE) { if ((mac_isr & MGBE_IMR_TXESIE) == MGBE_IMR_TXESIE) {
/* Check for the type of Tx error by reading MAC_Rx_Tx_Status /* Check for the type of Tx error by reading MAC_Rx_Tx_Status
* register * register
*/ */
tx_errors = osi_readl((nveu8_t *)osi_core->base + MGBE_MAC_RX_TX_STS); tx_errors = osi_readl(base + MGBE_MAC_RX_TX_STS);
#ifndef OSI_STRIPPED_LIB
if ((tx_errors & MGBE_MAC_TX_TJT) == MGBE_MAC_TX_TJT) { if ((tx_errors & MGBE_MAC_TX_TJT) == MGBE_MAC_TX_TJT) {
/* increment Tx Jabber timeout stats */ /* increment Tx Jabber timeout stats */
osi_core->stats.mgbe_jabber_timeout_err = osi_core->stats.mgbe_jabber_timeout_err =
@@ -2233,9 +2235,27 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core)
osi_core->stats.mgbe_payload_cs_err, osi_core->stats.mgbe_payload_cs_err,
1UL); 1UL);
} }
}
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
#ifdef HSI_SUPPORT
tx_errors &= (MGBE_MAC_TX_TJT | MGBE_MAC_TX_IHE | MGBE_MAC_TX_PCE);
if (tx_errors != OSI_NONE) {
osi_core->hsi.tx_frame_err_count =
osi_update_stats_counter(
osi_core->hsi.tx_frame_err_count, 1UL);
tx_frame_err = osi_core->hsi.tx_frame_err_count /
osi_core->hsi.err_count_threshold;
if (osi_core->hsi.tx_frame_err_threshold <
tx_frame_err) {
osi_core->hsi.tx_frame_err_threshold = tx_frame_err;
osi_core->hsi.report_count_err[TX_FRAME_ERR_IDX] = OSI_ENABLE;
}
osi_core->hsi.err_code[TX_FRAME_ERR_IDX] = OSI_TX_FRAME_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
}
#endif
}
if ((mac_isr & MGBE_ISR_TSIS) == MGBE_ISR_TSIS) { if ((mac_isr & MGBE_ISR_TSIS) == MGBE_ISR_TSIS) {
struct osi_core_tx_ts *head = &l_core->tx_ts_head; struct osi_core_tx_ts *head = &l_core->tx_ts_head;
@@ -2250,7 +2270,7 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core)
} }
/* TXTSC bit should get reset when all timestamp read */ /* TXTSC bit should get reset when all timestamp read */
while (((osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_TSS) & while (((osi_readla(osi_core, base + MGBE_MAC_TSS) &
MGBE_MAC_TSS_TXTSC) == MGBE_MAC_TSS_TXTSC)) { MGBE_MAC_TSS_TXTSC) == MGBE_MAC_TSS_TXTSC)) {
nveu32_t i = get_free_ts_idx(l_core); nveu32_t i = get_free_ts_idx(l_core);
@@ -2275,17 +2295,11 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core)
} }
} }
l_core->ts[i].nsec = osi_readla(osi_core, l_core->ts[i].nsec = osi_readla(osi_core, base + MGBE_MAC_TSNSSEC);
(nveu8_t *)osi_core->base +
MGBE_MAC_TSNSSEC);
l_core->ts[i].in_use = OSI_ENABLE; l_core->ts[i].in_use = OSI_ENABLE;
l_core->ts[i].pkt_id = osi_readla(osi_core, l_core->ts[i].pkt_id = osi_readla(osi_core, base + MGBE_MAC_TSPKID);
(nveu8_t *)osi_core->base + l_core->ts[i].sec = osi_readla(osi_core, base + MGBE_MAC_TSSEC);
MGBE_MAC_TSPKID);
l_core->ts[i].sec = osi_readla(osi_core,
(nveu8_t *)osi_core->base +
MGBE_MAC_TSSEC);
/* Add time stamp to end of list */ /* Add time stamp to end of list */
l_core->ts[i].next = head->prev->next; l_core->ts[i].next = head->prev->next;
head->prev->next = &l_core->ts[i]; head->prev->next = &l_core->ts[i];

10
osi/core/mgbe_core.h
View File

@@ -43,7 +43,6 @@
#define MGBE_MAC_PIDR2 0x0DCC #define MGBE_MAC_PIDR2 0x0DCC
#define MGBE_MAC_PMTCSR 0x00C0 #define MGBE_MAC_PMTCSR 0x00C0
#define MGBE_MAC_HTR_REG(x) ((0x0004U * (x)) + 0x0010U) #define MGBE_MAC_HTR_REG(x) ((0x0004U * (x)) + 0x0010U)
#define MGBE_MAC_RX_TX_STS 0x00B8
#define MGBE_WRAP_AXI_ASID0_CTRL 0x8400 #define MGBE_WRAP_AXI_ASID0_CTRL 0x8400
#define MGBE_WRAP_AXI_ASID1_CTRL 0x8404 #define MGBE_WRAP_AXI_ASID1_CTRL 0x8404
#define MGBE_WRAP_AXI_ASID2_CTRL 0x8408 #define MGBE_WRAP_AXI_ASID2_CTRL 0x8408
@@ -62,8 +61,6 @@
#define MGBE3_SID ((nveu32_t)0x4BU) #define MGBE3_SID ((nveu32_t)0x4BU)
#define MGBE_MAC_PAUSE_TIME 0xFFFF0000U #define MGBE_MAC_PAUSE_TIME 0xFFFF0000U
#define MGBE_MAC_PAUSE_TIME_MASK 0xFFFF0000U #define MGBE_MAC_PAUSE_TIME_MASK 0xFFFF0000U
#define MGBE_MAC_TX_TJT OSI_BIT(0)
#define MGBE_MAC_TX_IHE OSI_BIT(12)
#define MGBE_MAC_VLAN_TR_VTHM OSI_BIT(25) #define MGBE_MAC_VLAN_TR_VTHM OSI_BIT(25)
#define MGBE_MAC_VLAN_TR_VTIM OSI_BIT(17) #define MGBE_MAC_VLAN_TR_VTIM OSI_BIT(17)
#define MGBE_MAC_VLAN_TR_VTIM_SHIFT 17 #define MGBE_MAC_VLAN_TR_VTIM_SHIFT 17
@@ -100,7 +97,6 @@
#define MGBE_MAC_RSS_ADDR_RSSIA_SHIFT 8U #define MGBE_MAC_RSS_ADDR_RSSIA_SHIFT 8U
#define MGBE_MAC_RSS_ADDR_OB OSI_BIT(0) #define MGBE_MAC_RSS_ADDR_OB OSI_BIT(0)
#define MGBE_MAC_RSS_ADDR_CT OSI_BIT(1) #define MGBE_MAC_RSS_ADDR_CT OSI_BIT(1)
#define MGBE_MAC_TX_PCE OSI_BIT(13)
/** /**
* @addtogroup - MGBE-LPI LPI configuration macros * @addtogroup - MGBE-LPI LPI configuration macros
* *
@@ -156,9 +152,9 @@
#define MGBE_MTL_RXP_BYPASS_CNT 2U #define MGBE_MTL_RXP_BYPASS_CNT 2U
#define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1) #define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1)
#define MGBE_IMR_TXESIE OSI_BIT(13)
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
#define MGBE_MAC_RX_TX_STS 0x00B8
#define MGBE_MTL_EST_CONTROL 0x1050 #define MGBE_MTL_EST_CONTROL 0x1050
#define MGBE_MTL_EST_OVERHEAD 0x1054 #define MGBE_MTL_EST_OVERHEAD 0x1054
#define MGBE_MTL_EST_STATUS 0x1058 #define MGBE_MTL_EST_STATUS 0x1058
@@ -174,6 +170,9 @@
#define MGBE_MTL_RXP_IND_CS 0x10B0 #define MGBE_MTL_RXP_IND_CS 0x10B0
#define MGBE_MTL_RXP_IND_DATA 0x10B4 #define MGBE_MTL_RXP_IND_DATA 0x10B4
#define MGBE_MAC_TX_PCE OSI_BIT(13)
#define MGBE_MAC_TX_IHE OSI_BIT(12)
#define MGBE_MAC_TX_TJT OSI_BIT(0)
#define MGBE_MTL_TCQ_ETS_HCR(x) ((0x0080U * (x)) + 0x1120U) #define MGBE_MTL_TCQ_ETS_HCR(x) ((0x0080U * (x)) + 0x1120U)
#define MGBE_MTL_TCQ_ETS_LCR(x) ((0x0080U * (x)) + 0x1124U) #define MGBE_MTL_TCQ_ETS_LCR(x) ((0x0080U * (x)) + 0x1124U)
#define MGBE_MTL_TCQ_ETS_SSCR(x) ((0x0080U * (x)) + 0x111CU) #define MGBE_MTL_TCQ_ETS_SSCR(x) ((0x0080U * (x)) + 0x111CU)
@@ -200,6 +199,7 @@
#define MGBE_8PTP_CYCLE 26U #define MGBE_8PTP_CYCLE 26U
#define MGBE_PTP_CLK_SPEED 312500000U #define MGBE_PTP_CLK_SPEED 312500000U
#define MGBE_DMA_ISR_MTLIS OSI_BIT(16) #define MGBE_DMA_ISR_MTLIS OSI_BIT(16)
#define MGBE_IMR_TXESIE OSI_BIT(13)
#define MGBE_IMR_FPEIE OSI_BIT(15) #define MGBE_IMR_FPEIE OSI_BIT(15)
#ifndef OSI_STRIPPED_LIB #ifndef OSI_STRIPPED_LIB
#define MGBE_MAC_EXT_CNF_EIPG 0x1U #define MGBE_MAC_EXT_CNF_EIPG 0x1U