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core: mgbe: use lock for time stamping
Using lock for protect critical section between common interrupt and ioctl call to read timestamp Add mmc counters for lock failure during node addition and deletion. Bug 200743666 Change-Id: I12a2e57993e91d6ed50ed0efc84d1b60ef736677 Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2590099 Tested-by: Gaurav Asati <gasati@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Gaurav Asati <gasati@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com> Reviewed-by: Bhadram Varka <vbhadram@nvidia.com> Reviewed-by: Krishna Thota <kthota@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
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@@ -578,6 +578,10 @@ struct osi_xtra_stat_counters {
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nveu64_t link_connect_count;
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/** link disconnect count */
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nveu64_t link_disconnect_count;
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/** lock fail count node addition */
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nveu64_t ts_lock_add_fail;
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/** lock fail count node removal */
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nveu64_t ts_lock_del_fail;
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};
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#ifdef MACSEC_SUPPORT
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@@ -299,6 +299,8 @@ struct core_local {
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nveu32_t gcl_dep;
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/** Max GCL width (time + gate) value supported by HW */
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nveu32_t gcl_width_val;
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/** TS lock */
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nveu32_t ts_lock;
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};
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/**
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@@ -3270,6 +3270,15 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core,
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if ((mac_isr & MGBE_ISR_TSIS) == MGBE_ISR_TSIS) {
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struct osi_core_tx_ts *head = &l_core->tx_ts_head;
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if (__sync_fetch_and_add(&l_core->ts_lock, 1) == 1U) {
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/* mask return as initial value is returned always */
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(void)__sync_fetch_and_sub(&l_core->ts_lock, 1);
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osi_core->xstats.ts_lock_add_fail =
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osi_update_stats_counter(
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osi_core->xstats.ts_lock_add_fail, 1U);
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goto done;
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}
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/* TXTSC bit should get reset when all timestamp read */
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while (((osi_readla(osi_core, (nveu8_t *)osi_core->base +
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MGBE_MAC_TSS) &
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@@ -3299,7 +3308,11 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core,
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l_core->ts[i].prev = head->prev;
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head->prev = &l_core->ts[i];
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}
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/* mask return as initial value is returned always */
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(void)__sync_fetch_and_sub(&l_core->ts_lock, 1);
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}
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done:
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mac_isr &= ~MGBE_ISR_TSIS;
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osi_writela(osi_core, mac_isr,
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@@ -167,6 +167,7 @@ nve32_t osi_init_core_ops(struct osi_core_priv_data *const osi_core)
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return ret;
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}
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l_core->if_init_done = OSI_ENABLE;
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l_core->ts_lock = OSI_DISABLE;
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return ret;
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}
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@@ -1425,6 +1425,15 @@ static inline nve32_t get_tx_ts(struct osi_core_priv_data *osi_core,
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nve32_t ret = -1;
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nveu32_t count = 0U;
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if (__sync_fetch_and_add(&l_core->ts_lock, 1) == 1U) {
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/* mask return as initial value is returned always */
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(void)__sync_fetch_and_sub(&l_core->ts_lock, 1);
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osi_core->xstats.ts_lock_del_fail =
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osi_update_stats_counter(
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osi_core->xstats.ts_lock_del_fail, 1U);
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goto done;
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}
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while ((temp != head) && (count < MAX_TX_TS_CNT)) {
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if ((temp->pkt_id == ts->pkt_id) &&
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(temp->in_use != OSI_NONE)) {
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@@ -1442,6 +1451,9 @@ static inline nve32_t get_tx_ts(struct osi_core_priv_data *osi_core,
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temp = temp->next;
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}
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/* mask return as initial value is returned always */
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(void)__sync_fetch_and_sub(&l_core->ts_lock, 1);
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done:
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return ret;
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}
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@@ -249,7 +249,7 @@ nve32_t dma_desc_init(struct osi_dma_priv_data *osi_dma,
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} \
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} \
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#define BOOLEAN_FALSE (0U != 0U)
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#define BOOLEAN_FALSE (0U != 0U)
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#define L32(data) ((data) & 0xFFFFFFFFU)
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#define H32(data) (((data) & 0xFFFFFFFF00000000UL) >> 32UL)
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/** @} */
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