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nvethernetrm: Update comments with Doxygen style

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replace kernel doc comments with Doxygen style comments

Bug 200512422

Change-Id: I2e8e1f395674ab9e1b66bf40c1f6cc0551608163
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2154252
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Narayan Reddy
2019-07-16 23:08:50 +05:30
committed by Bhadram Varka
parent bac6dd9ca0
commit ae6f4415a9
16 changed files with 2258 additions and 2406 deletions
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451
include/mmc.h
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@@ -23,362 +23,333 @@
#ifndef MMC_H #ifndef MMC_H
#define MMC_H #define MMC_H
/** /**
* osi_mmc_counters - The structure to hold RMON counter values * @brief osi_mmc_counters - The structure to hold RMON counter values
*
* mmc_tx_octetcount_gb: This counter provides the number of bytes
* transmitted, exclusive of preamble and retried bytes, in good and
* bad packets.
* mmc_tx_framecount_gb: This counter provides the number of good and
* bad packets transmitted, exclusive of retried packets.
* mmc_tx_broadcastframe_g: This counter provides the number of good
* broadcast packets transmitted
* mmc_tx_multicastframe_g: This counter provides the number of good
* multicast packets transmitted
* mmc_tx_64_octets_gb: This counter provides the number of good and bad
* packets transmitted with length 64 bytes, exclusive of preamble and
* retried packets
* mmc_tx_65_to_127_octets_gb: This counter provides the number of good
* and bad packets transmitted with length 65-127 bytes, exclusive of
* preamble and retried packets
* mmc_tx_128_to_255_octets_gb: This counter provides the number of good
* and bad packets transmitted with length 128-255 bytes, exclusive of
* preamble and retried packets
* mmc_tx_256_to_511_octets_gb: This counter provides the number of good
* and bad packets transmitted with length 256-511 bytes, exclusive of
* preamble and retried packets
* mmc_tx_512_to_1023_octets_gb: This counter provides the number of good
* and bad packets transmitted with length 512-1023 bytes, exclusive of
* preamble and retried packets
* mmc_tx_1024_to_max_octets_gb: This counter provides the number of good
* and bad packets transmitted with length 1024-max bytes, exclusive of
* preamble and retried packets
* mmc_tx_unicast_gb: This counter provides the number of good and bad
* unicast packets
* mmc_tx_multicast_gb: This counter provides the number of good and bad
* multicast packets
* mmc_tx_broadcast_gb: This counter provides the number of good and bad
* braodcast packets
* mmc_tx_underflow_error: This counter provides the number of abort
* packets due to underflow error
* mmc_tx_singlecol_g: This counter provides the number of successfully
* transmitted packets after a single collision in the half-duplex mode
* mmc_tx_multicol_g: This counter provides the number of successfully
* transmitted packets after a multiple collision in the half-duplex mode
* mmc_tx_deferred: This counter provides the number of successfully
* transmitted after a deferral in the half-duplex mode
* mmc_tx_latecol: This counter provides the number of packets aborted
* because of late collision error
* mmc_tx_exesscol: This counter provides the number of packets aborted
* because of excessive (16) collision errors
* mmc_tx_carrier_error: This counter provides the number of packets
* aborted because of carrier sense error (no carrier or loss of carrier)
* mmc_tx_octetcount_g: This counter provides the number of bytes
* transmitted, exclusive of preamble, only in good packets.
* mmc_tx_framecount_g: This counter provides the number of good packets
* transmitted .
* mmc_tx_excessdef: This counter provides the number of packets aborted
* because of excessive deferral error (deferred for more than two
* max-sized packet times).
* mmc_tx_pause_frame: This counter provides the number of good Pause
* packets transmitted.
* mmc_tx_vlan_frame_g: This counter provides the number of good
* VLAN packets transmitted
* mmc_tx_osize_frame_g: This counter provides the number of packets
* transmitted without errors and with length greater than the maxsize
* (1,518 or 1,522 bytes for VLAN tagged packets; 2000 bytes.
* mmc_rx_framecount_gb: This counter provides the number of good and bad
* packets received
* mmc_rx_octetcount_gb: This counter provides the number of bytes
* received by DWC_ther_qos, exclusive of preamble, in good and bad packets
* mmc_rx_octetcount_g: This counter provides the number of bytes
* received by DWC_ther_qos, exclusive of preamble, in good and bad packets
* mmc_rx_broadcastframe_g: This counter provides the number of good
* broadcast packets received
* mmc_rx_multicastframe_g: This counter provides the number of good
* multicast packets received
* mmc_rx_crc_error: This counter provides the number of packets received
* with CRC error
* mmc_rx_align_error: This counter provides the number of packets
* received with alignment (dribble) error. It is valid only in 10/100
* mode.
* mmc_rx_runt_error: This counter provides the number of packets
* received with runt (length less than 64 bytes and CRC error) error
* mmc_rx_jabber_error: This counter provides the number of giant packets
* received with length (including CRC) greater than 1,518 bytes
* (1,522 bytes for VLAN tagged) and with CRC error.
* mmc_rx_undersize_g: This counter provides the number of packets
* received with length less than 64 bytes, without any errors
* mmc_rx_oversize_g: This counter provides the number of packets
* received without errors, with length greater than the maxsize
* mmc_rx_64_octets_gb: This counter provides the number of good and bad
* packets received with length 64 bytes, exclusive of the preamble.
* mmc_rx_65_to_127_octets_gb: This counter provides the number of good
* and bad packets received with length 65-127 bytes, exclusive of the
* preamble.
* mmc_rx_128_to_255_octets_gb: This counter provides the number of good
* and bad packets received with length 128-255 bytes, exclusive of the
* preamble.
* mmc_rx_256_to_511_octets_gb: This counter provides the number of good
* and bad packets received with length 256-511 bytes, exclusive of the
* preamble.
* mmc_rx_512_to_1023_octets_gb: This counter provides the number of good
* and bad packets received with length 512-1023 bytes, exclusive of the
* preamble.
* mmc_rx_1024_to_max_octets_gb: This counter provides the number of good
* and bad packets received with length 1024-max bytes, exclusive of the
* preamble.
* mmc_rx_unicast_g: This counter provides the number of good unicast
* packets received mmc_rx_length_error: This counter provides the
* number of packets received with length error (Length Type field
* not equal to packet size), for all packets with valid length field.
* mmc_rx_outofrangetype: This counter provides the number of packets
* received with length field not equal to the
* valid packet size (greater than 1,500 but less than 1,536).
* mmc_rx_pause_frames: This counter provides the number of good and
* valid Pause packets received
* mmc_rx_fifo_overflow: This counter provides the number of missed
* received packets because of FIFO overflow in DWC_ether_qos
* mmc_rx_vlan_frames_gb: This counter provides the number of good and
* bad VLAN packets received
* mmc_rx_watchdog_error: This counter provides the number of packets
* received with error because of watchdog timeout error
* mmc_rx_receive_error: This counter provides the number of packets
* received with Receive error or Packet Extension error on the GMII or
* MII interface
* mmc_rx_ctrl_frames_g: This counter provides the number of packets
* received with Receive error or Packet Extension error on the GMII
* or MII interface
* mmc_rx_ipv4_gd: This counter provides the number of good IPv4
* datagrams received with the TCP, UDP, or ICMP payload
* mmc_rx_ipv4_hderr: RxIPv4 Header Error Packets
* mmc_rx_ipv4_nopay: This counter provides the number of IPv4 datagram
* packets received that did not have a TCP, UDP, or ICMP payload
* mmc_rx_ipv4_frag: This counter provides the number of good IPv4
* datagrams received with fragmentation.
* mmc_rx_ipv4_udsbl: This counter provides the number of good IPv4
* datagrams received that had a UDP payload with checksum disabled
* mmc_rx_ipv6_gd_octets: This counter provides the number of good IPv6
* datagrams received with the TCP, UDP, or ICMP payload
* mmc_rx_ipv6_hderr_octets: This counter provides the number of IPv6
* datagrams received with header (length or version mismatch) errors
* mmc_rx_ipv6_nopay_octets: This counter provides the number of IPv6
* datagram packets received that did not have a TCP, UDP, or ICMP
* payload
* mmc_rx_udp_gd: This counter provides the number of good IP datagrams
* received by DWC_ether_qos with a good UDP payload.
* mmc_rx_udp_err: This counter provides the number of good IP datagrams
* received by DWC_ether_qos with a good UDP payload. This counter is not
* updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is
* incremented.
* mmc_rx_tcp_gd: This counter provides the number of good IP datagrams
* received with a good TCP payload
* mmc_rx_tcp_err: This counter provides the number of good IP datagrams
* received with a good TCP payload
* mmc_rx_icmp_gd: This counter provides the number of good IP datagrams
* received with a good ICMP payload
* mmc_rx_icmp_err: This counter provides the number of good IP
* datagrams received whose ICMP payload has a checksum error
* mmc_rx_ipv4_gd_octets: This counter provides the number of bytes
* received by DWC_ether_qos in good IPv4 datagrams encapsulating TCP,
* UDP, or ICMP data. (Ethernet header, FCS, pad, or IP pad bytes are
* not included in this counter
* mmc_rx_ipv4_hderr_octets: This counter provides the number of bytes
* received in IPv4 datagrams with header errors (checksum, length,
* version mismatch). The value in the Length field of IPv4 header is
* used to update this counter. (Ethernet header, FCS, pad,
* or IP pad bytes are not included in this counter
* mmc_rx_ipv4_nopay_octets: This counter provides the number of bytes
* received in IPv4 datagrams that did not have a TCP, UDP, or
* ICMP payload. The value in the Length field of IPv4 header is used
* to update this counter. (Ethernet header, FCS, pad, or IP pad bytes
* are not included in this counter.
* mmc_rx_ipv4_frag_octets: This counter provides the number of bytes
* received in fragmented IPv4 datagrams. The value in the Length
* field of IPv4 header is used to update this counter. (Ethernet header,
* FCS, pad, or IP pad bytes are not included in this counter
* mmc_rx_ipv4_udsbl_octets: This counter provides the number of bytes
* received in a UDP segment that had the UDP checksum disabled. This
* counter does not count IP Header bytes. (Ethernet header, FCS, pad,
* or IP pad bytes are not included in this counter.
* mmc_rx_ipv6_gd: This counter provides the number of bytes received
* in good IPv6 datagrams encapsulating TCP, UDP, or ICMP data.
* (Ethernet header, FCS, pad, or IP pad bytes are not included in
* this counter
* mmc_rx_ipv6_hderr: This counter provides the number of bytes received
* in IPv6 datagrams with header errors (length, version mismatch). The
* value in the Length field of IPv6 header is used to update this
* counter. (Ethernet header, FCS, pad, or IP pad bytes are not included
* in this counter.
* mmc_rx_ipv6_nopay: This counter provides the number of bytes received
* in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The
* value in the Length field of IPv6 header is used to update this
* counter. (Ethernet header, FCS, pad, or IP pad bytes are not included
* in this counter
* mmc_rx_udp_gd_octets: This counter provides the number of bytes
* received in a good UDP segment. This counter does not count IP header
* bytes.
* mmc_rx_udp_err_octets: This counter provides the number of bytes
* received in a UDP segment that had checksum errors. This counter
* does not count IP header bytes
* mmc_rx_tcp_gd_octets: This counter provides the number of bytes
* received in a good TCP segment. This counter does not count IP
* header bytes
* mmc_rx_tcp_err_octets: This counter provides the number of bytes
* received in a TCP segment that had checksum errors. This counter
* does not count IP header bytes
* mmc_rx_icmp_gd_octets: This counter provides the number of bytes
* received in a good ICMP segment. This counter does not count
* IP header bytes
* mmc_rx_icmp_err_octets: This counter provides the number of bytes
* received in a ICMP segment that had checksum errors.
* This counter does not count IP header bytes
*/ */
struct osi_mmc_counters { struct osi_mmc_counters {
/* MMC TX counters */ /** This counter provides the number of bytes transmitted, exclusive of
* preamble and retried bytes, in good and bad packets */
unsigned long mmc_tx_octetcount_gb; unsigned long mmc_tx_octetcount_gb;
/** This counter provides the number of good and
* bad packets transmitted, exclusive of retried packets */
unsigned long mmc_tx_framecount_gb; unsigned long mmc_tx_framecount_gb;
/** This counter provides number of good broadcast
* packets transmitted */
unsigned long mmc_tx_broadcastframe_g; unsigned long mmc_tx_broadcastframe_g;
/** This counter provides number of good multicast
* packets transmitted */
unsigned long mmc_tx_multicastframe_g; unsigned long mmc_tx_multicastframe_g;
/** This counter provides the number of good and bad packets
* transmitted with length 64 bytes, exclusive of preamble and
* retried packets */
unsigned long mmc_tx_64_octets_gb; unsigned long mmc_tx_64_octets_gb;
/** This counter provides the number of good and bad packets
* transmitted with length 65-127 bytes, exclusive of preamble and
* retried packets */
unsigned long mmc_tx_65_to_127_octets_gb; unsigned long mmc_tx_65_to_127_octets_gb;
/** This counter provides the number of good and bad packets
* transmitted with length 128-255 bytes, exclusive of preamble and
* retried packets */
unsigned long mmc_tx_128_to_255_octets_gb; unsigned long mmc_tx_128_to_255_octets_gb;
/** This counter provides the number of good and bad packets
* transmitted with length 256-511 bytes, exclusive of preamble and
* retried packets */
unsigned long mmc_tx_256_to_511_octets_gb; unsigned long mmc_tx_256_to_511_octets_gb;
/** This counter provides the number of good and bad packets
* transmitted with length 512-1023 bytes, exclusive of preamble and
* retried packets */
unsigned long mmc_tx_512_to_1023_octets_gb; unsigned long mmc_tx_512_to_1023_octets_gb;
/** This counter provides the number of good and bad packets
* transmitted with length 1024-max bytes, exclusive of preamble and
* retried packets */
unsigned long mmc_tx_1024_to_max_octets_gb; unsigned long mmc_tx_1024_to_max_octets_gb;
/** This counter provides the number of good and bad unicast packets */
unsigned long mmc_tx_unicast_gb; unsigned long mmc_tx_unicast_gb;
/** This counter provides the number of good and bad
* multicast packets */
unsigned long mmc_tx_multicast_gb; unsigned long mmc_tx_multicast_gb;
/** This counter provides the number of good and bad
* broadcast packets */
unsigned long mmc_tx_broadcast_gb; unsigned long mmc_tx_broadcast_gb;
/** mmc_tx_underflow_error: This counter provides the number of abort
* packets due to underflow error */
unsigned long mmc_tx_underflow_error; unsigned long mmc_tx_underflow_error;
/** This counter provides the number of successfully transmitted
* packets after a single collision in the half-duplex mode */
unsigned long mmc_tx_singlecol_g; unsigned long mmc_tx_singlecol_g;
/** This counter provides the number of successfully transmitted
* packets after a multi collision in the half-duplex mode */
unsigned long mmc_tx_multicol_g; unsigned long mmc_tx_multicol_g;
/** This counter provides the number of successfully transmitted
* after a deferral in the half-duplex mode */
unsigned long mmc_tx_deferred; unsigned long mmc_tx_deferred;
/** This counter provides the number of packets aborted because of
* late collision error */
unsigned long mmc_tx_latecol; unsigned long mmc_tx_latecol;
/** This counter provides the number of packets aborted because of
* excessive (16) collision errors */
unsigned long mmc_tx_exesscol; unsigned long mmc_tx_exesscol;
/** This counter provides the number of packets aborted because of
* carrier sense error (no carrier or loss of carrier) */
unsigned long mmc_tx_carrier_error; unsigned long mmc_tx_carrier_error;
/** This counter provides the number of bytes transmitted,
* exclusive of preamble, only in good packets */
unsigned long mmc_tx_octetcount_g; unsigned long mmc_tx_octetcount_g;
/** This counter provides the number of good packets transmitted */
unsigned long mmc_tx_framecount_g; unsigned long mmc_tx_framecount_g;
/** This counter provides the number of packets aborted because of
* excessive deferral error
* (deferred for more than two max-sized packet times) */
unsigned long mmc_tx_excessdef; unsigned long mmc_tx_excessdef;
/** This counter provides the number of good Pause
* packets transmitted */
unsigned long mmc_tx_pause_frame; unsigned long mmc_tx_pause_frame;
/** This counter provides the number of good VLAN packets transmitted */
unsigned long mmc_tx_vlan_frame_g; unsigned long mmc_tx_vlan_frame_g;
/** This counter provides the number of packets transmitted without
* errors and with length greater than the maxsize (1,518 or 1,522 bytes
* for VLAN tagged packets; 2000 bytes */
unsigned long mmc_tx_osize_frame_g; unsigned long mmc_tx_osize_frame_g;
/** This counter provides the number of good and bad packets received */
/* MMC RX counters */
unsigned long mmc_rx_framecount_gb; unsigned long mmc_rx_framecount_gb;
/** This counter provides the number of bytes received by DWC_ther_qos,
* exclusive of preamble, in good and bad packets */
unsigned long mmc_rx_octetcount_gb; unsigned long mmc_rx_octetcount_gb;
/** This counter provides the number of bytes received by DWC_ther_qos,
* exclusive of preamble, in good and bad packets */
unsigned long mmc_rx_octetcount_g; unsigned long mmc_rx_octetcount_g;
/** This counter provides the number of good
* broadcast packets received */
unsigned long mmc_rx_broadcastframe_g; unsigned long mmc_rx_broadcastframe_g;
/** This counter provides the number of good
* multicast packets received */
unsigned long mmc_rx_multicastframe_g; unsigned long mmc_rx_multicastframe_g;
/** This counter provides the number of packets
* received with CRC error */
unsigned long mmc_rx_crc_error; unsigned long mmc_rx_crc_error;
/** This counter provides the number of packets received with
* alignment (dribble) error. It is valid only in 10/100 mode */
unsigned long mmc_rx_align_error; unsigned long mmc_rx_align_error;
/** This counter provides the number of packets received with
* runt (length less than 64 bytes and CRC error) error */
unsigned long mmc_rx_runt_error; unsigned long mmc_rx_runt_error;
/** This counter provides the number of giant packets received with
* length (including CRC) greater than 1,518 bytes (1,522 bytes for
* VLAN tagged) and with CRC error */
unsigned long mmc_rx_jabber_error; unsigned long mmc_rx_jabber_error;
/** This counter provides the number of packets received with length
* less than 64 bytes, without any errors */
unsigned long mmc_rx_undersize_g; unsigned long mmc_rx_undersize_g;
/** This counter provides the number of packets received without error,
* with length greater than the maxsize */
unsigned long mmc_rx_oversize_g; unsigned long mmc_rx_oversize_g;
/** This counter provides the number of good and bad packets received
* with length 64 bytes, exclusive of the preamble */
unsigned long mmc_rx_64_octets_gb; unsigned long mmc_rx_64_octets_gb;
/** This counter provides the number of good and bad packets received
* with length 65-127 bytes, exclusive of the preamble */
unsigned long mmc_rx_65_to_127_octets_gb; unsigned long mmc_rx_65_to_127_octets_gb;
/** This counter provides the number of good and bad packets received
* with length 128-255 bytes, exclusive of the preamble */
unsigned long mmc_rx_128_to_255_octets_gb; unsigned long mmc_rx_128_to_255_octets_gb;
/** This counter provides the number of good and bad packets received
* with length 256-511 bytes, exclusive of the preamble */
unsigned long mmc_rx_256_to_511_octets_gb; unsigned long mmc_rx_256_to_511_octets_gb;
/** This counter provides the number of good and bad packets received
* with length 512-1023 bytes, exclusive of the preamble */
unsigned long mmc_rx_512_to_1023_octets_gb; unsigned long mmc_rx_512_to_1023_octets_gb;
/** This counter provides the number of good and bad packets received
* with length 1024-maxbytes, exclusive of the preamble */
unsigned long mmc_rx_1024_to_max_octets_gb; unsigned long mmc_rx_1024_to_max_octets_gb;
/** This counter provides the number of good unicast packets received */
unsigned long mmc_rx_unicast_g; unsigned long mmc_rx_unicast_g;
/** This counter provides the number of packets received with length
* error (Length Type field not equal to packet size), for all packets
* with valid length field */
unsigned long mmc_rx_length_error; unsigned long mmc_rx_length_error;
/** This counter provides the number of packets received with length
* field not equal to the valid packet size (greater than 1,500 but
* less than 1,536) */
unsigned long mmc_rx_outofrangetype; unsigned long mmc_rx_outofrangetype;
/** This counter provides the number of good and valid Pause packets
* received */
unsigned long mmc_rx_pause_frames; unsigned long mmc_rx_pause_frames;
/** This counter provides the number of missed received packets
* because of FIFO overflow in DWC_ether_qos */
unsigned long mmc_rx_fifo_overflow; unsigned long mmc_rx_fifo_overflow;
/** This counter provides the number of good and bad VLAN packets
* received */
unsigned long mmc_rx_vlan_frames_gb; unsigned long mmc_rx_vlan_frames_gb;
/** This counter provides the number of packets received with error
* because of watchdog timeout error */
unsigned long mmc_rx_watchdog_error; unsigned long mmc_rx_watchdog_error;
/** This counter provides the number of packets received with Receive
* error or Packet Extension error on the GMII or MII interface */
unsigned long mmc_rx_receive_error; unsigned long mmc_rx_receive_error;
/** This counter provides the number of packets received with Receive
* error or Packet Extension error on the GMII or MII interface */
unsigned long mmc_rx_ctrl_frames_g; unsigned long mmc_rx_ctrl_frames_g;
/* IPv4 */ /** This counter provides the number of good IPv4 datagrams received
* with the TCP, UDP, or ICMP payload */
unsigned long mmc_rx_ipv4_gd; unsigned long mmc_rx_ipv4_gd;
/** RxIPv4 Header Error Packets */
unsigned long mmc_rx_ipv4_hderr; unsigned long mmc_rx_ipv4_hderr;
/** This counter provides the number of IPv4 datagram packets received
* that did not have a TCP, UDP, or ICMP payload */
unsigned long mmc_rx_ipv4_nopay; unsigned long mmc_rx_ipv4_nopay;
/** This counter provides the number of good IPv4 datagrams received
* with fragmentation */
unsigned long mmc_rx_ipv4_frag; unsigned long mmc_rx_ipv4_frag;
/** This counter provides the number of good IPv4 datagrams received
* that had a UDP payload with checksum disabled */
unsigned long mmc_rx_ipv4_udsbl; unsigned long mmc_rx_ipv4_udsbl;
/* IPV6 */ /** This counter provides the number of good IPv6 datagrams received
* with the TCP, UDP, or ICMP payload */
unsigned long mmc_rx_ipv6_gd_octets; unsigned long mmc_rx_ipv6_gd_octets;
/** This counter provides the number of IPv6 datagrams received
* with header (length or version mismatch) errors */
unsigned long mmc_rx_ipv6_hderr_octets; unsigned long mmc_rx_ipv6_hderr_octets;
/** This counter provides the number of IPv6 datagram packets received
* that did not have a TCP, UDP, or ICMP payload */
unsigned long mmc_rx_ipv6_nopay_octets; unsigned long mmc_rx_ipv6_nopay_octets;
/* Protocols */ /* Protocols */
/** This counter provides the number of good IP datagrams received by
* DWC_ether_qos with a good UDP payload */
unsigned long mmc_rx_udp_gd; unsigned long mmc_rx_udp_gd;
/** This counter provides the number of good IP datagrams received by
* DWC_ether_qos with a good UDP payload. This counter is not updated
* when the RxIPv4_UDP_Checksum_Disabled_Packets counter is
* incremented */
unsigned long mmc_rx_udp_err; unsigned long mmc_rx_udp_err;
/** This counter provides the number of good IP datagrams received
* with a good TCP payload */
unsigned long mmc_rx_tcp_gd; unsigned long mmc_rx_tcp_gd;
/** This counter provides the number of good IP datagrams received
* with a good TCP payload */
unsigned long mmc_rx_tcp_err; unsigned long mmc_rx_tcp_err;
/** This counter provides the number of good IP datagrams received
* with a good ICMP payload */
unsigned long mmc_rx_icmp_gd; unsigned long mmc_rx_icmp_gd;
/** This counter provides the number of good IP datagrams received
* whose ICMP payload has a checksum error */
unsigned long mmc_rx_icmp_err; unsigned long mmc_rx_icmp_err;
/* IPv4 */ /** This counter provides the number of bytes received by DWC_ether_qos
* in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data.
* (Ethernet header, FCS, pad, or IP pad bytes are not included
* in this counter */
unsigned long mmc_rx_ipv4_gd_octets; unsigned long mmc_rx_ipv4_gd_octets;
/** This counter provides the number of bytes received in IPv4 datagram
* with header errors (checksum, length, version mismatch). The value
* in the Length field of IPv4 header is used to update this counter.
* (Ethernet header, FCS, pad, or IP pad bytes are not included
* in this counter */
unsigned long mmc_rx_ipv4_hderr_octets; unsigned long mmc_rx_ipv4_hderr_octets;
/** This counter provides the number of bytes received in IPv4 datagram
* that did not have a TCP, UDP, or ICMP payload. The value in the
* Length field of IPv4 header is used to update this counter.
* (Ethernet header, FCS, pad, or IP pad bytes are not included
* in this counter */
unsigned long mmc_rx_ipv4_nopay_octets; unsigned long mmc_rx_ipv4_nopay_octets;
/** This counter provides the number of bytes received in fragmented
* IPv4 datagrams. The value in the Length field of IPv4 header is
* used to update this counter. (Ethernet header, FCS, pad, or IP pad
* bytes are not included in this counter */
unsigned long mmc_rx_ipv4_frag_octets; unsigned long mmc_rx_ipv4_frag_octets;
/** This counter provides the number of bytes received in a UDP segment
* that had the UDP checksum disabled. This counter does not count IP
* Header bytes. (Ethernet header, FCS, pad, or IP pad bytes are not
* included in this counter */
unsigned long mmc_rx_ipv4_udsbl_octets; unsigned long mmc_rx_ipv4_udsbl_octets;
/** This counter provides the number of bytes received in good IPv6
/* IPV6 */ * datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header,
* FCS, pad, or IP pad bytes are not included in this counter */
unsigned long mmc_rx_ipv6_gd; unsigned long mmc_rx_ipv6_gd;
/** This counter provides the number of bytes received in IPv6 datagrams
* with header errors (length, version mismatch). The value in the
* Length field of IPv6 header is used to update this counter.
* (Ethernet header, FCS, pad, or IP pad bytes are not included in
* this counter */
unsigned long mmc_rx_ipv6_hderr; unsigned long mmc_rx_ipv6_hderr;
/** This counter provides the number of bytes received in IPv6
* datagrams that did not have a TCP, UDP, or ICMP payload. The value
* in the Length field of IPv6 header is used to update this counter.
* (Ethernet header, FCS, pad, or IP pad bytes are not included
* in this counter */
unsigned long mmc_rx_ipv6_nopay; unsigned long mmc_rx_ipv6_nopay;
/* Protocols */ /* Protocols */
/** This counter provides the number of bytes received in a good UDP
* segment. This counter does not count IP header bytes */
unsigned long mmc_rx_udp_gd_octets; unsigned long mmc_rx_udp_gd_octets;
/** This counter provides the number of bytes received in a UDP
* segment that had checksum errors. This counter does not count
* IP header bytes */
unsigned long mmc_rx_udp_err_octets; unsigned long mmc_rx_udp_err_octets;
/** This counter provides the number of bytes received in a good
* TCP segment. This counter does not count IP header bytes */
unsigned long mmc_rx_tcp_gd_octets; unsigned long mmc_rx_tcp_gd_octets;
/** This counter provides the number of bytes received in a TCP
* segment that had checksum errors. This counter does not count
* IP header bytes */
unsigned long mmc_rx_tcp_err_octets; unsigned long mmc_rx_tcp_err_octets;
/** This counter provides the number of bytes received in a good
* ICMP segment. This counter does not count IP header bytes */
unsigned long mmc_rx_icmp_gd_octets; unsigned long mmc_rx_icmp_gd_octets;
/** This counter provides the number of bytes received in a ICMP
* segment that had checksum errors. This counter does not count
* IP header bytes */
unsigned long mmc_rx_icmp_err_octets; unsigned long mmc_rx_icmp_err_octets;
}; };
/** /**
* osi_xtra_stat_counters - OSI core extra stat counters * @brief osi_xtra_stat_counters - OSI core extra stat counters
*
* rx_buf_unavail_irq_n: RX buffer unavailable irq count
* tx_proc_stopped_irq_n: Transmit Process Stopped irq count
* tx_buf_unavail_irq_n: Transmit Buffer Unavailable irq count
* rx_proc_stopped_irq_n: Receive Process Stopped irq count
* rx_watchdog_irq_n: Receive Watchdog Timeout irq count
* fatal_bus_error_irq_n: Fatal Bus Error irq count
* q_re_alloc_rx_buf_failed: rx sbk allocation failure count
* tx_normal_irq_n: TX per channel interrupt count
* rx_normal_irq_n: RX per cannel interrupt count
* link_connect_count: link disconnect count
* link_disconnect_count: link connect count
*/ */
struct osi_xtra_stat_counters { struct osi_xtra_stat_counters {
/** RX buffer unavailable irq count */
unsigned long rx_buf_unavail_irq_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long rx_buf_unavail_irq_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Transmit Process Stopped irq count */
unsigned long tx_proc_stopped_irq_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long tx_proc_stopped_irq_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Transmit Buffer Unavailable irq count */
unsigned long tx_buf_unavail_irq_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long tx_buf_unavail_irq_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Receive Process Stopped irq count */
unsigned long rx_proc_stopped_irq_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long rx_proc_stopped_irq_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Receive Watchdog Timeout irq count */
unsigned long rx_watchdog_irq_n; unsigned long rx_watchdog_irq_n;
/** Fatal Bus Error irq count */
unsigned long fatal_bus_error_irq_n; unsigned long fatal_bus_error_irq_n;
/** rx skb allocation failure count */
unsigned long re_alloc_rxbuf_failed[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long re_alloc_rxbuf_failed[OSI_EQOS_MAX_NUM_QUEUES];
/** TX per channel interrupt count */
unsigned long tx_normal_irq_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long tx_normal_irq_n[OSI_EQOS_MAX_NUM_QUEUES];
/** RX per channel interrupt count */
unsigned long rx_normal_irq_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long rx_normal_irq_n[OSI_EQOS_MAX_NUM_QUEUES];
/** link connect count */
unsigned long link_connect_count; unsigned long link_connect_count;
/** link disconnect count */
unsigned long link_disconnect_count; unsigned long link_disconnect_count;
}; };
/** /**
* osi_xtra_dma_stat_counters - OSI dma extra stats counters * @brief osi_xtra_dma_stat_counters - OSI DMA extra stats counters
* q_tx_pkt_n: Per Q TX packet count
* q_rx_pkt_n: Per Q RX packet count
* tx_clean_n: Per Q TX complete call count
* tx_pkt_n: Total number of tx packets count
* rx_pkt_n: Total number of rx packet count
* rx_vlan_pkt_n: Total number of VLAN RX packet count
* tx_vlan_pkt_n: Total number of VLAN TX packet count
* tx_tso_pkt_n: Total number of TSO packet count
*/ */
struct osi_xtra_dma_stat_counters { struct osi_xtra_dma_stat_counters {
/** Per Q TX packet count */
unsigned long q_tx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long q_tx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Per Q RX packet count */
unsigned long q_rx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long q_rx_pkt_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Per Q TX complete call count */
unsigned long tx_clean_n[OSI_EQOS_MAX_NUM_QUEUES]; unsigned long tx_clean_n[OSI_EQOS_MAX_NUM_QUEUES];
/** Total number of tx packets count */
unsigned long tx_pkt_n; unsigned long tx_pkt_n;
/** Total number of rx packet count */
unsigned long rx_pkt_n; unsigned long rx_pkt_n;
/** Total number of VLAN RX packet count */
unsigned long rx_vlan_pkt_n; unsigned long rx_vlan_pkt_n;
/** Total number of VLAN TX packet count */
unsigned long tx_vlan_pkt_n; unsigned long tx_vlan_pkt_n;
/** Total number of TSO packet count */
unsigned long tx_tso_pkt_n; unsigned long tx_tso_pkt_n;
}; };

111
include/osd.h
View File

@@ -23,70 +23,91 @@
#ifndef OSD_H #ifndef OSD_H
#define OSD_H #define OSD_H
/**
* @brief osd_usleep_range - sleep in micro seconds
*
* @param[in] umin: Minimum time in usecs to sleep
* @param[in] umax: Maximum time in usecs to sleep
*/
void osd_usleep_range(unsigned long umin, unsigned long umax); void osd_usleep_range(unsigned long umin, unsigned long umax);
/**
* @brief osd_msleep - sleep in milli seconds
*
* @param[in] msec: time in milli seconds
*/
void osd_msleep(unsigned int msec); void osd_msleep(unsigned int msec);
/**
* @brief osd_udelay - delay in micro seconds
*
* @param[in] usec: time in usec
*/
void osd_udelay(unsigned long usec); void osd_udelay(unsigned long usec);
/**
* @brief osd_info - logging function
*
* @param[in] priv: OSD private data
* @param[in] fmt: fragments
*/
void osd_info(void *priv, const char *fmt, ...); void osd_info(void *priv, const char *fmt, ...);
/**
* @brief osd_err - logging function
*
* @param[in] priv: OSD private data
* @param[in] fmt: fragments
*/
void osd_err(void *priv, const char *fmt, ...); void osd_err(void *priv, const char *fmt, ...);
/** /**
* osd_receive_packet - Handover received packet to network stack. * @brief osd_receive_packet - Handover received packet to network stack.
* @priv: OSD private data structure.
* @rxring: Pointer to DMA channel Rx ring.
* @chan: DMA Rx channel number.
* @dma_buf_len: Rx DMA buffer length.
* @rxpkt_cx: Received packet context.
* @rx_pkt_swcx: Received packet sw context.
* *
* Algorithm: * Algorithm:
* 1) Unmap the DMA buffer address. * 1) Unmap the DMA buffer address.
* 2) Updates socket buffer with len and ether type and handover to * 2) Updates socket buffer with len and ether type and handover to
* OS network stack. * OS network stack.
* 3) Refill the Rx ring based on threshold. * 3) Refill the Rx ring based on threshold.
* 4) Fills the rxpkt_cx->flags with the below bit fields accordingly * 4) Fills the rxpkt_cx->flags with the below bit fields accordingly
* OSI_PKT_CX_VLAN * OSI_PKT_CX_VLAN
* OSI_PKT_CX_VALID * OSI_PKT_CX_VALID
* OSI_PKT_CX_CSUM * OSI_PKT_CX_CSUM
* OSI_PKT_CX_TSO * OSI_PKT_CX_TSO
* OSI_PKT_CX_PTP * OSI_PKT_CX_PTP
* *
* Dependencies: Rx completion need to make sure that Rx descriptors * @param[in] priv: OSD private data structure.
* processed properly. * @param[in] rxring: Pointer to DMA channel Rx ring.
* @param[in] chan: DMA Rx channel number.
* @param[in] dma_buf_len: Rx DMA buffer length.
* @param[in] rxpkt_cx: Received packet context.
* @param[in] rx_pkt_swcx: Received packet sw context.
* *
* Protection: None. * @note Rx completion need to make sure that Rx descriptors processed properly.
*
* Return: None.
*/ */
void osd_receive_packet(void *priv, void *rxring, unsigned int chan, void osd_receive_packet(void *priv, void *rxring, unsigned int chan,
unsigned int dma_buf_len, void *rxpkt_cx, unsigned int dma_buf_len, void *rxpkt_cx,
void *rx_pkt_swcx); void *rx_pkt_swcx);
/** /**
* osd_transmit_complete - Transmit completion routine. * @brief osd_transmit_complete - Transmit completion routine.
* @priv: OSD private data structure.
* @buffer: Buffer address to free.
* @dmaaddr: DMA address to unmap.
* @len: Length of data.
* @tx_done_pkt_cx: Pointer to struct which has tx done status info.
* This struct has flags to indicate tx error, whether DMA address
* is mapped from paged/linear buffer, Time stamp availability,
* if TS available txdone_pkt_cx->ns stores the time stamp.
* Below are the valid bit maps set for txdone_pkt_cx->flags
* #define OSI_TXDONE_CX_PAGED_BUF OSI_BIT(0)
* #define OSI_TXDONE_CX_ERROR OSI_BIT(1)
* #define OSI_TXDONE_CX_TS OSI_BIT(2)
* *
* Algorithm: * Algorithm:
* 1) Updates stats for linux network stack. * 1) Updates stats for Linux network stack.
* 2) unmap and free the buffer DMA address and buffer. * 2) unmap and free the buffer DMA address and buffer.
* 3) Time stamp will be updated to stack if available. * 3) Time stamp will be updated to stack if available.
* *
* Dependencies: Tx completion need to make sure that Tx descriptors * @param[in] priv: OSD private data structure.
* processed properly. * @param[in] buffer: Buffer address to free.
* @param[in] dmaaddr: DMA address to unmap.
* @param[in] len: Length of data.
* @param[in] txdone_pkt_cx: Pointer to struct which has tx done status info.
* This struct has flags to indicate tx error, whether DMA address
* is mapped from paged/linear buffer, Time stamp availability,
* if TS available txdone_pkt_cx->ns stores the time stamp.
* Below are the valid bit maps set for txdone_pkt_cx->flags
* OSI_TXDONE_CX_PAGED_BUF OSI_BIT(0)
* OSI_TXDONE_CX_ERROR OSI_BIT(1)
* OSI_TXDONE_CX_TS OSI_BIT(2)
* *
* Protection: None. * @note Tx completion need to make sure that Tx descriptors processed properly.
*
* Return: None.
*/ */
void osd_transmit_complete(void *priv, void *buffer, unsigned long dmaaddr, void osd_transmit_complete(void *priv, void *buffer, unsigned long dmaaddr,
unsigned int len, void *txdone_pkt_cx); unsigned int len, void *txdone_pkt_cx);

393
include/osi_common.h
View File

@@ -23,9 +23,12 @@
#ifndef OSI_COMMON_H #ifndef OSI_COMMON_H
#define OSI_COMMON_H #define OSI_COMMON_H
/**
* @addtogroup EQOS-Helper Helper MACROS
* @{
*/
#define OSI_UNLOCKED 0x0U #define OSI_UNLOCKED 0x0U
#define OSI_LOCKED 0x1U #define OSI_LOCKED 0x1U
#define TEN_POWER_9 0x3B9ACA00U #define TEN_POWER_9 0x3B9ACA00U
#define TWO_POWER_32 0x100000000ULL #define TWO_POWER_32 0x100000000ULL
#define TWO_POWER_31 0x80000000U #define TWO_POWER_31 0x80000000U
@@ -143,7 +146,14 @@
#define H32(data) (((data) & 0xFFFFFFFF00000000UL) >> 32UL) #define H32(data) (((data) & 0xFFFFFFFF00000000UL) >> 32UL)
#define OSI_INVALID_CHAN_NUM 0xFFU #define OSI_INVALID_CHAN_NUM 0xFFU
/** @} */
/**
* @addtogroup EQOS-MAC EQOS MAC HW supported features
*
* @brief Helps in identifying the features that are set in MAC HW
* @{
*/
#define EQOS_MAC_HFR0 0x11c #define EQOS_MAC_HFR0 0x11c
#define EQOS_MAC_HFR1 0x120 #define EQOS_MAC_HFR1 0x120
#define EQOS_MAC_HFR2 0x124 #define EQOS_MAC_HFR2 0x124
@@ -185,195 +195,184 @@
#define EQOS_MAC_HFR2_TXCHCNT_MASK 0xfU #define EQOS_MAC_HFR2_TXCHCNT_MASK 0xfU
#define EQOS_MAC_HFR2_PPSOUTNUM_MASK 0x7U #define EQOS_MAC_HFR2_PPSOUTNUM_MASK 0x7U
#define EQOS_MAC_HFR2_AUXSNAPNUM_MASK 0x7U #define EQOS_MAC_HFR2_AUXSNAPNUM_MASK 0x7U
/** @} */
/** /**
* struct osi_hw_features - MAC HW supported features. * @brief struct osi_hw_features - MAC HW supported features.
* @mii_sel: It sets to 1 when 10/100 Mbps is selected as the Mode of
* Operation
* @gmii_sel: It sets to 1 when 1000 Mbps is selected as the Mode of
* Operation.
* @hd_sel: It sets to 1 when the half-duplex mode is selected.
* @pcs_sel: It sets to 1 when the TBI, SGMII, or RTBI PHY interface
* option is selected.
* @vlan_hash_en: It sets to 1 when the Enable VLAN Hash Table Based
* Filtering option is selected.
* @sma_sel: It sets to 1 when the Enable Station Management
* (MDIO Interface) option is selected.
* @rwk_sel: It sets to 1 when the Enable Remote Wake-Up Packet Detection
* option is selected.
* @mgk_sel: It sets to 1 when the Enable Magic Packet Detection option is
* selected.
* @mmc_sel: It sets to 1 when the Enable MAC Management Counters (MMC)
* option is selected.
* @arp_offld_en: It sets to 1 when the Enable IPv4 ARP Offload option is
* selected.
* @ts_sel: It sets to 1 when the Enable IEEE 1588 Timestamp Support
* option is selected.
* @eee_sel: It sets to 1 when the Enable Energy Efficient Ethernet (EEE)
* option is selected.
* @tx_coe_sel: It sets to 1 when the Enable Transmit TCP/IP Checksum
* Insertion option is selected.
* @rx_coe_sel: It sets to 1 when the Enable Receive TCP/IP Checksum Check
* option is selected.
* @mac_addr16_sel: It sets to 1 when the Enable Additional 1-31 MAC
* Address Registers option is selected.
* @mac_addr32_sel: It sets to 1 when the Enable Additional 32 MAC
* Address Registers (32-63) option is selected
* @mac_addr64_sel: It sets to 1 when the Enable Additional 64 MAC
* Address Registers (64-127) option is selected.
* @tsstssel: It sets to 1 when the Enable IEEE 1588 Timestamp Support
* option is selected.
* @sa_vlan_ins: It sets to 1 when the Enable SA and VLAN Insertion on Tx
* option is selected.
* @act_phy_sel: Active PHY Selected
* When you have multiple PHY interfaces in your configuration,
* this field indicates the sampled value of phy_intf_sel_i during
* reset de-assertion:
* 000: GMII or MII
* 001: RGMII
* 010: SGMII
* 011: TBI
* 100: RMII
* 101: RTBI
* 110: SMII
* 111: RevMII
* All Others: Reserved.
* @rx_fifo_size: MTL Receive FIFO Size
* This field contains the configured value of MTL Rx FIFO in
* bytes expressed as Log to base 2 minus 7, that is,
* Log2(RXFIFO_SIZE) -7:
* 00000: 128 bytes
* 00001: 256 bytes
* 00010: 512 bytes
* 00011: 1,024 bytes
* 00100: 2,048 bytes
* 00101: 4,096 bytes
* 00110: 8,192 bytes
* 00111: 16,384 bytes
* 01000: 32,767 bytes
* 01000: 32 KB
* 01001: 64 KB
* 01010: 128 KB
* 01011: 256 KB
* 01100-11111: Reserved.
* @tx_fifo_size: MTL Transmit FIFO Size.
* This field contains the configured value of MTL Tx FIFO in
* bytes expressed as Log to base 2 minus 7, that is,
* Log2(TXFIFO_SIZE) -7:
* 00000: 128 bytes
* 00001: 256 bytes
* 00010: 512 bytes
* 00011: 1,024 bytes
* 00100: 2,048 bytes
* 00101: 4,096 bytes
* 00110: 8,192 bytes
* 00111: 16,384 bytes
* 01000: 32 KB
* 01001: 64 KB
* 01010: 128 KB
* 01011-11111: Reserved.
* @adv_ts_hword: It set to 1 when Advance timestamping High Word selected.
* @addr_64: Address Width.
* This field indicates the configured address width:
* 00: 32
* 01: 40
* 10: 48
* 11: Reserved
* @dcb_en: It sets to 1 when DCB Feature Enable.
* @sph_en: It sets to 1 when Split Header Feature Enable.
* @tso_en: It sets to 1 when TCP Segmentation Offload Enable.
* @dma_debug_gen: It seys to 1 when DMA debug registers are enabled.
* @av_sel: It sets to 1 AV Feature Enabled.
* @hash_tbl_sz: This field indicates the size of the hash table:
* 00: No hash table
* 01: 64
* 10: 128
* 11: 256.
* @l3l4_filter_num: This field indicates the total number of L3 or L4
* filters:
* 0000: No L3 or L4 Filter
* 0001: 1 L3 or L4 Filter
* 0010: 2 L3 or L4 Filters
* ..
* 1000: 8 L3 or L4.
* @rx_q_cnt: It holds number of MTL Receive Queues.
* @tx_q_cnt: It holds number of MTL Transmit Queues.
* @rx_ch_cnt: It holds number of DMA Receive channels.
* @tx_ch_cnt: This field indicates the number of DMA Transmit channels:
* 0000: 1 DMA Tx Channel
* 0001: 2 DMA Tx Channels
* ..
* 0111: 8 DMA Tx.
* @pps_out_num: This field indicates the number of PPS outputs:
* 000: No PPS output
* 001: 1 PPS output
* 010: 2 PPS outputs
* 011: 3 PPS outputs
* 100: 4 PPS outputs
* 101-111: Reserved
* @aux_snap_num: Number of Auxiliary Snapshot Inputs
* This field indicates the number of auxiliary snapshot inputs:
* 000: No auxiliary input
* 001: 1 auxiliary input
* 010: 2 auxiliary inputs
* 011: 3 auxiliary inputs
* 100: 4 auxiliary inputs
* 101-111: Reserved
*/ */
struct osi_hw_features { struct osi_hw_features {
/* HW Feature Register0 */ /** It is set to 1 when 10/100 Mbps is selected as the Mode of
* Operation */
unsigned int mii_sel; unsigned int mii_sel;
/** It sets to 1 when 1000 Mbps is selected as the Mode of Operation */
unsigned int gmii_sel; unsigned int gmii_sel;
/** It sets to 1 when the half-duplex mode is selected */
unsigned int hd_sel; unsigned int hd_sel;
/** It sets to 1 when the TBI, SGMII, or RTBI PHY interface
* option is selected */
unsigned int pcs_sel; unsigned int pcs_sel;
/** It sets to 1 when the Enable VLAN Hash Table Based Filtering
* option is selected */
unsigned int vlan_hash_en; unsigned int vlan_hash_en;
/** It sets to 1 when the Enable Station Management (MDIO Interface)
* option is selected */
unsigned int sma_sel; unsigned int sma_sel;
/** It sets to 1 when the Enable Remote Wake-Up Packet Detection
* option is selected */
unsigned int rwk_sel; unsigned int rwk_sel;
/** It sets to 1 when the Enable Magic Packet Detection option is
* selected */
unsigned int mgk_sel; unsigned int mgk_sel;
/** It sets to 1 when the Enable MAC Management Counters (MMC) option
* is selected */
unsigned int mmc_sel; unsigned int mmc_sel;
/** It sets to 1 when the Enable IPv4 ARP Offload option is selected */
unsigned int arp_offld_en; unsigned int arp_offld_en;
/** It sets to 1 when the Enable IEEE 1588 Timestamp Support option
* is selected */
unsigned int ts_sel; unsigned int ts_sel;
/** It sets to 1 when the Enable Energy Efficient Ethernet (EEE) option
* is selected */
unsigned int eee_sel; unsigned int eee_sel;
/** It sets to 1 when the Enable Transmit TCP/IP Checksum Insertion
* option is selected */
unsigned int tx_coe_sel; unsigned int tx_coe_sel;
/** It sets to 1 when the Enable Receive TCP/IP Checksum Check option
* is selected */
unsigned int rx_coe_sel; unsigned int rx_coe_sel;
/** It sets to 1 when the Enable Additional 1-31 MAC Address Registers
* option is selected */
unsigned int mac_addr16_sel; unsigned int mac_addr16_sel;
/** It sets to 1 when the Enable Additional 32-63 MAC Address Registers
* option is selected */
unsigned int mac_addr32_sel; unsigned int mac_addr32_sel;
/** It sets to 1 when the Enable Additional 64-127 MAC Address Registers
* option is selected */
unsigned int mac_addr64_sel; unsigned int mac_addr64_sel;
/** It sets to 1 when the Enable IEEE 1588 Timestamp Support option
* is selected */
unsigned int tsstssel; unsigned int tsstssel;
/** It sets to 1 when the Enable SA and VLAN Insertion on Tx option
* is selected */
unsigned int sa_vlan_ins; unsigned int sa_vlan_ins;
/** Active PHY Selected
* When you have multiple PHY interfaces in your configuration,
* this field indicates the sampled value of phy_intf_sel_i during
* reset de-assertion:
* 000: GMII or MII
* 001: RGMII
* 010: SGMII
* 011: TBI
* 100: RMII
* 101: RTBI
* 110: SMII
* 111: RevMII
* All Others: Reserved */
unsigned int act_phy_sel; unsigned int act_phy_sel;
/* HW Feature Register1 */ /** MTL Receive FIFO Size
* This field contains the configured value of MTL Rx FIFO in bytes
* expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
* 00000: 128 bytes
* 00001: 256 bytes
* 00010: 512 bytes
* 00011: 1,024 bytes
* 00100: 2,048 bytes
* 00101: 4,096 bytes
* 00110: 8,192 bytes
* 00111: 16,384 bytes
* 01000: 32,767 bytes
* 01000: 32 KB
* 01001: 64 KB
* 01010: 128 KB
* 01011: 256 KB
* 01100-11111: Reserved */
unsigned int rx_fifo_size; unsigned int rx_fifo_size;
/** MTL Transmit FIFO Size.
* This field contains the configured value of MTL Tx FIFO in
* bytes expressed as Log to base 2 minus 7, that is,
* Log2(TXFIFO_SIZE) -7:
* 00000: 128 bytes
* 00001: 256 bytes
* 00010: 512 bytes
* 00011: 1,024 bytes
* 00100: 2,048 bytes
* 00101: 4,096 bytes
* 00110: 8,192 bytes
* 00111: 16,384 bytes
* 01000: 32 KB
* 01001: 64 KB
* 01010: 128 KB
* 01011-11111: Reserved */
unsigned int tx_fifo_size; unsigned int tx_fifo_size;
/** It set to 1 when Advance timestamping High Word selected */
unsigned int adv_ts_hword; unsigned int adv_ts_hword;
/** Address Width.
* This field indicates the configured address width:
* 00: 32
* 01: 40
* 10: 48
* 11: Reserved */
unsigned int addr_64; unsigned int addr_64;
/** It sets to 1 when DCB Feature Enable */
unsigned int dcb_en; unsigned int dcb_en;
/** It sets to 1 when Split Header Feature Enable */
unsigned int sph_en; unsigned int sph_en;
/** It sets to 1 when TCP Segmentation Offload Enable */
unsigned int tso_en; unsigned int tso_en;
/** It sets to 1 when DMA debug registers are enabled */
unsigned int dma_debug_gen; unsigned int dma_debug_gen;
/** It sets to 1 if AV Feature Enabled */
unsigned int av_sel; unsigned int av_sel;
/** This field indicates the size of the hash table:
* 00: No hash table
* 01: 64
* 10: 128
* 11: 256 */
unsigned int hash_tbl_sz; unsigned int hash_tbl_sz;
/** This field indicates the total number of L3 or L4 filters:
* 0000: No L3 or L4 Filter
* 0001: 1 L3 or L4 Filter
* 0010: 2 L3 or L4 Filters
* ..
* 1000: 8 L3 or L4 */
unsigned int l3l4_filter_num; unsigned int l3l4_filter_num;
/* HW Feature Register2 */ /** It holds number of MTL Receive Queues */
unsigned int rx_q_cnt; unsigned int rx_q_cnt;
/** It holds number of MTL Transmit Queues */
unsigned int tx_q_cnt; unsigned int tx_q_cnt;
/** It holds number of DMA Receive channels */
unsigned int rx_ch_cnt; unsigned int rx_ch_cnt;
/** This field indicates the number of DMA Transmit channels:
* 0000: 1 DMA Tx Channel
* 0001: 2 DMA Tx Channels
* ..
* 0111: 8 DMA Tx */
unsigned int tx_ch_cnt; unsigned int tx_ch_cnt;
/** This field indicates the number of PPS outputs:
* 000: No PPS output
* 001: 1 PPS output
* 010: 2 PPS outputs
* 011: 3 PPS outputs
* 100: 4 PPS outputs
* 101-111: Reserved */
unsigned int pps_out_num; unsigned int pps_out_num;
/** Number of Auxiliary Snapshot Inputs
* This field indicates the number of auxiliary snapshot inputs:
* 000: No auxiliary input
* 001: 1 auxiliary input
* 010: 2 auxiliary inputs
* 011: 3 auxiliary inputs
* 100: 4 auxiliary inputs
* 101-111: Reserved */
unsigned int aux_snap_num; unsigned int aux_snap_num;
}; };
/** /**
* osi_lock_init - Initialize lock to unlocked state. * @brief osi_lock_init - Initialize lock to unlocked state.
* @lock - Pointer to lock to be initialized
* *
* Algorithm: Set lock to unlocked state. * Algorithm: Set lock to unlocked state.
* *
* Dependencies: None. * @param[in] lock - Pointer to lock to be initialized
*
* Protection: None.
*
* Return: None.
*/ */
static inline void osi_lock_init(unsigned int *lock) static inline void osi_lock_init(unsigned int *lock)
{ {
@@ -381,17 +380,14 @@ static inline void osi_lock_init(unsigned int *lock)
} }
/** /**
* osi_lock_irq_enabled - Spin lock. Busy loop till lock is acquired. * @brief osi_lock_irq_enabled - Spin lock. Busy loop till lock is acquired.
* @lock - Pointer to lock to be acquired.
* *
* Algorithm: Atomic compare and swap operation till lock is held. * Algorithm: Atomic compare and swap operation till lock is held.
* *
* Dependencies: Does not disable irq. Do not call this API to acquire any * @param[in] lock - Pointer to lock to be acquired.
*
* @note Does not disable irq. Do not call this API to acquire any
* lock that is shared between top/bottom half. It will result in deadlock. * lock that is shared between top/bottom half. It will result in deadlock.
*
* Protection: None.
*
* Return: None.
*/ */
static inline void osi_lock_irq_enabled(unsigned int *lock) static inline void osi_lock_irq_enabled(unsigned int *lock)
{ {
@@ -407,17 +403,14 @@ static inline void osi_lock_irq_enabled(unsigned int *lock)
} }
/** /**
* osi_unlock_irq_enabled - Release lock. * @brief osi_unlock_irq_enabled - Release lock.
* @lock - Pointer to lock to be released.
* *
* Algorithm: Atomic compare and swap operation to release lock. * Algorithm: Atomic compare and swap operation to release lock.
* *
* Dependencies: Does not disable irq. Do not call this API to release any * @param[in] lock - Pointer to lock to be released.
*
* @note Does not disable irq. Do not call this API to release any
* lock that is shared between top/bottom half. * lock that is shared between top/bottom half.
*
* Protection: None.
*
* Return: None.
*/ */
static inline void osi_unlock_irq_enabled(unsigned int *lock) static inline void osi_unlock_irq_enabled(unsigned int *lock)
{ {
@@ -428,16 +421,13 @@ static inline void osi_unlock_irq_enabled(unsigned int *lock)
} }
/** /**
* osi_readl - Read a memory mapped regsiter. * @brief osi_readl - Read a memory mapped register.
* @addr: Memory mapped address.
* *
* Algorithm: None. * @param[in] addr: Memory mapped address.
* *
* Dependencies: Physical address has to be memmory mapped. * @note Physical address has to be memmory mapped.
* *
* Protection: None. * @return Data from memory mapped register - success.
*
* Return: Data from memory mapped register - success.
*/ */
static inline unsigned int osi_readl(void *addr) static inline unsigned int osi_readl(void *addr)
{ {
@@ -445,17 +435,12 @@ static inline unsigned int osi_readl(void *addr)
} }
/** /**
* osi_writel - Write to a memory mapped regsiter. * @brief osi_writel - Write to a memory mapped register.
* @val: Value to be written.
* @addr: Memory mapped address.
* *
* Algorithm: None. * @param[in] val: Value to be written.
* @param[in] addr: Memory mapped address.
* *
* Dependencies: Physical address has to be memmory mapped. * @note Physical address has to be memmory mapped.
*
* Protection: None.
*
* Return: None.
*/ */
static inline void osi_writel(unsigned int val, void *addr) static inline void osi_writel(unsigned int val, void *addr)
{ {
@@ -463,16 +448,14 @@ static inline void osi_writel(unsigned int val, void *addr)
} }
/** /**
* is_valid_mac_version - Check if read MAC IP is valid or not. * @brief is_valid_mac_version - Check if read MAC IP is valid or not.
* @mac_ver: MAC version read.
* *
* Algorithm: None. * @param[in] mac_ver: MAC version read.
* *
* Dependencies: MAC has to be out of reset. * @note MAC has to be out of reset.
* *
* Protection: None. * @retval 0 - for not Valid MAC
* * @retval 1 - for Valid MAC
* Return: 0 - for not Valid MAC, 1 - for Valid MAC
*/ */
static inline int is_valid_mac_version(unsigned int mac_ver) static inline int is_valid_mac_version(unsigned int mac_ver)
{ {
@@ -486,17 +469,17 @@ static inline int is_valid_mac_version(unsigned int mac_ver)
} }
/** /**
* osi_update_stats_counter - update value by increment passed as parameter * @brief osi_update_stats_counter - update value by increment passed
* @last_value: last value of stat counter * as parameter
* @incr: increment value
* *
* Algorithm: Check for boundary and return sum * Algorithm: Check for boundary and return sum
* *
* Dependencies: Input parameter should be only unsigned long type * @param[in] last_value: last value of stat counter
* @param[in] incr: increment value
* *
* Protection: None * @note Input parameter should be only unsigned long type
* *
* Return: unsigned long value * @return unsigned long value
*/ */
static inline unsigned long osi_update_stats_counter(unsigned long last_value, static inline unsigned long osi_update_stats_counter(unsigned long last_value,
unsigned long incr) unsigned long incr)
@@ -515,20 +498,36 @@ static inline unsigned long osi_update_stats_counter(unsigned long last_value,
} }
/** /**
* osi_get_mac_version - Reading MAC version * @brief osi_get_mac_version - Reading MAC version
* @addr: io-remap MAC base address.
* @mac_ver: holds mac version.
* *
* Algorithm: Reads MAC version and check whether its valid or not. * Algorithm: Reads MAC version and check whether its valid or not.
* *
* Dependencies: MAC has to be out of reset. * @param[in] addr: io-remap MAC base address.
* @param[in] mac_ver: holds mac version.
* *
* Protection: None * @note MAC has to be out of reset.
* *
* Return: 0 - success, -1 - failure * @retval 0 on success
* @retval -1 on failure.
*/ */
int osi_get_mac_version(void *addr, unsigned int *mac_ver); int osi_get_mac_version(void *addr, unsigned int *mac_ver);
/**
* @brief osi_get_hw_features - Reading MAC HW features
*
* @param[in] base: io-remap MAC base address.
* @param[in] hw_feat: holds the supported features of the hardware.
*
* @note MAC has to be out of reset.
*/
void osi_get_hw_features(void *base, struct osi_hw_features *hw_feat); void osi_get_hw_features(void *base, struct osi_hw_features *hw_feat);
/**
* @brief osi_memset - osi memset
*
* @param[in] s: source that need to be set
* @param[in] c: value to fill in source
* @param[in] count: first n bytes of source
*
*/
void osi_memset(void *s, unsigned int c, unsigned long count); void osi_memset(void *s, unsigned int c, unsigned long count);
#endif /* OSI_COMMON_H */ #endif /* OSI_COMMON_H */

1085
include/osi_core.h
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File diff suppressed because it is too large Load Diff

646
include/osi_dma.h
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File diff suppressed because it is too large Load Diff

43
include/osi_dma_txrx.h
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@@ -23,16 +23,43 @@
#ifndef OSI_DMA_TXRX_H #ifndef OSI_DMA_TXRX_H
#define OSI_DMA_TXRX_H #define OSI_DMA_TXRX_H
/**
* @addtogroup EQOS_Help Descriptor Helper MACROS
*
* @brief Helper macros for defining Tx/Rx descriptor count
* @{
*/
#define TX_DESC_CNT 256U #define TX_DESC_CNT 256U
#define RX_DESC_CNT 256U #define RX_DESC_CNT 256U
/** @} */
/** TSO Header length divisor */
#define OSI_TSO_HDR_LEN_DIVISOR 4U #define OSI_TSO_HDR_LEN_DIVISOR 4U
/**
* @addtogroup EQOS_Help1 Helper MACROS for descriptor index operations
*
* @brief Helper macros for incrementing or decrementing Tx/Rx descriptor index
* @{
*/
/** Increment the tx descriptor index */
#define INCR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (TX_DESC_CNT - 1U)) #define INCR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (TX_DESC_CNT - 1U))
/** Decrement the tx descriptor index */
#define DECR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (TX_DESC_CNT - 1U)) #define DECR_TX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (TX_DESC_CNT - 1U))
/** Increment the rx descriptor index */
#define INCR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (RX_DESC_CNT - 1U)) #define INCR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) + (i)) & (RX_DESC_CNT - 1U))
/** Decrement the rx descriptor index */
#define DECR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (RX_DESC_CNT - 1U)) #define DECR_RX_DESC_INDEX(idx, i) ((idx) = ((idx) - (i)) & (RX_DESC_CNT - 1U))
/** @} */
/**
* @addtogroup EQOS_RxDesc Receive Descriptors bit fields
*
* @brief These macros are used to check the value in specific bit fields of
* the descriptor. The fields in the descriptor are mapped as
* defined in the HW manual
* @{
*/
#define RDES3_OWN OSI_BIT(31) #define RDES3_OWN OSI_BIT(31)
#define RDES3_CTXT OSI_BIT(30) #define RDES3_CTXT OSI_BIT(30)
#define RDES3_IOC OSI_BIT(30) #define RDES3_IOC OSI_BIT(30)
@@ -51,17 +78,27 @@
#define RDES3_RS0V OSI_BIT(25) #define RDES3_RS0V OSI_BIT(25)
#define RDES3_RS1V OSI_BIT(26) #define RDES3_RS1V OSI_BIT(26)
#define RDES0_OVT 0x0000FFFFU #define RDES0_OVT 0x0000FFFFU
#define RDES1_TSA OSI_BIT(14) /* Timestamp available */ #define RDES1_TSA OSI_BIT(14)
#define RDES1_TD OSI_BIT(15) /* Timestamp Dropped */ #define RDES1_TD OSI_BIT(15)
#define RDES1_IPCE OSI_BIT(7) #define RDES1_IPCE OSI_BIT(7)
#define RDES1_IPCB OSI_BIT(6) #define RDES1_IPCB OSI_BIT(6)
#define RDES1_IPHE OSI_BIT(3) #define RDES1_IPHE OSI_BIT(3)
/** @} */
/** Error Summary bits for Received packet */
#define RDES3_ES_BITS \ #define RDES3_ES_BITS \
(RDES3_ERR_CRC | RDES3_ERR_GP | RDES3_ERR_WD | \ (RDES3_ERR_CRC | RDES3_ERR_GP | RDES3_ERR_WD | \
RDES3_ERR_ORUN | RDES3_ERR_RE | RDES3_ERR_DRIB) RDES3_ERR_ORUN | RDES3_ERR_RE | RDES3_ERR_DRIB)
/**
* @addtogroup EQOS_TxDesc Transmit Descriptors bit fields
*
* @brief These macros are used to check the value in specific bit fields of
* the descriptor. The fields in the descriptor are mapped as
* defined in the HW manual
* @{
*/
#define TDES2_IOC OSI_BIT(31) #define TDES2_IOC OSI_BIT(31)
#define TDES2_MSS_MASK 0x3FFFU #define TDES2_MSS_MASK 0x3FFFU
#define TDES3_OWN OSI_BIT(31) #define TDES3_OWN OSI_BIT(31)
@@ -95,7 +132,9 @@
*/ */
#define TDES2_VTIR ((unsigned int)0x2 << 14U) #define TDES2_VTIR ((unsigned int)0x2 << 14U)
#define TDES2_TTSE ((unsigned int)0x1 << 30U) #define TDES2_TTSE ((unsigned int)0x1 << 30U)
/** @} */
/** Error Summary bits for Transmitted packet */
#define TDES3_ES_BITS (TDES3_IP_HEADER_ERR | \ #define TDES3_ES_BITS (TDES3_IP_HEADER_ERR | \
TDES3_UNDER_FLOW_ERR | \ TDES3_UNDER_FLOW_ERR | \
TDES3_EXCESSIVE_DEF_ERR | \ TDES3_EXCESSIVE_DEF_ERR | \

11
osi/common/osi_common.c
View File

@@ -23,17 +23,6 @@
#include <osi_core.h> #include <osi_core.h>
#include <osd.h> #include <osd.h>
/**
* osi_get_hw_features: Get MAC Hardware features from features registers
* @osi: OSI private data structure.
*
* Algorithm: Reads HW features from HW registers and populate those
* in hw features structure.
*
* Dependencies: CAR reset should be success before calling this function
*
* Return: None
*/
void osi_get_hw_features(void *base, struct osi_hw_features *hw_feat) void osi_get_hw_features(void *base, struct osi_hw_features *hw_feat)
{ {
unsigned int mac_hfr0; unsigned int mac_hfr0;

999
osi/core/eqos_core.c
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File diff suppressed because it is too large Load Diff

104
osi/core/eqos_core.h
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@@ -23,8 +23,12 @@
#ifndef EQOS_CORE_H_ #ifndef EQOS_CORE_H_
#define EQOS_CORE_H_ #define EQOS_CORE_H_
/* These bits control the threshold (fill-level of Rx queue) at which /**
* @addtogroup EQOS-FC Flow Control Threshold Macros
*
* @brief These bits control the threshold (fill-level of Rx queue) at which
* the flow control is asserted or de-asserted * the flow control is asserted or de-asserted
* @{
*/ */
#define FULL_MINUS_1_5K (unsigned int)1 #define FULL_MINUS_1_5K (unsigned int)1
#define FULL_MINUS_2_K (unsigned int)2 #define FULL_MINUS_2_K (unsigned int)2
@@ -34,20 +38,26 @@
#define FULL_MINUS_6_K (unsigned int)10 #define FULL_MINUS_6_K (unsigned int)10
#define FULL_MINUS_10_K (unsigned int)18 #define FULL_MINUS_10_K (unsigned int)18
#define FULL_MINUS_16_K (unsigned int)30 #define FULL_MINUS_16_K (unsigned int)30
/** @} */
/** /**
* MTL queue operation mode * @addtogroup EQOS-MTLQ MTL queue operation mode
* EQOS_MTL_QUEUE_DISABLED - queue disabled *
* EQOS_MTL_QUEUE_QAVB - queue in AVB mode * @brief MTL queue operation mode options
* EQOS_MTL_QUEUE_QDCB - queue in DCB mode * @{
* EQOS_MTL_QUEUE_QGENERIC - queue in gerneric mode
*/ */
#define EQOS_MTL_QUEUE_DISABLED 0x0U #define EQOS_MTL_QUEUE_DISABLED 0x0U
#define EQOS_MTL_QUEUE_AVB 0x1U #define EQOS_MTL_QUEUE_AVB 0x1U
#define EQOS_MTL_QUEUE_DCB 0x2U #define EQOS_MTL_QUEUE_DCB 0x2U
#define EQOS_MTL_QUEUE_GENERIC 0x3U #define EQOS_MTL_QUEUE_GENERIC 0x3U
/** @} */
/* MDC Clock Selection define*/ /**
* @addtogroup EQOS-MDC MDC Clock Selection defines
*
* @brief MDC Clock defines
* @{
*/
#define EQOS_CSR_60_100M 0x0 /* MDC = clk_csr/42 */ #define EQOS_CSR_60_100M 0x0 /* MDC = clk_csr/42 */
#define EQOS_CSR_100_150M 0x1 /* MDC = clk_csr/62 */ #define EQOS_CSR_100_150M 0x1 /* MDC = clk_csr/62 */
#define EQOS_CSR_20_35M 0x2 /* MDC = clk_csr/16 */ #define EQOS_CSR_20_35M 0x2 /* MDC = clk_csr/16 */
@@ -56,11 +66,24 @@
#define EQOS_CSR_250_300M 0x5 /* MDC = clk_csr/124 */ #define EQOS_CSR_250_300M 0x5 /* MDC = clk_csr/124 */
#define EQOS_CSR_300_500M 0x6 /* MDC = clk_csr/204 */ #define EQOS_CSR_300_500M 0x6 /* MDC = clk_csr/204 */
#define EQOS_CSR_500_800M 0x7 /* MDC = clk_csr/324 */ #define EQOS_CSR_500_800M 0x7 /* MDC = clk_csr/324 */
/** @} */
/**
* @addtogroup EQOS-SIZE SIZE calculation helper Macros
*
* @brief SIZE calculation defines
* @{
*/
#define FIFO_SIZE_B(x) (x) #define FIFO_SIZE_B(x) (x)
#define FIFO_SIZE_KB(x) ((x) * 1024U) #define FIFO_SIZE_KB(x) ((x) * 1024U)
/** @} */
/* per queue fifo size programmable value */ /**
* @addtogroup EQOS-QUEUE QUEUE fifo size programmable values
*
* @brief Queue FIFO size programmable values
* @{
*/
#define EQOS_256 0x00U #define EQOS_256 0x00U
#define EQOS_512 0x01U #define EQOS_512 0x01U
#define EQOS_1K 0x03U #define EQOS_1K 0x03U
@@ -71,8 +94,14 @@
#define EQOS_16K 0x3FU #define EQOS_16K 0x3FU
#define EQOS_32K 0x7FU #define EQOS_32K 0x7FU
#define EQOS_36K 0x8FU #define EQOS_36K 0x8FU
/** @} */
/* EQOS HW Registers */ /**
* @addtogroup EQOS-HW Hardware Register offsets
*
* @brief EQOS HW register offsets
* @{
*/
#define EQOS_5_00_MAC_ARPPA 0x0210 #define EQOS_5_00_MAC_ARPPA 0x0210
#define EQOS_4_10_MAC_ARPPA 0x0AE0 #define EQOS_4_10_MAC_ARPPA 0x0AE0
#define EQOS_DMA_SBUS 0x1004 #define EQOS_DMA_SBUS 0x1004
@@ -120,8 +149,14 @@
#define EQOS_MAC_STSUR 0x0B10 #define EQOS_MAC_STSUR 0x0B10
#define EQOS_MAC_STNSUR 0x0B14 #define EQOS_MAC_STNSUR 0x0B14
#define EQOS_MAC_TAR 0x0B18 #define EQOS_MAC_TAR 0x0B18
/** @} */
/* EQOS MTL registers*/ /**
* @addtogroup EQOS-MTL MTL HW Register offsets
*
* @brief EQOS MTL HW Register offsets
* @{
*/
#define EQOS_MTL_CHX_TX_OP_MODE(x) ((0x0040U * (x)) + 0x0D00U) #define EQOS_MTL_CHX_TX_OP_MODE(x) ((0x0040U * (x)) + 0x0D00U)
#define EQOS_MTL_TXQ_QW(x) ((0x0040U * (x)) + 0x0D18U) #define EQOS_MTL_TXQ_QW(x) ((0x0040U * (x)) + 0x0D18U)
#define EQOS_MTL_CHX_RX_OP_MODE(x) ((0x0040U * (x)) + 0x0D30U) #define EQOS_MTL_CHX_RX_OP_MODE(x) ((0x0040U * (x)) + 0x0D30U)
@@ -131,14 +166,26 @@
#define EQOS_MTL_TXQ_ETS_LCR(x) ((0x0040U * (x)) + 0x0D24U) #define EQOS_MTL_TXQ_ETS_LCR(x) ((0x0040U * (x)) + 0x0D24U)
#define EQOS_MTL_RXQ_DMA_MAP0 0x0C30 #define EQOS_MTL_RXQ_DMA_MAP0 0x0C30
#define EQOS_MTL_OP_MODE 0x0C00 #define EQOS_MTL_OP_MODE 0x0C00
/** @} */
/* EQOS Wrapper registers*/ /**
* @addtogroup EQOS-Wrapper EQOS Wrapper HW Register offsets
*
* @brief EQOS Wrapper register offsets
* @{
*/
#define EQOS_PAD_AUTO_CAL_CFG 0x8804U #define EQOS_PAD_AUTO_CAL_CFG 0x8804U
#define EQOS_PAD_AUTO_CAL_STAT 0x880CU #define EQOS_PAD_AUTO_CAL_STAT 0x880CU
#define EQOS_PAD_CRTL 0x8800U #define EQOS_PAD_CRTL 0x8800U
#define EQOS_CLOCK_CTRL_0 0x8000U #define EQOS_CLOCK_CTRL_0 0x8000U
/** @} */
/* EQOS Register BIT Masks */ /**
* @addtogroup HW Register BIT values
*
* @brief consists of corresponding EQOS MAC, MTL register bit values
* @{
*/
#define EQOS_PAD_AUTO_CAL_CFG_ENABLE OSI_BIT(29) #define EQOS_PAD_AUTO_CAL_CFG_ENABLE OSI_BIT(29)
#define EQOS_PAD_AUTO_CAL_CFG_START OSI_BIT(31) #define EQOS_PAD_AUTO_CAL_CFG_START OSI_BIT(31)
#define EQOS_PAD_AUTO_CAL_STAT_ACTIVE OSI_BIT(31) #define EQOS_PAD_AUTO_CAL_STAT_ACTIVE OSI_BIT(31)
@@ -335,11 +382,25 @@
#define EQOS_DMA_CHX_STATUS_RPS OSI_BIT(8) #define EQOS_DMA_CHX_STATUS_RPS OSI_BIT(8)
#define EQOS_DMA_CHX_STATUS_RWT OSI_BIT(9) #define EQOS_DMA_CHX_STATUS_RWT OSI_BIT(9)
#define EQOS_DMA_CHX_STATUS_FBE OSI_BIT(10) #define EQOS_DMA_CHX_STATUS_FBE OSI_BIT(10)
/** @} */
/**
* @brief update_ehfc_rfa_rfd - Update EHFC, RFD and RSA values
*
* Algorithm: Calculates and stores the RSD (Threshold for Deactivating
* Flow control) and RSA (Threshold for Activating Flow Control) values
* based on the Rx FIFO size and also enables HW flow control
*
* @param[in] rx_fifo: Rx FIFO size.
* @param[in] value: Stores RFD and RSA values
*/
void update_ehfc_rfa_rfd(unsigned int rx_fifo, unsigned int *value); void update_ehfc_rfa_rfd(unsigned int rx_fifo, unsigned int *value);
/* Below macros are used for periodic reg validation for functional safety. /**
* HW register mask - to mask reserved and self-clearing bits * @addtogroup EQOS-Safety-Register EQOS Safety Register Mask
*
* @brief EQOS HW register masks and index
* @{
*/ */
#define EQOS_MAC_MCR_MASK 0xFFFFFF7FU #define EQOS_MAC_MCR_MASK 0xFFFFFF7FU
#define EQOS_MAC_PFR_MASK 0x803107FFU #define EQOS_MAC_PFR_MASK 0x803107FFU
@@ -398,21 +459,22 @@ void update_ehfc_rfa_rfd(unsigned int rx_fifo, unsigned int *value);
#define EQOS_MTL_CH3_RX_OP_MODE_IDX 29U #define EQOS_MTL_CH3_RX_OP_MODE_IDX 29U
#define EQOS_DMA_SBUS_IDX 30U #define EQOS_DMA_SBUS_IDX 30U
#define EQOS_MAX_CORE_SAFETY_REGS 31U #define EQOS_MAX_CORE_SAFETY_REGS 31U
/** @} */
/** /**
* struct core_func_safety - Struct used to store last written values of * @brief core_func_safety - Struct used to store last written values of
* critical core HW registers. * critical core HW registers.
* @reg_addr: Array of reg MMIO addresses (base of EQoS + offset of reg)
* @reg_mask: Array of bit-mask value of each corresponding reg (used to
* ignore self-clearing/reserved bits in reg).
* @reg_val: Array of value stored in each corresponding register.
* @core_safety_lock: OSI lock variable used to protect writes to reg while
* validation is in-progress.
*/ */
struct core_func_safety { struct core_func_safety {
/** Array of reg MMIO addresses (base of EQoS + offset of reg) */
void *reg_addr[EQOS_MAX_CORE_SAFETY_REGS]; void *reg_addr[EQOS_MAX_CORE_SAFETY_REGS];
/** Array of bit-mask value of each corresponding reg
* (used to ignore self-clearing/reserved bits in reg) */
unsigned int reg_mask[EQOS_MAX_CORE_SAFETY_REGS]; unsigned int reg_mask[EQOS_MAX_CORE_SAFETY_REGS];
/** Array of value stored in each corresponding register */
unsigned int reg_val[EQOS_MAX_CORE_SAFETY_REGS]; unsigned int reg_val[EQOS_MAX_CORE_SAFETY_REGS];
/** OSI lock variable used to protect writes to reg while
* validation is in-progress */
unsigned int core_safety_lock; unsigned int core_safety_lock;
}; };
#endif #endif

49
osi/core/eqos_mmc.c
View File

@@ -27,22 +27,21 @@
#include "eqos_core.h" #include "eqos_core.h"
/** /**
* update_mmc_val - function to read resgister and return vlaue to callee * @brief update_mmc_val - function to read register and return value to callee
* *
* @osi_core: OSI core private data structure. * Algorithm: Read the registers, check for boundary, if more, reset
* @last_vlaue: previous value of stats variable. * counters else return same to caller.
* @offset: HW register offset
* *
* Algorithm: Read the registers, check for boundary, if more, reset * @param[in] osi_core: OSI core private data structure.
* counters else return same to caller. * @param[in] last_value: previous value of stats variable.
* @param[in] offset: HW register offset
* *
* Dependencies: * @note
* 1) MAC should be init and started. see osi_start_mac() * 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated * 2) osi_core->osd should be populated
* *
* Protection: None * @retval 0 on success
* * @retval -1 on failure
* Return: unsigned value
*/ */
static inline unsigned long update_mmc_val(struct osi_core_priv_data *osi_core, static inline unsigned long update_mmc_val(struct osi_core_priv_data *osi_core,
unsigned long last_value, unsigned long last_value,
@@ -66,19 +65,14 @@ static inline unsigned long update_mmc_val(struct osi_core_priv_data *osi_core,
} }
/** /**
* eqos_reset_mmc - To reset MMC registers and ether_mmc_counter structure * @brief eqos_reset_mmc - To reset MMC registers and ether_mmc_counter
* variable * structure variable
* @osi_core: OSI core private data structure.
* *
* Algorithm: reset HW counter and structure variable value. * @param[in] osi_core: OSI core private data structure.
* *
* Dependencies: * @note
* 1) MAC should be init and started. see osi_start_mac() * 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated * 2) osi_core->osd should be populated
*
* Protection: None
*
* Return: None
*/ */
void eqos_reset_mmc(struct osi_core_priv_data *osi_core) void eqos_reset_mmc(struct osi_core_priv_data *osi_core)
{ {
@@ -92,20 +86,17 @@ void eqos_reset_mmc(struct osi_core_priv_data *osi_core)
} }
/** /**
* eqos_read_mmc - To read MMC registers and ether_mmc_counter structure * @brief eqos_read_mmc - To read MMC registers and ether_mmc_counter structure
* variable * variable
* @osi_core: OSI core private data structure.
* *
* Algorithm: Pass register offset and old value to helper function and * Algorithm: Pass register offset and old value to helper function and
* update structure. * update structure.
* *
* Dependencies: * @param[in] osi_core: OSI core private data structure.
*
* @note
* 1) MAC should be init and started. see osi_start_mac() * 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated * 2) osi_core->osd should be populated
*
* Protection: None
*
* Return: None
*/ */
void eqos_read_mmc(struct osi_core_priv_data *osi_core) void eqos_read_mmc(struct osi_core_priv_data *osi_core)
{ {

31
osi/core/eqos_mmc.h
View File

@@ -23,6 +23,12 @@
#ifndef EQOS_MMC_H_ #ifndef EQOS_MMC_H_
#define EQOS_MMC_H_ #define EQOS_MMC_H_
/**
* @addtogroup EQOS-MMC MMC HW register offsets
*
* @brief MMC HW register offsets
* @{
*/
#define MMC_TXOCTETCOUNT_GB 0x00714 #define MMC_TXOCTETCOUNT_GB 0x00714
#define MMC_TXPACKETCOUNT_GB 0x00718 #define MMC_TXPACKETCOUNT_GB 0x00718
#define MMC_TXBROADCASTPACKETS_G 0x0071c #define MMC_TXBROADCASTPACKETS_G 0x0071c
@@ -103,7 +109,32 @@
#define MMC_RXTCP_ERR_OCTETS 0x0087c #define MMC_RXTCP_ERR_OCTETS 0x0087c
#define MMC_RXICMP_GD_OCTETS 0x00880 #define MMC_RXICMP_GD_OCTETS 0x00880
#define MMC_RXICMP_ERR_OCTETS 0x00884 #define MMC_RXICMP_ERR_OCTETS 0x00884
/** @} */
/**
* @brief eqos_read_mmc - To read MMC registers and ether_mmc_counter structure
* variable
*
* Algorithm: Pass register offset and old value to helper function and
* update structure.
*
* @param[in] osi_core: OSI core private data structure.
*
* @note
* 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated
*/
void eqos_read_mmc(struct osi_core_priv_data *osi_core); void eqos_read_mmc(struct osi_core_priv_data *osi_core);
/**
* @brief eqos_reset_mmc - To reset MMC registers and ether_mmc_counter
* structure variable
*
* @param[in] osi_core: OSI core private data structure.
*
* @note
* 1) MAC should be init and started. see osi_start_mac()
* 2) osi_core->osd should be populated
*/
void eqos_reset_mmc(struct osi_core_priv_data *osi_core); void eqos_reset_mmc(struct osi_core_priv_data *osi_core);
#endif #endif

50
osi/core/osi_core.c
View File

@@ -23,6 +23,11 @@
#include <osi_core.h> #include <osi_core.h>
#include <osd.h> #include <osd.h>
/**
* @addtogroup MDIO Macros
* @brief Helper MACROS for MDIO
* @{
*/
#define MAC_MDIO_ADDRESS 0x200 #define MAC_MDIO_ADDRESS 0x200
#define MAC_GMII_BUSY 0x00000001U #define MAC_GMII_BUSY 0x00000001U
@@ -34,7 +39,18 @@
#define MDIO_PHY_ADDR_SHIFT 21U #define MDIO_PHY_ADDR_SHIFT 21U
#define MDIO_PHY_REG_SHIFT 16U #define MDIO_PHY_REG_SHIFT 16U
#define MDIO_MII_WRITE OSI_BIT(2) #define MDIO_MII_WRITE OSI_BIT(2)
/** @} */
/**
* @brief poll_for_mii_idle Query the status of an ongoing DMA transfer
*
* @param[in] osi_core: OSI Core private data structure.
*
* @note MAC needs to be out of reset and proper clock configured.
*
* @retval 0 on Success
* @retval -1 on Failure
*/
static inline int poll_for_mii_idle(struct osi_core_priv_data *osi_core) static inline int poll_for_mii_idle(struct osi_core_priv_data *osi_core)
{ {
unsigned int retry = 1000; unsigned int retry = 1000;
@@ -645,20 +661,19 @@ int osi_set_systime_to_mac(struct osi_core_priv_data *osi_core,
} }
/** /**
* div_u64_rem - updates remainder and returns Quotient *@brief div_u64_rem - updates remainder and returns Quotient
* @dividend: Dividend value
* @divisor: Divisor value
* @remainder: Remainder
* *
* Algorithm: Dividend will be divided by divisor and stores the * Algorithm: Dividend will be divided by divisor and stores the
* remainder value and returns quotient * remainder value and returns quotient
* *
* Dependencies: MAC IP should be out of reset * @param[in] dividend: Dividend value
* and need to be initialized as the requirements * @param[in] divisor: Divisor value
* @param[out] remain: Remainder
* *
* Protection: None * @note MAC IP should be out of reset and need to be initialized as the
* requirements
* *
* Return: Quotient * @returns Quotient
*/ */
static inline unsigned long div_u64_rem(unsigned long dividend, static inline unsigned long div_u64_rem(unsigned long dividend,
unsigned long divisor, unsigned long divisor,
@@ -676,18 +691,15 @@ static inline unsigned long div_u64_rem(unsigned long dividend,
} }
/** /**
* div_u64 - Calls a function which returns quotient * @brief div_u64 - Calls a function which returns quotient
* @dividend: Dividend
* @divisor: Divisor
* *
* Algorithm: Calls a function which returns quotient. * @param[in] dividend: Dividend
* @param[in] divisor: Divisor
* *
* Dependencies: MAC IP should be out of reset * @note MAC IP should be out of reset and need to be initialized as the
* and need to be initialized as the requirements. * requirements.
* *
* Protection: None * @returns Quotient
*
* Return: Quotient
*/ */
static inline unsigned long div_u64(unsigned long dividend, static inline unsigned long div_u64(unsigned long dividend,
unsigned long divisor) unsigned long divisor)

355
osi/dma/eqos_dma.c
View File

@@ -24,15 +24,15 @@
#include <osi_dma.h> #include <osi_dma.h>
#include "eqos_dma.h" #include "eqos_dma.h"
/**
* @brief eqos_dma_safety_config - EQOS MAC DMA safety configuration
*/
static struct dma_func_safety eqos_dma_safety_config; static struct dma_func_safety eqos_dma_safety_config;
/** /**
* eqos_dma_safety_writel - Write to safety critical register. * @brief Write to safety critical register.
* @val: Value to be written.
* @addr: memory mapped register address to be written to.
* @idx: Index of register corresponding to enum func_safety_dma_regs.
* *
* Algorithm: * Algorithm:
* 1) Acquire RW lock, so that eqos_validate_dma_regs does not run while * 1) Acquire RW lock, so that eqos_validate_dma_regs does not run while
* updating the safety critical register. * updating the safety critical register.
* 2) call osi_writel() to actually update the memory mapped register. * 2) call osi_writel() to actually update the memory mapped register.
@@ -40,12 +40,11 @@ static struct dma_func_safety eqos_dma_safety_config;
* this latest value will be compared when eqos_validate_dma_regs is * this latest value will be compared when eqos_validate_dma_regs is
* scheduled. * scheduled.
* *
* Dependencies: * @param[in] val: Value to be written.
* 1) MAC has to be out of reset, and clocks supplied. * @param[in] addr: memory mapped register address to be written to.
* @param[in] idx: Index of register corresponding to enum func_safety_dma_regs.
* *
* Protection: None. * @note MAC has to be out of reset, and clocks supplied.
*
* Return: None.
*/ */
static inline void eqos_dma_safety_writel(unsigned int val, void *addr, static inline void eqos_dma_safety_writel(unsigned int val, void *addr,
unsigned int idx) unsigned int idx)
@@ -59,21 +58,16 @@ static inline void eqos_dma_safety_writel(unsigned int val, void *addr,
} }
/** /**
* eqos_dma_safety_init - Initialize the eqos_dma_safety_config. * @brief Initialize the eqos_dma_safety_config.
* @base_addr: Base address of memory mapped register space.
* *
* Algorithm: Populate the list of safety critical registers and provide * @param[in] osi_dma: OSI DMA private data structure.
*
* Algorithm: Populate the list of safety critical registers and provide
* 1) the address of the register * 1) the address of the register
* 2) Register mask (to ignore reserved/self-critical bits in the reg). * 2) Register mask (to ignore reserved/self-critical bits in the reg).
* See @eqos_validate_dma_regs which can be ivoked periodically to compare * See eqos_validate_dma_regs which can be ivoked periodically to compare
* the last written value to this register vs the actual value read when * the last written value to this register vs the actual value read when
* eqos_validate_dma_regs is scheduled. * eqos_validate_dma_regs is scheduled.
*
* Dependencies: None
*
* Protection: None
*
* Return: None
*/ */
static void eqos_dma_safety_init(struct osi_dma_priv_data *osi_dma) static void eqos_dma_safety_init(struct osi_dma_priv_data *osi_dma)
{ {
@@ -131,21 +125,22 @@ static void eqos_dma_safety_init(struct osi_dma_priv_data *osi_dma)
} }
/** /**
* eqos_validate_dma_regs - Read-validate HW registers for functional safety. * @brief Read-validate HW registers for functional safety.
* @osi_dma: OSI dma private data structure. *
* Algorithm: Reads pre-configured list of MAC/MTL configuration registers * Algorithm: Reads pre-configured list of MAC/MTL configuration registers
* and compares with last written value for any modifications. * and compares with last written value for any modifications.
* *
* Dependencies: * @param[in] osi_dma: OSI DMA private data structure.
*
* @note
* 1) MAC has to be out of reset. * 1) MAC has to be out of reset.
* 2) osi_hw_dma_init has to be called. Internally this would initialize * 2) osi_hw_dma_init has to be called. Internally this would initialize
* the safety_config (see @osi_dma_priv_data) based on MAC version and * the safety_config (see osi_dma_priv_data) based on MAC version and
* which specific registers needs to be validated periodically. * which specific registers needs to be validated periodically.
* 3) Invoke this call iff (osi_dma_priv_data->safety_config != OSI_NULL) * 3) Invoke this call iff (osi_dma_priv_data->safety_config != OSI_NULL)
* *
* Protection: None * @retval 0 on success
* * @retval -1 on failure.
* Return: 0 - success, -1 - failure
*/ */
static int eqos_validate_dma_regs(struct osi_dma_priv_data *osi_dma) static int eqos_validate_dma_regs(struct osi_dma_priv_data *osi_dma)
{ {
@@ -180,21 +175,16 @@ static int eqos_validate_dma_regs(struct osi_dma_priv_data *osi_dma)
} }
/** /**
* eqos_disable_chan_tx_intr - Disables DMA Tx channel interrupts. * @brief eqos_disable_chan_tx_intr - Disables DMA Tx channel interrupts.
* @addr: MAC base address.
* @chan: DMA Tx channel number.
* *
* Algorithm: Disables Tx interrupts at wrapper level. * @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] chan: DMA Tx channel number.
* *
* Dependencies: * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 1) MAC needs to be out of reset and proper clocks need to be configured. * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * 3) Mapping of physical IRQ line to DMA channel need to be maintained at
* 3) Mapping of physical IRQ line to DMA channel need to be maintained at * OSDependent layer and pass corresponding channel number.
* OSDependent layer and pass corresponding channel number.
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_disable_chan_tx_intr(void *addr, unsigned int chan) static void eqos_disable_chan_tx_intr(void *addr, unsigned int chan)
{ {
@@ -206,21 +196,16 @@ static void eqos_disable_chan_tx_intr(void *addr, unsigned int chan)
} }
/** /**
* eqos_enable_chan_tx_intr - Enable Tx channel interrupts. * @brief eqos_enable_chan_tx_intr - Enable Tx channel interrupts.
* @addr: MAC base address.
* @chan: DMA Tx channel number.
* *
* Algorithm: Enables EQOS DMA tx channel interrupts. * @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] chan: DMA Tx channel number.
* *
* Dependencies: * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 1) MAC needs to be out of reset and proper clocks need to be configured. * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * 3) Mapping of physical IRQ line to DMA channel need to be maintained at
* 3) Mapping of physical IRQ line to DMA channel need to be maintained at * OSDependent layer and pass corresponding channel number.
* OSDependent layer and pass corresponding channel number.
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_enable_chan_tx_intr(void *addr, unsigned int chan) static void eqos_enable_chan_tx_intr(void *addr, unsigned int chan)
{ {
@@ -232,19 +217,16 @@ static void eqos_enable_chan_tx_intr(void *addr, unsigned int chan)
} }
/** /**
* eqos_disable_chan_rx_intr - Disable Rx channel interrupts. * @brief eqos_disable_chan_rx_intr - Disable Rx channel interrupts.
* @addr: MAC base address.
* @chan: DMA Rx channel number.
* *
* Algorithm: Disables EQOS DMA rx channel interrupts. * @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] chan: DMA Rx channel number.
* *
* Dependencies: * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 1) MAC needs to be out of reset and proper clocks need to be configured. * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * 3) Mapping of physical IRQ line to DMA channel need to be maintained at
* 3) Mapping of physical IRQ line to DMA channel need to be maintained at * OSDependent layer and pass corresponding channel number.
* OSDependent layer and pass corresponding channel number.
* Protection: None.
* Return: None.
*/ */
static void eqos_disable_chan_rx_intr(void *addr, unsigned int chan) static void eqos_disable_chan_rx_intr(void *addr, unsigned int chan)
{ {
@@ -256,19 +238,14 @@ static void eqos_disable_chan_rx_intr(void *addr, unsigned int chan)
} }
/** /**
* eqos_enable_chan_rx_intr - Enable Rx channel interrupts. * @brief eqos_enable_chan_rx_intr - Enable Rx channel interrupts.
* @addr: MAC base address.
* @chan: DMA Rx channel number.
* *
* Algorithm: Enables EQOS DMA Rx channel interrupts. * @param[in] addr: Base address indicating the start of
* memory mapped IO region of the MAC.
* @param[in] chan: DMA Rx channel number.
* *
* Dependencies: * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 1) MAC needs to be out of reset and proper clocks need to be configured. * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_enable_chan_rx_intr(void *addr, unsigned int chan) static void eqos_enable_chan_rx_intr(void *addr, unsigned int chan)
{ {
@@ -280,21 +257,18 @@ static void eqos_enable_chan_rx_intr(void *addr, unsigned int chan)
} }
/** /**
* eqos_clear_tx_intr - Handle EQOS DMA Tx channel interrupts. * @brief eqos_clear_tx_intr - Handle EQOS DMA Tx channel interrupts.
* @addr: MAC base address.
* @chan: DMA Tx channel number.
* *
* Algorithm: Clear DMA Tx interrupt source at wrapper and DMA level. * Algorithm: Clear DMA Tx interrupt source at wrapper and DMA level.
* *
* Dependencies: * @param[in] addr: Base address indicating the start of
* 1) MAC needs to be out of reset and proper clocks need to be configured. * memory mapped IO region of the MAC.
* @param[in] chan: DMA Tx channel number.
*
* @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 3) Mapping of physical IRQ line to DMA channel need to be maintained at * 3) Mapping of physical IRQ line to DMA channel need to be maintained at
* OSDependent layer and pass corresponding channel number. * OSDependent layer and pass corresponding channel number.
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_clear_tx_intr(void *addr, unsigned int chan) static void eqos_clear_tx_intr(void *addr, unsigned int chan)
{ {
@@ -310,21 +284,18 @@ static void eqos_clear_tx_intr(void *addr, unsigned int chan)
} }
/** /**
* eqos_clear_rx_intr - Handles DMA Rx channel interrupts. * @brief eqos_clear_rx_intr - Handles DMA Rx channel interrupts.
* @addr: MAC base address.
* @chan: DMA Rx channel number.
* *
* Algorithm: Clear DMA Rx interrupt source at wrapper and DMA level. * Algorithm: Clear DMA Rx interrupt source at wrapper and DMA level.
* *
* Dependencies: * @param[in] addr: Base address indicating the start of
* 1) MAC needs to be out of reset and proper clocks need to be configured. * memory mapped IO region of the MAC.
* @param[in] chan: DMA Rx channel number.
*
* @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 3) Mapping of physical IRQ line to DMA channel need to be maintained at * 3) Mapping of physical IRQ line to DMA channel need to be maintained at
* OSDependent layer and pass corresponding channel number. * OSDependent layer and pass corresponding channel number.
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_clear_rx_intr(void *addr, unsigned int chan) static void eqos_clear_rx_intr(void *addr, unsigned int chan)
{ {
@@ -340,18 +311,14 @@ static void eqos_clear_rx_intr(void *addr, unsigned int chan)
} }
/** /**
* eqos_set_tx_ring_len - Set DMA Tx ring length. * @brief eqos_set_tx_ring_len - Set DMA Tx ring length.
* @addr: MAC base address.
* @chan: DMA Tx channel number.
* @len: Length.
* *
* Algorithm: Set DMA Tx channel ring length for specific channel. * Algorithm: Set DMA Tx channel ring length for specific channel.
* *
* Dependencies: None. * @param[in] addr: Base address indicating the start of
* * memory mapped IO region of the MAC.
* Protection: None. * @param[in] chan: DMA Tx channel number.
* * @param[in] len: Length.
* Return: None.
*/ */
static void eqos_set_tx_ring_len(void *addr, unsigned int chan, static void eqos_set_tx_ring_len(void *addr, unsigned int chan,
unsigned int len) unsigned int len)
@@ -362,18 +329,14 @@ static void eqos_set_tx_ring_len(void *addr, unsigned int chan,
} }
/** /**
* eqos_set_tx_ring_start_addr - Set DMA Tx ring base address. * @brief eqos_set_tx_ring_start_addr - Set DMA Tx ring base address.
* @addr: MAC base address.
* @chan: DMA Tx channel number.
* @tx_desc: Tx desc base addess.
* *
* Algorithm: Sets DMA Tx ring base address for specific channel. * Algorithm: Sets DMA Tx ring base address for specific channel.
* *
* Dependencies: None. * @param[in] addr: Base address indicating the start of
* * memory mapped IO region of the MAC.
* Protection: None. * @param[in] chan: DMA Tx channel number.
* * @param[in] tx_desc: Tx desc base addess.
* Return: None.
*/ */
static void eqos_set_tx_ring_start_addr(void *addr, unsigned int chan, static void eqos_set_tx_ring_start_addr(void *addr, unsigned int chan,
unsigned long tx_desc) unsigned long tx_desc)
@@ -383,20 +346,18 @@ static void eqos_set_tx_ring_start_addr(void *addr, unsigned int chan,
} }
/** /**
* eqos_update_tx_tailptr - Updates DMA Tx ring tail pointer. * @brief eqos_update_tx_tailptr - Updates DMA Tx ring tail pointer.
* @addr: MAC base address.
* @chan: DMA Tx channel number.
* @tailptr: DMA Tx ring tail pointer.
* *
* Algorithm: Updates DMA Tx ring tail pointer for specific channel. * Algorithm: Updates DMA Tx ring tail pointer for specific channel.
* *
* Dependencies: * @param[in] addr: Base address indicating the start of
* 1) MAC needs to be out of reset and proper clocks need to be configured. * memory mapped IO region of the MAC.
* @param[in] chan: DMA Tx channel number.
* @param[in] tailptr: DMA Tx ring tail pointer.
*
*
* @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_update_tx_tailptr(void *addr, unsigned int chan, static void eqos_update_tx_tailptr(void *addr, unsigned int chan,
unsigned long tailptr) unsigned long tailptr)
@@ -405,18 +366,14 @@ static void eqos_update_tx_tailptr(void *addr, unsigned int chan,
} }
/** /**
* eqos_set_rx_ring_len - Set Rx channel ring length. * @brief eqos_set_rx_ring_len - Set Rx channel ring length.
* @addr: MAC base address.
* @chan: DMA Rx channel number.
* @len: Length
* *
* Algorithm: Sets DMA Rx channel ring length for specific DMA channel. * Algorithm: Sets DMA Rx channel ring length for specific DMA channel.
* *
* Dependencies: None. * @param[in] addr: Base address indicating the start of
* * memory mapped IO region of the MAC.
* Protection: None. * @param[in] chan: DMA Rx channel number.
* * @param[in] len: Length
* Return: None.
*/ */
static void eqos_set_rx_ring_len(void *addr, unsigned int chan, static void eqos_set_rx_ring_len(void *addr, unsigned int chan,
unsigned int len) unsigned int len)
@@ -427,18 +384,14 @@ static void eqos_set_rx_ring_len(void *addr, unsigned int chan,
} }
/** /**
* eqos_set_rx_ring_start_addr - Set DMA Rx ring base address. * @brief eqos_set_rx_ring_start_addr - Set DMA Rx ring base address.
* @addr: MAC base address.
* @chan: DMA Rx channel number.
* @tx_desc: DMA Rx desc base address.
* *
* Algorithm: Sets DMA Rx channel ring base address. * Algorithm: Sets DMA Rx channel ring base address.
* *
* Dependencies: None. * @param[in] addr: Base address indicating the start of
* * memory mapped IO region of the MAC.
* Protection: None. * @param[in] chan: DMA Rx channel number.
* * @param[in] tx_desc: DMA Rx desc base address.
* Return: None.
*/ */
static void eqos_set_rx_ring_start_addr(void *addr, unsigned int chan, static void eqos_set_rx_ring_start_addr(void *addr, unsigned int chan,
unsigned long tx_desc) unsigned long tx_desc)
@@ -448,41 +401,36 @@ static void eqos_set_rx_ring_start_addr(void *addr, unsigned int chan,
} }
/** /**
* eqos_update_rx_tailptr - Update Rx ring tail pointer * @brief eqos_update_rx_tailptr - Update Rx ring tail pointer
* @addr: MAC base address.
* @chan: DMA Rx channel number.
* @tailptr: Tail pointer
* *
* Algorithm: Updates DMA Rx channel tail pointer for specific channel. * Algorithm: Updates DMA Rx channel tail pointer for specific channel.
* *
* Dependencies: * @param[in] addr: Base address indicating the start of
* 1) MAC needs to be out of reset and proper clocks need to be configured. * memory mapped IO region of the MAC.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * @param[in] chan: DMA Rx channel number.
* @param[in] tailptr: Tail pointer
* *
* Protection: None. * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* Return: None.
*/ */
static void eqos_update_rx_tailptr(void *addr, unsigned int chan, static void eqos_update_rx_tailptr(void *addr, unsigned int chan,
unsigned long tailptr) unsigned long tailptr)
{ {
osi_writel((unsigned int)L32(tailptr), (unsigned char *)addr + EQOS_DMA_CHX_RDTP(chan)); osi_writel((unsigned int)L32(tailptr), (unsigned char *)addr +
EQOS_DMA_CHX_RDTP(chan));
} }
/** /**
* eqos_start_dma - Start DMA. * @brief eqos_start_dma - Start DMA.
* @addr: MAC base address.
* @chan: DMA Tx/Rx channel number.
* *
* Algorithm: Start Tx and Rx DMA for specific channel. * Algorithm: Start Tx and Rx DMA for specific channel.
* *
* Dependencies: * @param[in] addr: Base address indicating the start of
* 1) MAC needs to be out of reset and proper clocks need to be configured. * memory mapped IO region of the MAC.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * @param[in] chan: DMA Tx/Rx channel number.
* *
* Protection: None. * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* Return: None.
*/ */
static void eqos_start_dma(void *addr, unsigned int chan) static void eqos_start_dma(void *addr, unsigned int chan)
{ {
@@ -504,19 +452,16 @@ static void eqos_start_dma(void *addr, unsigned int chan)
} }
/** /**
* eqos_stop_dma - Stop DMA. * @brief eqos_stop_dma - Stop DMA.
* @addr: MAC base address.
* @chan: DMA Tx/Rx channel number.
* *
* Algorithm: Start Tx and Rx DMA for specific channel. * Algorithm: Start Tx and Rx DMA for specific channel.
* *
* Dependencies: * @param[in] addr: Base address indicating the start of
* 1) MAC needs to be out of reset and proper clocks need to be configured. * memory mapped IO region of the MAC.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * @param[in] chan: DMA Tx/Rx channel number.
* *
* Protection: None. * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* Return: None.
*/ */
static void eqos_stop_dma(void *addr, unsigned int chan) static void eqos_stop_dma(void *addr, unsigned int chan)
{ {
@@ -538,11 +483,9 @@ static void eqos_stop_dma(void *addr, unsigned int chan)
} }
/** /**
* eqos_configure_dma_channel - Configure DMA channel * @brief eqos_configure_dma_channel - Configure DMA channel
* @chan: DMA channel number that need to be configured.
* @osi_dma: OSI DMA private data structure.
* *
* Algorithm: This takes care of configuring the below * Algorithm: This takes care of configuring the below
* parameters for the DMA channel * parameters for the DMA channel
* 1) Enabling DMA channel interrupts * 1) Enabling DMA channel interrupts
* 2) Enable 8xPBL mode * 2) Enable 8xPBL mode
@@ -550,11 +493,10 @@ static void eqos_stop_dma(void *addr, unsigned int chan)
* 4) Enable TSO if HW supports * 4) Enable TSO if HW supports
* 5) Program Rx Watchdog timer * 5) Program Rx Watchdog timer
* *
* Dependencies: MAC has to be out of reset. * @param[in] chan: DMA channel number that need to be configured.
* @param[in] osi_dma: OSI DMA private data structure.
* *
* Protection: None * @note MAC has to be out of reset.
*
* Return: NONE
*/ */
static void eqos_configure_dma_channel(unsigned int chan, static void eqos_configure_dma_channel(unsigned int chan,
struct osi_dma_priv_data *osi_dma) struct osi_dma_priv_data *osi_dma)
@@ -639,16 +581,9 @@ static void eqos_configure_dma_channel(unsigned int chan,
} }
/** /**
* eqos_init_dma_channel - DMA channel INIT * @brief eqos_init_dma_channel - DMA channel INIT
* @osi_dma: OSI DMA private data structure.
* *
* Description: Initialise all DMA channels. * @param[in] osi_dma: OSI DMA private data structure.
*
* Dependencies: None.
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_init_dma_channel(struct osi_dma_priv_data *osi_dma) static void eqos_init_dma_channel(struct osi_dma_priv_data *osi_dma)
{ {
@@ -663,20 +598,14 @@ static void eqos_init_dma_channel(struct osi_dma_priv_data *osi_dma)
} }
/** /**
* eqos_set_rx_buf_len - Set Rx buffer length * @brief eqos_set_rx_buf_len - Set Rx buffer length
* @osi_dma: OSI DMA private data structure. * Sets the Rx buffer length based on the new MTU size set.
* *
* Description: Sets the Rx buffer lenght based on the new MTU size set. * @param[in] osi_dma: OSI DMA private data structure.
* *
* Dependencies: * @note 1) MAC needs to be out of reset and proper clocks need to be configured
* 1) MAC needs to be out of reset and proper clocks need to be configured. * 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init * 3) osi_dma->mtu need to be filled with current MTU size <= 9K
* 3) osi_dma->mtu need to be filled with current MTU size <= 9K
*
*
* Protection: None.
*
* Return: None.
*/ */
static void eqos_set_rx_buf_len(struct osi_dma_priv_data *osi_dma) static void eqos_set_rx_buf_len(struct osi_dma_priv_data *osi_dma)
{ {
@@ -699,6 +628,10 @@ static void eqos_set_rx_buf_len(struct osi_dma_priv_data *osi_dma)
~(EQOS_AXI_BUS_WIDTH - 1U)); ~(EQOS_AXI_BUS_WIDTH - 1U));
} }
/**
* @brief eqos_dma_chan_ops - EQOS DMA operations
*
*/
static struct osi_dma_chan_ops eqos_dma_chan_ops = { static struct osi_dma_chan_ops eqos_dma_chan_ops = {
.set_tx_ring_len = eqos_set_tx_ring_len, .set_tx_ring_len = eqos_set_tx_ring_len,
.set_rx_ring_len = eqos_set_rx_ring_len, .set_rx_ring_len = eqos_set_rx_ring_len,
@@ -719,11 +652,17 @@ static struct osi_dma_chan_ops eqos_dma_chan_ops = {
.validate_regs = eqos_validate_dma_regs, .validate_regs = eqos_validate_dma_regs,
}; };
/**
* @brief eqos_get_dma_safety_config - EQOS get DMA safety configuration
*/
void *eqos_get_dma_safety_config(void) void *eqos_get_dma_safety_config(void)
{ {
return &eqos_dma_safety_config; return &eqos_dma_safety_config;
} }
/**
* @brief eqos_get_dma_chan_ops - EQOS get DMA channel operations
*/
struct osi_dma_chan_ops *eqos_get_dma_chan_ops(void) struct osi_dma_chan_ops *eqos_get_dma_chan_ops(void)
{ {
return &eqos_dma_chan_ops; return &eqos_dma_chan_ops;

33
osi/dma/eqos_dma.h
View File

@@ -23,9 +23,12 @@
#ifndef EQOS_DMA_H_ #ifndef EQOS_DMA_H_
#define EQOS_DMA_H_ #define EQOS_DMA_H_
#define EQOS_AXI_BUS_WIDTH 0x10U /**
* @addtogroup EQOS1 DMA Channel Register offsets
/* EQOS DMA channel registers */ *
* @brief EQOS DMA Channel register offsets
* @{
*/
#define EQOS_DMA_CHX_CTRL(x) ((0x0080U * (x)) + 0x1100U) #define EQOS_DMA_CHX_CTRL(x) ((0x0080U * (x)) + 0x1100U)
#define EQOS_DMA_CHX_TX_CTRL(x) ((0x0080U * (x)) + 0x1104U) #define EQOS_DMA_CHX_TX_CTRL(x) ((0x0080U * (x)) + 0x1104U)
#define EQOS_DMA_CHX_RX_CTRL(x) ((0x0080U * (x)) + 0x1108U) #define EQOS_DMA_CHX_RX_CTRL(x) ((0x0080U * (x)) + 0x1108U)
@@ -42,6 +45,14 @@
#define EQOS_DMA_CHX_TDRL(x) ((0x0080U * (x)) + 0x112CU) #define EQOS_DMA_CHX_TDRL(x) ((0x0080U * (x)) + 0x112CU)
#define EQOS_VIRT_INTR_CHX_STATUS(x) (0x8604U + ((x) * 8U)) #define EQOS_VIRT_INTR_CHX_STATUS(x) (0x8604U + ((x) * 8U))
#define EQOS_VIRT_INTR_CHX_CNTRL(x) (0x8600U + ((x) * 8U)) #define EQOS_VIRT_INTR_CHX_CNTRL(x) (0x8600U + ((x) * 8U))
/** @} */
/**
* @addtogroup EQOS2 BIT fields for EQOS MAC HW DMA Channel Registers
*
* @brief Values defined for the DMA channel registers
* @{
*/
#define EQOS_VIRT_INTR_CHX_STATUS_TX OSI_BIT(0) #define EQOS_VIRT_INTR_CHX_STATUS_TX OSI_BIT(0)
#define EQOS_VIRT_INTR_CHX_STATUS_RX OSI_BIT(1) #define EQOS_VIRT_INTR_CHX_STATUS_RX OSI_BIT(1)
#define EQOS_DMA_CHX_STATUS_TI OSI_BIT(0) #define EQOS_DMA_CHX_STATUS_TI OSI_BIT(0)
@@ -110,21 +121,23 @@
#define EQOS_DMA_CH2_INTR_ENA_IDX 22U #define EQOS_DMA_CH2_INTR_ENA_IDX 22U
#define EQOS_DMA_CH3_INTR_ENA_IDX 23U #define EQOS_DMA_CH3_INTR_ENA_IDX 23U
#define EQOS_MAX_DMA_SAFETY_REGS 24U #define EQOS_MAX_DMA_SAFETY_REGS 24U
#define EQOS_AXI_BUS_WIDTH 0x10U
/** @} */
/** /**
* struct dma_func_safety - Struct used to store last written values of * @brief dma_func_safety - Struct used to store last written values of
* critical DMA HW registers. * critical DMA HW registers.
* @reg_addr: Array of reg MMIO addresses (base of EQoS + offset of reg)
* @reg_mask: Array of bit-mask value of each corresponding reg (used to
* ignore self-clearing/reserved bits in reg).
* @reg_val: Array of value stored in each corresponding register.
* @dma_safety_lock: OSI lock variable used to protect writes to reg while
* validation is in-progress.
*/ */
struct dma_func_safety { struct dma_func_safety {
/** Array of reg MMIO addresses (base EQoS + offset of reg) */
void *reg_addr[EQOS_MAX_DMA_SAFETY_REGS]; void *reg_addr[EQOS_MAX_DMA_SAFETY_REGS];
/** Array of bit-mask value of each corresponding reg
* (used to ignore self-clearing/reserved bits in reg) */
unsigned int reg_mask[EQOS_MAX_DMA_SAFETY_REGS]; unsigned int reg_mask[EQOS_MAX_DMA_SAFETY_REGS];
/** Array of value stored in each corresponding register */
unsigned int reg_val[EQOS_MAX_DMA_SAFETY_REGS]; unsigned int reg_val[EQOS_MAX_DMA_SAFETY_REGS];
/** OSI lock variable used to protect writes to reg
* while validation is in-progress */
unsigned int dma_safety_lock; unsigned int dma_safety_lock;
}; };
#endif #endif

14
osi/dma/osi_dma.c
View File

@@ -69,20 +69,6 @@ int osi_hw_dma_init(struct osi_dma_priv_data *osi_dma)
return ret; return ret;
} }
/**
* osi_hw_deinit - De-init the HW
* @osi: OSI private data structure.
*
* Algorithm:
* 1) Stop the DMA
* 2) free all allocated resources.
*
* Dependencies: None
*
* Protection: None
*
* Return: 0 - Success, -ve - failure
*/
int osi_hw_dma_deinit(struct osi_dma_priv_data *osi_dma) int osi_hw_dma_deinit(struct osi_dma_priv_data *osi_dma)
{ {
unsigned int i; unsigned int i;

269
osi/dma/osi_dma_txrx.c
View File

@@ -27,11 +27,9 @@
int dma_desc_init(struct osi_dma_priv_data *osi_dma); int dma_desc_init(struct osi_dma_priv_data *osi_dma);
/** /**
* get_rx_csum - Get the Rx checksum from descriptor if valid * @brief get_rx_csum - Get the Rx checksum from descriptor if valid
* @rx_desc: Rx descriptor
* @rx_pkt_cx: Per-Rx packet context structure
* *
* Algorithm: * Algorithm:
* 1) Check if the descriptor has any checksum validation errors. * 1) Check if the descriptor has any checksum validation errors.
* 2) If none, set a per packet context flag indicating no err in * 2) If none, set a per packet context flag indicating no err in
* Rx checksum * Rx checksum
@@ -39,11 +37,8 @@ int dma_desc_init(struct osi_dma_priv_data *osi_dma);
* IP/TCP/UDP checksum validation in software based on whether * IP/TCP/UDP checksum validation in software based on whether
* COE is enabled for the device. * COE is enabled for the device.
* *
* Dependencies: None * @param[in] rx_desc: Rx descriptor
* * @param[in] rx_pkt_cx: Per-Rx packet context structure
* Protection: None
*
* Return: None.
*/ */
static inline void get_rx_csum(struct osi_rx_desc *rx_desc, static inline void get_rx_csum(struct osi_rx_desc *rx_desc,
struct osi_rx_pkt_cx *rx_pkt_cx) struct osi_rx_pkt_cx *rx_pkt_cx)
@@ -61,6 +56,18 @@ static inline void get_rx_csum(struct osi_rx_desc *rx_desc,
} }
} }
/**
* @brief get_rx_vlan_from_desc - Get Rx VLAN from descriptor
*
* Algorithm:
* 1) Check if the descriptor has any type set.
* 2) If set, set a per packet context flag indicating packet is VLAN
* tagged.
* 3) Extract VLAN tag ID from the descriptor
*
* @param[in] rx_desc: Rx descriptor
* @param[in] rx_pkt_cx: Per-Rx packet context structure
*/
static inline void get_rx_vlan_from_desc(struct osi_rx_desc *rx_desc, static inline void get_rx_vlan_from_desc(struct osi_rx_desc *rx_desc,
struct osi_rx_pkt_cx *rx_pkt_cx) struct osi_rx_pkt_cx *rx_pkt_cx)
{ {
@@ -78,18 +85,16 @@ static inline void get_rx_vlan_from_desc(struct osi_rx_desc *rx_desc,
} }
/** /**
* get_rx_tstamp_status - Get Tx Time stamp status * @brief get_rx_tstamp_status - Get Tx Time stamp status
* @context_desc: Rx context descriptor
* *
* Algorithm: * Algorithm:
* 1) Check if the received descriptor is a context descriptor. * 1) Check if the received descriptor is a context descriptor.
* 2) If yes, check whether the time stamp is valid or not. * 2) If yes, check whether the time stamp is valid or not.
* *
* Dependencies: None * @param[in] context_desc: Rx context descriptor
* *
* Protection: None * @retval -1 if TimeStamp is not valid
* * @retval 0 if TimeStamp is valid.
* Return: -1 if TS is not valid and 0 if TS is valid.
*/ */
static inline int get_rx_tstamp_status(struct osi_rx_desc *context_desc) static inline int get_rx_tstamp_status(struct osi_rx_desc *context_desc)
{ {
@@ -108,22 +113,20 @@ static inline int get_rx_tstamp_status(struct osi_rx_desc *context_desc)
} }
/** /**
* get_rx_hwstamp - Get Rx HW Time stamp * @brief get_rx_hwstamp - Get Rx HW Time stamp
* @rx_desc: Rx descriptor
* @context_desc: Rx context descriptor
* @rx_pkt_cx: Rx packet context
* *
* Algorithm: * Algorithm:
* 1) Check for TS availability. * 1) Check for TS availability.
* 2) call get_tx_tstamp_status if TS is valid or not. * 2) call get_tx_tstamp_status if TS is valid or not.
* 3) If yes, set a bit and update nano seconds in rx_pkt_cx so that OSD * 3) If yes, set a bit and update nano seconds in rx_pkt_cx so that OSD
* layer can extract the time by checking this bit. * layer can extract the time by checking this bit.
* *
* Dependencies: None * @param[in] rx_desc: Rx descriptor
* @param[in] context_desc: Rx context descriptor
* @param[in] rx_pkt_cx: Rx packet context
* *
* Protection: None * @retval -1 if TimeStamp is not available
* * @retval 0 if TimeStamp is available.
* Return: -1 if TS is not available and 0 if TS is available.
*/ */
static int get_rx_hwstamp(struct osi_rx_desc *rx_desc, static int get_rx_hwstamp(struct osi_rx_desc *rx_desc,
struct osi_rx_desc *context_desc, struct osi_rx_desc *context_desc,
@@ -164,19 +167,14 @@ static int get_rx_hwstamp(struct osi_rx_desc *rx_desc,
/** /**
* get_rx_err_stats - Detect Errors from Rx Descriptor * @brief get_rx_err_stats - Detect Errors from Rx Descriptor
* @rx_desc: Rx Descriptor.
* @pkt_err_stats: Packet error stats which stores the errors reported
* *
* Algorimthm: This routine will be invoked by OSI layer itself which * Algorithm: This routine will be invoked by OSI layer itself which
* checks for the Last Descriptor and updates the receive status errors * checks for the Last Descriptor and updates the receive status errors
* accordingly. * accordingly.
* *
* Dependencies: None. * @param[in] rx_desc: Rx Descriptor.
* * @param[in] pkt_err_stats: Packet error stats which stores the errors reported
* Protection: None.
*
* Return: None.
*/ */
static inline void get_rx_err_stats(struct osi_rx_desc *rx_desc, static inline void get_rx_err_stats(struct osi_rx_desc *rx_desc,
struct osi_pkt_err_stats pkt_err_stats) struct osi_pkt_err_stats pkt_err_stats)
@@ -189,29 +187,6 @@ static inline void get_rx_err_stats(struct osi_rx_desc *rx_desc,
} }
} }
/**
* osi_process_rx_completions - Read data from receive channel descriptors
* @osi: OSI private data structure.
* @chan: Rx DMA channel number
* @budget: Threshould for reading the packets at a time.
*
* Algorimthm: This routine will be invoked by OSD layer to get the
* data from Rx descriptors and deliver the packet to the stack.
* 1) Checks descriptor owned by DMA or not.
* 2) Get the length from Rx descriptor
* 3) Invokes OSD layer to deliver the packet to network stack.
* 4) Re-allocate the receive buffers, populate Rx descriptor and
* handover to DMA.
*
* Dependencies:
* 1) MAC needs to be out of reset and proper clocks need to be configured.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 3) DMA need to be started, see osi_start_dma
*
* Protection: None.
*
* Return: None.
*/
int osi_process_rx_completions(struct osi_dma_priv_data *osi, int osi_process_rx_completions(struct osi_dma_priv_data *osi,
unsigned int chan, int budget) unsigned int chan, int budget)
{ {
@@ -278,19 +253,14 @@ int osi_process_rx_completions(struct osi_dma_priv_data *osi,
} }
/** /**
* get_tx_err_stats - Detect Errors from Tx Status * @brief get_tx_err_stats - Detect Errors from Tx Status
* @tx_desc: Tx Descriptor.
* @pkt_err_stats: Pakcet error stats which stores the errors reported
* *
* Algorimthm: This routine will be invoked by OSI layer itself which * Algorithm: This routine will be invoked by OSI layer itself which
* checks for the Last Descriptor and updates the transmit status errors * checks for the Last Descriptor and updates the transmit status errors
* accordingly. * accordingly.
* *
* Dependencies: None. * @param[in] tx_desc: Tx Descriptor.
* * @param[in] pkt_err_stats: Pakcet error stats which stores the errors reported
* Protection: None.
*
* Return: None.
*/ */
static inline void get_tx_err_stats(struct osi_tx_desc *tx_desc, static inline void get_tx_err_stats(struct osi_tx_desc *tx_desc,
struct osi_pkt_err_stats pkt_err_stats) struct osi_pkt_err_stats pkt_err_stats)
@@ -370,21 +340,6 @@ static inline void get_tx_err_stats(struct osi_tx_desc *tx_desc,
} }
} }
/**
* osi_clear_tx_pkt_err_stats - Clear tx packet error stats.
* @osi: OSI dma private data structure.
*
* Algorithm: This function will be invoked by OSD layer to clear the
* tx packet error stats
*
* Dependencies:
* 1) MAC needs to be out of reset and proper clocks need to be configured.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
*
* Protection: None
*
* Return: 0 - success, -1 - failure.
*/
int osi_clear_tx_pkt_err_stats(struct osi_dma_priv_data *osi_dma) int osi_clear_tx_pkt_err_stats(struct osi_dma_priv_data *osi_dma)
{ {
int ret = -1; int ret = -1;
@@ -407,21 +362,6 @@ int osi_clear_tx_pkt_err_stats(struct osi_dma_priv_data *osi_dma)
return ret; return ret;
} }
/**
* osi_clear_rx_pkt_err_stats - Clear rx packet error stats.
* @osi: OSI dma private data structure.
*
* Algorithm: This function will be invoked by OSD layer to clear the
* rx packet error stats
*
* Dependencies:
* 1) MAC needs to be out of reset and proper clocks need to be configured.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
*
* Protection: None
*
* Return: 0 - success, -1 - failure.
*/
int osi_clear_rx_pkt_err_stats(struct osi_dma_priv_data *osi_dma) int osi_clear_rx_pkt_err_stats(struct osi_dma_priv_data *osi_dma)
{ {
int ret = -1; int ret = -1;
@@ -435,27 +375,6 @@ int osi_clear_rx_pkt_err_stats(struct osi_dma_priv_data *osi_dma)
return ret; return ret;
} }
/**
* osi_process_tx_completions - Process Tx complete on DMA channel ring.
* @osi: OSI private data structure.
* @chan: Channel number on which Tx complete need to be done.
*
* Algorithm: This function will be invoked by OSD layer to process Tx
* complete interrupt.
* 1) First checks whether descriptor owned by DMA or not.
* 2) Invokes OSD layer to release DMA address and Tx buffer which are
* updated as part of transmit routine.
*
* Dependencies:
* 1) MAC needs to be out of reset and proper clocks need to be configured.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 3) DMA need to be started, see osi_start_dma
*
*
* Protection: None
*
* Return: Number of decriptors (buffers) proccessed.
*/
int osi_process_tx_completions(struct osi_dma_priv_data *osi, int osi_process_tx_completions(struct osi_dma_priv_data *osi,
unsigned int chan) unsigned int chan)
{ {
@@ -544,20 +463,18 @@ int osi_process_tx_completions(struct osi_dma_priv_data *osi,
} }
/** /**
* need_cntx_desc - Helper function to check if context desc is needed. * @brief need_cntx_desc - Helper function to check if context desc is needed.
* @tx_pkt_cx: Pointer to transmit packet context structure
* @tx_desc: Pointer to tranmit descriptor to be filled.
* *
* Algorithm: * Algorithm:
* 1) Check if transmit packet context flags are set * 1) Check if transmit packet context flags are set
* 2) If set, set the context descriptor bit along * 2) If set, set the context descriptor bit along
* with other context information in the transmit descriptor. * with other context information in the transmit descriptor.
* *
* Dependencies: None. * @param[in] tx_pkt_cx: Pointer to transmit packet context structure
* @param[in] tx_desc: Pointer to tranmit descriptor to be filled.
* *
* Protection: None * @retval 0 - cntx desc not used
* * @retval 1 - cntx desc used.
* Return: 0 - cntx desc not used, 1 - cntx desc used.
*/ */
static inline int need_cntx_desc(struct osi_tx_pkt_cx *tx_pkt_cx, static inline int need_cntx_desc(struct osi_tx_pkt_cx *tx_pkt_cx,
struct osi_tx_desc *tx_desc) struct osi_tx_desc *tx_desc)
@@ -594,22 +511,18 @@ static inline int need_cntx_desc(struct osi_tx_pkt_cx *tx_pkt_cx,
} }
/** /**
* fill_first_desc - Helper function to fill the first transmit descriptor. * @brief fill_first_desc - Helper function to fill the first transmit
* @tx_pkt_cx: Pointer to transmit packet context structure * descriptor.
* @tx_desc: Pointer to tranmit descriptor to be filled.
* @tx_swcx: Pointer to corresponding tranmit descriptor software context.
* *
* Algorithm: * Algorithm:
* 1) Update the buffer address and length of buffer in first desc. * 1) Update the buffer address and length of buffer in first desc.
* 2) Check if any features like HW checksum offload, TSO, VLAN insertion * 2) Check if any features like HW checksum offload, TSO, VLAN insertion
* etc. are flagged in transmit packet context. If so, set the fiels in * etc. are flagged in transmit packet context. If so, set the fiels in
* first desc corresponding to those features. * first desc corresponding to those features.
* *
* Dependencies: None. * @param[in] tx_pkt_cx: Pointer to transmit packet context structure
* * @param[in] tx_desc: Pointer to tranmit descriptor to be filled.
* Protection: None * @param[in] tx_swcx: Pointer to corresponding tx descriptor software context.
*
* Return: None.
*/ */
static inline void fill_first_desc(struct osi_tx_pkt_cx *tx_pkt_cx, static inline void fill_first_desc(struct osi_tx_pkt_cx *tx_pkt_cx,
struct osi_tx_desc *tx_desc, struct osi_tx_desc *tx_desc,
@@ -658,35 +571,6 @@ static inline void fill_first_desc(struct osi_tx_pkt_cx *tx_pkt_cx,
} }
} }
/**
* osi_hw_transmit - Initialize Tx DMA descriptors for a channel
* @osi: OSI private data structure.
* @chan: DMA Tx channel number
*
* Algorithm: Initialize Transmit descriptors with DMA mappabled buffers,
* set OWN bit, Tx ring length and set starting address of Tx DMA channel.
* Tx ring base address in Tx DMA registers.
*
* Dependencies:
* 1) MAC needs to be out of reset and proper clocks need to be configured.
* 2) DMA HW init need to be completed successfully, see osi_hw_dma_init
* 3) DMA channel need to be started, see osi_start_dma
* 4) Need to set update tx_pkt_cx->flags accordingly as per the
* requirements
* #define OSI_PKT_CX_VLAN OSI_BIT(0)
* #define OSI_PKT_CX_CSUM OSI_BIT(1)
* #define OSI_PKT_CX_TSO OSI_BIT(2)
* #define OSI_PKT_CX_PTP OSI_BIT(3)
* 5) tx_pkt_cx->desc_cnt need to be populated which holds the number
* of swcx descriptors allocated for that packet
* 6) tx_swcx structure need to be filled for per packet with the
* buffer len, DMA mapped address of buffer for each descriptor
* consumed by the packet
*
* Protection: None.
*
* Return: None.
*/
void osi_hw_transmit(struct osi_dma_priv_data *osi, unsigned int chan) void osi_hw_transmit(struct osi_dma_priv_data *osi, unsigned int chan)
{ {
struct osi_tx_ring *tx_ring = osi->tx_ring[chan]; struct osi_tx_ring *tx_ring = osi->tx_ring[chan];
@@ -773,19 +657,17 @@ void osi_hw_transmit(struct osi_dma_priv_data *osi, unsigned int chan)
} }
/** /**
* rx_dma_desc_initialization - Initialize DMA Receive descriptors for Rx. * @brief rx_dma_desc_initialization - Initialize DMA Receive descriptors for Rx
* @osi: OSI private data structure.
* @chan: Rx channel number.
* *
* Algorithm: Initialize Receive descriptors with DMA mappable buffers, * Algorithm: Initialize Receive descriptors with DMA mappable buffers,
* set OWN bit, Rx ring length and set starting address of Rx DMA channel. * set OWN bit, Rx ring length and set starting address of Rx DMA channel.
* Tx ring base address in Tx DMA registers. * Tx ring base address in Tx DMA registers.
* *
* Dependencies: None. * @param[in] osi: OSI private data structure.
* @param[in] chan: Rx channel number.
* *
* Protection: None. * @retval 0 on success
* * @retval -1 on failure.
* Return: 0 - success, -1 - failure.
*/ */
static int rx_dma_desc_initialization(struct osi_dma_priv_data *osi, static int rx_dma_desc_initialization(struct osi_dma_priv_data *osi,
unsigned int chan) unsigned int chan)
@@ -826,18 +708,16 @@ static int rx_dma_desc_initialization(struct osi_dma_priv_data *osi,
} }
/** /**
* rx_dma_desc_init - Initialize DMA Receive descriptors for Rx channel. * @brief rx_dma_desc_init - Initialize DMA Receive descriptors for Rx channel.
* @osi: OSI private data structure.
* *
* Algorithm: Initialize Receive descriptors with DMA mappabled buffers, * Algorithm: Initialize Receive descriptors with DMA mappabled buffers,
* set OWN bit, Rx ring length and set starting address of Rx DMA channel. * set OWN bit, Rx ring length and set starting address of Rx DMA channel.
* Tx ring base address in Tx DMA registers. * Tx ring base address in Tx DMA registers.
* *
* Dependencies: None. * @param[in] osi: OSI private data structure.
* *
* Protection: None. * @retval 0 on success
* * @retval -1 on failure.
* Return: 0 - success, -1 - failure.
*/ */
static int rx_dma_desc_init(struct osi_dma_priv_data *osi) static int rx_dma_desc_init(struct osi_dma_priv_data *osi)
{ {
@@ -858,17 +738,12 @@ static int rx_dma_desc_init(struct osi_dma_priv_data *osi)
} }
/** /**
* tx_dma_desc_init - Initialize DMA Transmit descriptors. * @brief tx_dma_desc_init - Initialize DMA Transmit descriptors.
* @osi: OSI private data structure.
* *
* Algorithm: Initialize Trannsmit descriptors and set Tx ring length, * Algorithm: Initialize Trannsmit descriptors and set Tx ring length,
* Tx ring base address in Tx DMA registers. * Tx ring base address in Tx DMA registers.
* *
* Dependencies: None. * @param[in] osi_dma: OSI DMA private data structure.
*
* Protection: None.
*
* Return: None.
*/ */
static void tx_dma_desc_init(struct osi_dma_priv_data *osi_dma) static void tx_dma_desc_init(struct osi_dma_priv_data *osi_dma)
{ {
@@ -901,17 +776,15 @@ static void tx_dma_desc_init(struct osi_dma_priv_data *osi_dma)
} }
/** /**
* dma_desc_init - Initialize DMA Tx/Rx descriptors * @brief dma_desc_init - Initialize DMA Tx/Rx descriptors
* @osi: OSI private data structure.
* *
* Algorithm: Transmit and Receive desctiptors will be initialized with * Algorithm: Transmit and Receive desctiptors will be initialized with
* required values so that MAC DMA can understand and act accordingly. * required values so that MAC DMA can understand and act accordingly.
* *
* Dependencies: None. * @param[in] osi_dma: OSI DMA private data structure.
* *
* Protection: None. * @retval 0 on success
* * @retval -1 on failure.
* Return: 0 - success, -1 - failure.
*/ */
int dma_desc_init(struct osi_dma_priv_data *osi_dma) int dma_desc_init(struct osi_dma_priv_data *osi_dma)
{ {