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Revert "coe: Disable seq num check in macsec for COE"

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This reverts commit b8fe432eea.

Reason for revert: HSB FW has been updated to include resetting the frame number for every SOF. This has been verified with Eagle AIO modules with HSB FW FPGA version=0x2505 datecode=0xf1a72011

CT26X-1921

Change-Id: I67f83a2d7de93187276266689d34d68f8c551f7e
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3381926
This commit is contained in:
Srinivas Ramachandran
2025-06-06 15:57:16 -07:00
parent 9aa28e802d
commit b41d40ece9
1 changed files with 1 additions and 3 deletions
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4
osi/nvmacsecrm/macsec.c
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@@ -4748,9 +4748,7 @@ static nve32_t macsec_coe_config(struct osi_core_priv_data *const osi_core,
nve32_t ret = 0; nve32_t ret = 0;
val = coe_enable & MACSEC_COE_ENABLE_MASK; val = coe_enable & MACSEC_COE_ENABLE_MASK;
/* TODO - re-enable seq num check for production. This is just till HSB FPGA can be val |= (coe_enable & MACSEC_COE_ENABLE_MASK) << MACSEC_COE_SEQ_CHK_SHIFT;
* fixed to use proper starting seq for every SOF. */
//val |= (coe_enable & MACSEC_COE_ENABLE_MASK) << MACSEC_COE_SEQ_CHK_SHIFT;
val |= (coe_hdr_offset & MACSEC_COE_HDROFST_MASK) << MACSEC_COE_HDROFST_SHIFT; val |= (coe_hdr_offset & MACSEC_COE_HDROFST_MASK) << MACSEC_COE_HDROFST_SHIFT;
osi_macsec_writela(osi_core, val, addr + MACSEC_COE_CONFIG); osi_macsec_writela(osi_core, val, addr + MACSEC_COE_CONFIG);