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nvethernetrm: enable common interrupt in eqos wrapper

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Enable EQOS_CORE_SBD_INTR in ETHER_QOS_COMMON_INTR_ENABLE
and clear in ETHER_QOS_COMMON_INTR_STATUS.

Bug 200760072

Change-Id: Id0e4a6d5704664faf633181d816d3708cb85956a
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2577049
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Rakesh Goyal
2021-08-16 12:57:02 +05:30
committed by mobile promotions
parent 36510e26ad
commit b4f9f7fae8
2 changed files with 23 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
osi/core/eqos_core.c
View File

@@ -1692,6 +1692,15 @@ static void eqos_configure_mac(struct osi_core_priv_data *const osi_core)
eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base + eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MAC_MCR, EQOS_MAC_MCR_IDX); EQOS_MAC_MCR, EQOS_MAC_MCR_IDX);
/* Enable common interrupt at wrapper level */
if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) {
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_WRAP_COMMON_INTR_ENABLE);
value |= EQOS_MAC_SBD_INTR;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_WRAP_COMMON_INTR_ENABLE);
}
/* enable Packet Duplication Control */ /* enable Packet Duplication Control */
value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_EXTR); value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_EXTR);
if (osi_core->mac_ver >= OSI_EQOS_MAC_5_00) { if (osi_core->mac_ver >= OSI_EQOS_MAC_5_00) {
@@ -2520,8 +2529,17 @@ static void eqos_handle_common_intr(struct osi_core_priv_data *const osi_core)
nveu32_t i = 0; nveu32_t i = 0;
nveu32_t dma_sr = 0; nveu32_t dma_sr = 0;
nveu32_t dma_ier = 0; nveu32_t dma_ier = 0;
unsigned int mtl_isr = 0; nveu32_t mtl_isr = 0;
unsigned int frp_isr = 0U; nveu32_t frp_isr = 0U;
nveu32_t val = 0U;
if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) {
val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_WRAP_COMMON_INTR_STATUS);
val |= EQOS_MAC_SBD_INTR;
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
EQOS_WRAP_COMMON_INTR_STATUS);
}
dma_isr = osi_readla(osi_core, (nveu8_t *)base + EQOS_DMA_ISR); dma_isr = osi_readla(osi_core, (nveu8_t *)base + EQOS_DMA_ISR);
if (dma_isr == 0U) { if (dma_isr == 0U) {

3
osi/core/eqos_core.h
View File

@@ -184,6 +184,9 @@
#define EQOS_PAD_AUTO_CAL_CFG 0x8804U #define EQOS_PAD_AUTO_CAL_CFG 0x8804U
#define EQOS_PAD_AUTO_CAL_STAT 0x880CU #define EQOS_PAD_AUTO_CAL_STAT 0x880CU
#define EQOS_VIRT_INTR_APB_CHX_CNTRL(x) (0x8200U + ((x) * 4U)) #define EQOS_VIRT_INTR_APB_CHX_CNTRL(x) (0x8200U + ((x) * 4U))
#define EQOS_WRAP_COMMON_INTR_ENABLE 0x8704
#define EQOS_WRAP_COMMON_INTR_STATUS 0x8708
#define EQOS_MAC_SBD_INTR 0x4
/** @} */ /** @} */
/** /**