From baba0efe3638d311610f447ffd380efd2d49d0d6 Mon Sep 17 00:00:00 2001 From: Rakesh Goyal Date: Thu, 11 Aug 2022 06:33:53 +0530 Subject: [PATCH] nvethernetrm: take exported ioctl related header out Issue: SW needs to support IOCTL on safety builds and these header should be exposed to user Fix: Create new header file which is exposed externally Fix Coverity issues Enable TSN and FRP for safety build Optimize the code between eqos and mgbe Bug 3704251 Change-Id: I2807f8283a296de1f96d3f902cb4ad5a4781be50 Signed-off-by: Rakesh Goyal Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2759333 GVS: Gerrit_Virtual_Submit Reviewed-by: Bhadram Varka Reviewed-by: Narayan Reddy Reviewed-by: Krishna Thota --- include/ivc_core.h | 12 +- include/mmc.h | 525 ----------------------- include/nvethernetrm_export.h | 782 ++++++++++++++++++++++++++++++++++ include/osi_common.h | 73 +--- include/osi_core.h | 311 +++----------- osi/common/common.h | 6 +- osi/core/core_common.c | 658 +++++++++++++++++++++++++++- osi/core/core_common.h | 42 +- osi/core/core_local.h | 68 ++- osi/core/eqos_core.c | 600 +++----------------------- osi/core/eqos_core.h | 225 +++++----- osi/core/frp.c | 179 ++++---- osi/core/frp.h | 6 +- osi/core/ivc_core.c | 25 +- osi/core/mgbe_core.c | 759 ++++++--------------------------- osi/core/mgbe_core.h | 274 ++++++------ osi/core/osi_hal.c | 200 +++++---- 17 files changed, 2216 insertions(+), 2529 deletions(-) create mode 100644 include/nvethernetrm_export.h diff --git a/include/ivc_core.h b/include/ivc_core.h index d4e5253..9488686 100644 --- a/include/ivc_core.h +++ b/include/ivc_core.h @@ -35,6 +35,14 @@ */ #define MAX_ARGS 10 +/* + *@brief All Stats + */ +struct osi_stats { + struct osi_mmc_counters mmc_s; + struct osi_tsn_stats tsn_s; +}; + /** * @brief IVC commands between OSD & OSI. */ @@ -135,10 +143,8 @@ typedef struct ivc_msg_common { union { /** IVC argument structure */ ivc_args args; -#ifndef OSI_STRIPPED_LIB /** avb algorithm structure */ struct osi_core_avb_algorithm avb_algo; -#endif /** OSI filter structure */ struct osi_filter filter; /** OSI HW features */ @@ -149,6 +155,8 @@ typedef struct ivc_msg_common { ivc_core_args init_args; /** ioctl command structure */ struct osi_ioctl ioctl_data; + /** All stats */ + struct osi_stats eth_stats; #ifdef MACSEC_SUPPORT /** lut config */ struct osi_macsec_lut_config lut_config; diff --git a/include/mmc.h b/include/mmc.h index 95b957a..1231557 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -26,531 +26,6 @@ #include "../osi/common/type.h" #include "osi_common.h" -/** - * @brief osi_mmc_counters - The structure to hold RMON counter values - */ -struct osi_mmc_counters { - /** This counter provides the number of bytes transmitted, exclusive of - * preamble and retried bytes, in good and bad packets */ - nveu64_t mmc_tx_octetcount_gb; - /** This counter provides upper 32 bits of transmitted octet count */ - nveu64_t mmc_tx_octetcount_gb_h; - /** This counter provides the number of good and - * bad packets transmitted, exclusive of retried packets */ - nveu64_t mmc_tx_framecount_gb; - /** This counter provides upper 32 bits of transmitted good and bad - * packets count */ - nveu64_t mmc_tx_framecount_gb_h; - /** This counter provides number of good broadcast - * packets transmitted */ - nveu64_t mmc_tx_broadcastframe_g; - /** This counter provides upper 32 bits of transmitted good broadcast - * packets count */ - nveu64_t mmc_tx_broadcastframe_g_h; - /** This counter provides number of good multicast - * packets transmitted */ - nveu64_t mmc_tx_multicastframe_g; - /** This counter provides upper 32 bits of transmitted good multicast - * packet count */ - nveu64_t mmc_tx_multicastframe_g_h; - /** This counter provides the number of good and bad packets - * transmitted with length 64 bytes, exclusive of preamble and - * retried packets */ - nveu64_t mmc_tx_64_octets_gb; - /** This counter provides upper 32 bits of transmitted 64 octet size - * good and bad packets count */ - nveu64_t mmc_tx_64_octets_gb_h; - /** This counter provides the number of good and bad packets - * transmitted with length 65-127 bytes, exclusive of preamble and - * retried packets */ - nveu64_t mmc_tx_65_to_127_octets_gb; - /** Provides upper 32 bits of transmitted 65-to-127 octet size good and - * bad packets count */ - nveu64_t mmc_tx_65_to_127_octets_gb_h; - /** This counter provides the number of good and bad packets - * transmitted with length 128-255 bytes, exclusive of preamble and - * retried packets */ - nveu64_t mmc_tx_128_to_255_octets_gb; - /** This counter provides upper 32 bits of transmitted 128-to-255 - * octet size good and bad packets count */ - nveu64_t mmc_tx_128_to_255_octets_gb_h; - /** This counter provides the number of good and bad packets - * transmitted with length 256-511 bytes, exclusive of preamble and - * retried packets */ - nveu64_t mmc_tx_256_to_511_octets_gb; - /** This counter provides upper 32 bits of transmitted 256-to-511 - * octet size good and bad packets count. */ - nveu64_t mmc_tx_256_to_511_octets_gb_h; - /** This counter provides the number of good and bad packets - * transmitted with length 512-1023 bytes, exclusive of preamble and - * retried packets */ - nveu64_t mmc_tx_512_to_1023_octets_gb; - /** This counter provides upper 32 bits of transmitted 512-to-1023 - * octet size good and bad packets count.*/ - nveu64_t mmc_tx_512_to_1023_octets_gb_h; - /** This counter provides the number of good and bad packets - * transmitted with length 1024-max bytes, exclusive of preamble and - * retried packets */ - nveu64_t mmc_tx_1024_to_max_octets_gb; - /** This counter provides upper 32 bits of transmitted 1024-tomaxsize - * octet size good and bad packets count. */ - nveu64_t mmc_tx_1024_to_max_octets_gb_h; - /** This counter provides the number of good and bad unicast packets */ - nveu64_t mmc_tx_unicast_gb; - /** This counter provides upper 32 bits of transmitted good bad - * unicast packets count */ - nveu64_t mmc_tx_unicast_gb_h; - /** This counter provides the number of good and bad - * multicast packets */ - nveu64_t mmc_tx_multicast_gb; - /** This counter provides upper 32 bits of transmitted good bad - * multicast packets count */ - nveu64_t mmc_tx_multicast_gb_h; - /** This counter provides the number of good and bad - * broadcast packets */ - nveu64_t mmc_tx_broadcast_gb; - /** This counter provides upper 32 bits of transmitted good bad - * broadcast packets count */ - nveu64_t mmc_tx_broadcast_gb_h; - /** This counter provides the number of abort packets due to - * underflow error */ - nveu64_t mmc_tx_underflow_error; - /** This counter provides upper 32 bits of abort packets due to - * underflow error */ - nveu64_t mmc_tx_underflow_error_h; - /** This counter provides the number of successfully transmitted - * packets after a single collision in the half-duplex mode */ - nveu64_t mmc_tx_singlecol_g; - /** This counter provides the number of successfully transmitted - * packets after a multi collision in the half-duplex mode */ - nveu64_t mmc_tx_multicol_g; - /** This counter provides the number of successfully transmitted - * after a deferral in the half-duplex mode */ - nveu64_t mmc_tx_deferred; - /** This counter provides the number of packets aborted because of - * late collision error */ - nveu64_t mmc_tx_latecol; - /** This counter provides the number of packets aborted because of - * excessive (16) collision errors */ - nveu64_t mmc_tx_exesscol; - /** This counter provides the number of packets aborted because of - * carrier sense error (no carrier or loss of carrier) */ - nveu64_t mmc_tx_carrier_error; - /** This counter provides the number of bytes transmitted, - * exclusive of preamble, only in good packets */ - nveu64_t mmc_tx_octetcount_g; - /** This counter provides upper 32 bytes of bytes transmitted, - * exclusive of preamble, only in good packets */ - nveu64_t mmc_tx_octetcount_g_h; - /** This counter provides the number of good packets transmitted */ - nveu64_t mmc_tx_framecount_g; - /** This counter provides upper 32 bytes of good packets transmitted */ - nveu64_t mmc_tx_framecount_g_h; - /** This counter provides the number of packets aborted because of - * excessive deferral error - * (deferred for more than two max-sized packet times) */ - nveu64_t mmc_tx_excessdef; - /** This counter provides the number of good Pause - * packets transmitted */ - nveu64_t mmc_tx_pause_frame; - /** This counter provides upper 32 bytes of good Pause - * packets transmitted */ - nveu64_t mmc_tx_pause_frame_h; - /** This counter provides the number of good VLAN packets transmitted */ - nveu64_t mmc_tx_vlan_frame_g; - /** This counter provides upper 32 bytes of good VLAN packets - * transmitted */ - nveu64_t mmc_tx_vlan_frame_g_h; - /** This counter provides the number of packets transmitted without - * errors and with length greater than the maxsize (1,518 or 1,522 bytes - * for VLAN tagged packets; 2000 bytes */ - nveu64_t mmc_tx_osize_frame_g; - /** This counter provides the number of good and bad packets received */ - nveu64_t mmc_rx_framecount_gb; - /** This counter provides upper 32 bytes of good and bad packets - * received */ - nveu64_t mmc_rx_framecount_gb_h; - /** This counter provides the number of bytes received by DWC_ther_qos, - * exclusive of preamble, in good and bad packets */ - nveu64_t mmc_rx_octetcount_gb; - /** This counter provides upper 32 bytes of bytes received by - * DWC_ether_qos, exclusive of preamble, in good and bad packets */ - nveu64_t mmc_rx_octetcount_gb_h; - /** This counter provides the number of bytes received by DWC_ether_qos, - * exclusive of preamble, in good and bad packets */ - nveu64_t mmc_rx_octetcount_g; - /** This counter provides upper 32 bytes of bytes received by - * DWC_ether_qos, exclusive of preamble, in good and bad packets */ - nveu64_t mmc_rx_octetcount_g_h; - /** This counter provides the number of good - * broadcast packets received */ - nveu64_t mmc_rx_broadcastframe_g; - /** This counter provides upper 32 bytes of good - * broadcast packets received */ - nveu64_t mmc_rx_broadcastframe_g_h; - /** This counter provides the number of good - * multicast packets received */ - nveu64_t mmc_rx_multicastframe_g; - /** This counter provides upper 32 bytes of good - * multicast packets received */ - nveu64_t mmc_rx_multicastframe_g_h; - /** This counter provides the number of packets - * received with CRC error */ - nveu64_t mmc_rx_crc_error; - /** This counter provides upper 32 bytes of packets - * received with CRC error */ - nveu64_t mmc_rx_crc_error_h; - /** This counter provides the number of packets received with - * alignment (dribble) error. It is valid only in 10/100 mode */ - nveu64_t mmc_rx_align_error; - /** This counter provides the number of packets received with - * runt (length less than 64 bytes and CRC error) error */ - nveu64_t mmc_rx_runt_error; - /** This counter provides the number of giant packets received with - * length (including CRC) greater than 1,518 bytes (1,522 bytes for - * VLAN tagged) and with CRC error */ - nveu64_t mmc_rx_jabber_error; - /** This counter provides the number of packets received with length - * less than 64 bytes, without any errors */ - nveu64_t mmc_rx_undersize_g; - /** This counter provides the number of packets received without error, - * with length greater than the maxsize */ - nveu64_t mmc_rx_oversize_g; - /** This counter provides the number of good and bad packets received - * with length 64 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_64_octets_gb; - /** This counter provides upper 32 bytes of good and bad packets - * received with length 64 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_64_octets_gb_h; - /** This counter provides the number of good and bad packets received - * with length 65-127 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_65_to_127_octets_gb; - /** This counter provides upper 32 bytes of good and bad packets - * received with length 65-127 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_65_to_127_octets_gb_h; - /** This counter provides the number of good and bad packets received - * with length 128-255 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_128_to_255_octets_gb; - /** This counter provides upper 32 bytes of good and bad packets - * received with length 128-255 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_128_to_255_octets_gb_h; - /** This counter provides the number of good and bad packets received - * with length 256-511 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_256_to_511_octets_gb; - /** This counter provides upper 32 bytes of good and bad packets - * received with length 256-511 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_256_to_511_octets_gb_h; - /** This counter provides the number of good and bad packets received - * with length 512-1023 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_512_to_1023_octets_gb; - /** This counter provides upper 32 bytes of good and bad packets - * received with length 512-1023 bytes, exclusive of the preamble */ - nveu64_t mmc_rx_512_to_1023_octets_gb_h; - /** This counter provides the number of good and bad packets received - * with length 1024-maxbytes, exclusive of the preamble */ - nveu64_t mmc_rx_1024_to_max_octets_gb; - /** This counter provides upper 32 bytes of good and bad packets - * received with length 1024-maxbytes, exclusive of the preamble */ - nveu64_t mmc_rx_1024_to_max_octets_gb_h; - /** This counter provides the number of good unicast packets received */ - nveu64_t mmc_rx_unicast_g; - /** This counter provides upper 32 bytes of good unicast packets - * received */ - nveu64_t mmc_rx_unicast_g_h; - /** This counter provides the number of packets received with length - * error (Length Type field not equal to packet size), for all packets - * with valid length field */ - nveu64_t mmc_rx_length_error; - /** This counter provides upper 32 bytes of packets received with - * length error (Length Type field not equal to packet size), for all - * packets with valid length field */ - nveu64_t mmc_rx_length_error_h; - /** This counter provides the number of packets received with length - * field not equal to the valid packet size (greater than 1,500 but - * less than 1,536) */ - nveu64_t mmc_rx_outofrangetype; - /** This counter provides upper 32 bytes of packets received with - * length field not equal to the valid packet size (greater than 1,500 - * but less than 1,536) */ - nveu64_t mmc_rx_outofrangetype_h; - /** This counter provides the number of good and valid Pause packets - * received */ - nveu64_t mmc_rx_pause_frames; - /** This counter provides upper 32 bytes of good and valid Pause packets - * received */ - nveu64_t mmc_rx_pause_frames_h; - /** This counter provides the number of missed received packets - * because of FIFO overflow in DWC_ether_qos */ - nveu64_t mmc_rx_fifo_overflow; - /** This counter provides upper 32 bytes of missed received packets - * because of FIFO overflow in DWC_ether_qos */ - nveu64_t mmc_rx_fifo_overflow_h; - /** This counter provides the number of good and bad VLAN packets - * received */ - nveu64_t mmc_rx_vlan_frames_gb; - /** This counter provides upper 32 bytes of good and bad VLAN packets - * received */ - nveu64_t mmc_rx_vlan_frames_gb_h; - /** This counter provides the number of packets received with error - * because of watchdog timeout error */ - nveu64_t mmc_rx_watchdog_error; - /** This counter provides the number of packets received with Receive - * error or Packet Extension error on the GMII or MII interface */ - nveu64_t mmc_rx_receive_error; - /** This counter provides the number of packets received with Receive - * error or Packet Extension error on the GMII or MII interface */ - nveu64_t mmc_rx_ctrl_frames_g; - /** This counter provides the number of microseconds Tx LPI is asserted - * in the MAC controller */ - nveu64_t mmc_tx_lpi_usec_cntr; - /** This counter provides the number of times MAC controller has - * entered Tx LPI. */ - nveu64_t mmc_tx_lpi_tran_cntr; - /** This counter provides the number of microseconds Rx LPI is asserted - * in the MAC controller */ - nveu64_t mmc_rx_lpi_usec_cntr; - /** This counter provides the number of times MAC controller has - * entered Rx LPI.*/ - nveu64_t mmc_rx_lpi_tran_cntr; - /** This counter provides the number of good IPv4 datagrams received - * with the TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv4_gd; - /** This counter provides upper 32 bytes of good IPv4 datagrams received - * with the TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv4_gd_h; - /** RxIPv4 Header Error Packets */ - nveu64_t mmc_rx_ipv4_hderr; - /** RxIPv4 of upper 32 bytes of Header Error Packets */ - nveu64_t mmc_rx_ipv4_hderr_h; - /** This counter provides the number of IPv4 datagram packets received - * that did not have a TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv4_nopay; - /** This counter provides upper 32 bytes of IPv4 datagram packets - * received that did not have a TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv4_nopay_h; - /** This counter provides the number of good IPv4 datagrams received - * with fragmentation */ - nveu64_t mmc_rx_ipv4_frag; - /** This counter provides upper 32 bytes of good IPv4 datagrams received - * with fragmentation */ - nveu64_t mmc_rx_ipv4_frag_h; - /** This counter provides the number of good IPv4 datagrams received - * that had a UDP payload with checksum disabled */ - nveu64_t mmc_rx_ipv4_udsbl; - /** This counter provides upper 32 bytes of good IPv4 datagrams received - * that had a UDP payload with checksum disabled */ - nveu64_t mmc_rx_ipv4_udsbl_h; - /** This counter provides the number of good IPv6 datagrams received - * with the TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv6_gd_octets; - /** This counter provides upper 32 bytes of good IPv6 datagrams received - * with the TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv6_gd_octets_h; - /** This counter provides the number of IPv6 datagrams received - * with header (length or version mismatch) errors */ - nveu64_t mmc_rx_ipv6_hderr_octets; - /** This counter provides the number of IPv6 datagrams received - * with header (length or version mismatch) errors */ - nveu64_t mmc_rx_ipv6_hderr_octets_h; - /** This counter provides the number of IPv6 datagram packets received - * that did not have a TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv6_nopay_octets; - /** This counter provides upper 32 bytes of IPv6 datagram packets - * received that did not have a TCP, UDP, or ICMP payload */ - nveu64_t mmc_rx_ipv6_nopay_octets_h; - /* Protocols */ - /** This counter provides the number of good IP datagrams received by - * DWC_ether_qos with a good UDP payload */ - nveu64_t mmc_rx_udp_gd; - /** This counter provides upper 32 bytes of good IP datagrams received - * by DWC_ether_qos with a good UDP payload */ - nveu64_t mmc_rx_udp_gd_h; - /** This counter provides the number of good IP datagrams received by - * DWC_ether_qos with a good UDP payload. This counter is not updated - * when the RxIPv4_UDP_Checksum_Disabled_Packets counter is - * incremented */ - nveu64_t mmc_rx_udp_err; - /** This counter provides upper 32 bytes of good IP datagrams received - * by DWC_ether_qos with a good UDP payload. This counter is not updated - * when the RxIPv4_UDP_Checksum_Disabled_Packets counter is - * incremented */ - nveu64_t mmc_rx_udp_err_h; - /** This counter provides the number of good IP datagrams received - * with a good TCP payload */ - nveu64_t mmc_rx_tcp_gd; - /** This counter provides the number of good IP datagrams received - * with a good TCP payload */ - nveu64_t mmc_rx_tcp_gd_h; - /** This counter provides upper 32 bytes of good IP datagrams received - * with a good TCP payload */ - nveu64_t mmc_rx_tcp_err; - /** This counter provides upper 32 bytes of good IP datagrams received - * with a good TCP payload */ - nveu64_t mmc_rx_tcp_err_h; - /** This counter provides the number of good IP datagrams received - * with a good ICMP payload */ - nveu64_t mmc_rx_icmp_gd; - /** This counter provides upper 32 bytes of good IP datagrams received - * with a good ICMP payload */ - nveu64_t mmc_rx_icmp_gd_h; - /** This counter provides the number of good IP datagrams received - * whose ICMP payload has a checksum error */ - nveu64_t mmc_rx_icmp_err; - /** This counter provides upper 32 bytes of good IP datagrams received - * whose ICMP payload has a checksum error */ - nveu64_t mmc_rx_icmp_err_h; - /** This counter provides the number of bytes received by DWC_ether_qos - * in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv4_gd_octets; - /** This counter provides upper 32 bytes received by DWC_ether_qos - * in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv4_gd_octets_h; - /** This counter provides the number of bytes received in IPv4 datagram - * with header errors (checksum, length, version mismatch). The value - * in the Length field of IPv4 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv4_hderr_octets; - /** This counter provides upper 32 bytes received in IPv4 datagram - * with header errors (checksum, length, version mismatch). The value - * in the Length field of IPv4 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv4_hderr_octets_h; - /** This counter provides the number of bytes received in IPv4 datagram - * that did not have a TCP, UDP, or ICMP payload. The value in the - * Length field of IPv4 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv4_nopay_octets; - /** This counter provides upper 32 bytes received in IPv4 datagram - * that did not have a TCP, UDP, or ICMP payload. The value in the - * Length field of IPv4 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv4_nopay_octets_h; - /** This counter provides the number of bytes received in fragmented - * IPv4 datagrams. The value in the Length field of IPv4 header is - * used to update this counter. (Ethernet header, FCS, pad, or IP pad - * bytes are not included in this counter */ - nveu64_t mmc_rx_ipv4_frag_octets; - /** This counter provides upper 32 bytes received in fragmented - * IPv4 datagrams. The value in the Length field of IPv4 header is - * used to update this counter. (Ethernet header, FCS, pad, or IP pad - * bytes are not included in this counter */ - nveu64_t mmc_rx_ipv4_frag_octets_h; - /** This counter provides the number of bytes received in a UDP segment - * that had the UDP checksum disabled. This counter does not count IP - * Header bytes. (Ethernet header, FCS, pad, or IP pad bytes are not - * included in this counter */ - nveu64_t mmc_rx_ipv4_udsbl_octets; - /** This counter provides upper 32 bytes received in a UDP segment - * that had the UDP checksum disabled. This counter does not count IP - * Header bytes. (Ethernet header, FCS, pad, or IP pad bytes are not - * included in this counter */ - nveu64_t mmc_rx_ipv4_udsbl_octets_h; - /** This counter provides the number of bytes received in good IPv6 - * datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, - * FCS, pad, or IP pad bytes are not included in this counter */ - nveu64_t mmc_rx_ipv6_gd; - /** This counter provides upper 32 bytes received in good IPv6 - * datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, - * FCS, pad, or IP pad bytes are not included in this counter */ - nveu64_t mmc_rx_ipv6_gd_h; - /** This counter provides the number of bytes received in IPv6 datagrams - * with header errors (length, version mismatch). The value in the - * Length field of IPv6 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included in - * this counter */ - nveu64_t mmc_rx_ipv6_hderr; - /** This counter provides upper 32 bytes received in IPv6 datagrams - * with header errors (length, version mismatch). The value in the - * Length field of IPv6 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included in - * this counter */ - nveu64_t mmc_rx_ipv6_hderr_h; - /** This counter provides the number of bytes received in IPv6 - * datagrams that did not have a TCP, UDP, or ICMP payload. The value - * in the Length field of IPv6 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv6_nopay; - /** This counter provides upper 32 bytes received in IPv6 - * datagrams that did not have a TCP, UDP, or ICMP payload. The value - * in the Length field of IPv6 header is used to update this counter. - * (Ethernet header, FCS, pad, or IP pad bytes are not included - * in this counter */ - nveu64_t mmc_rx_ipv6_nopay_h; - /* Protocols */ - /** This counter provides the number of bytes received in a good UDP - * segment. This counter does not count IP header bytes */ - nveu64_t mmc_rx_udp_gd_octets; - /** This counter provides upper 32 bytes received in a good UDP - * segment. This counter does not count IP header bytes */ - nveu64_t mmc_rx_udp_gd_octets_h; - /** This counter provides the number of bytes received in a UDP - * segment that had checksum errors. This counter does not count - * IP header bytes */ - nveu64_t mmc_rx_udp_err_octets; - /** This counter provides upper 32 bytes received in a UDP - * segment that had checksum errors. This counter does not count - * IP header bytes */ - nveu64_t mmc_rx_udp_err_octets_h; - /** This counter provides the number of bytes received in a good - * TCP segment. This counter does not count IP header bytes */ - nveu64_t mmc_rx_tcp_gd_octets; - /** This counter provides upper 32 bytes received in a good - * TCP segment. This counter does not count IP header bytes */ - nveu64_t mmc_rx_tcp_gd_octets_h; - /** This counter provides the number of bytes received in a TCP - * segment that had checksum errors. This counter does not count - * IP header bytes */ - nveu64_t mmc_rx_tcp_err_octets; - /** This counter provides upper 32 bytes received in a TCP - * segment that had checksum errors. This counter does not count - * IP header bytes */ - nveu64_t mmc_rx_tcp_err_octets_h; - /** This counter provides the number of bytes received in a good - * ICMP segment. This counter does not count IP header bytes */ - nveu64_t mmc_rx_icmp_gd_octets; - /** This counter provides upper 32 bytes received in a good - * ICMP segment. This counter does not count IP header bytes */ - nveu64_t mmc_rx_icmp_gd_octets_h; - /** This counter provides the number of bytes received in a ICMP - * segment that had checksum errors. This counter does not count - * IP header bytes */ - nveu64_t mmc_rx_icmp_err_octets; - /** This counter provides upper 32 bytes received in a ICMP - * segment that had checksum errors. This counter does not count - * IP header bytes */ - nveu64_t mmc_rx_icmp_err_octets_h; - /** This counter provides the number of additional mPackets - * transmitted due to preemption */ - nveu64_t mmc_tx_fpe_frag_cnt; - /** This counter provides the count of number of times a hold - * request is given to MAC */ - nveu64_t mmc_tx_fpe_hold_req_cnt; - /** This counter provides the number of MAC frames with reassembly - * errors on the Receiver, due to mismatch in the fragment - * count value */ - nveu64_t mmc_rx_packet_reass_err_cnt; - /** This counter the number of received MAC frames rejected - * due to unknown SMD value and MAC frame fragments rejected due - * to arriving with an SMD-C when there was no preceding preempted - * frame */ - nveu64_t mmc_rx_packet_smd_err_cnt; - /** This counter provides the number of MAC frames that were - * successfully reassembled and delivered to MAC */ - nveu64_t mmc_rx_packet_asm_ok_cnt; - /** This counter provides the number of additional mPackets received - * due to preemption */ - nveu64_t mmc_rx_fpe_fragment_cnt; -}; - #ifndef OSI_STRIPPED_LIB /** * @brief osi_xtra_stat_counters - OSI core extra stat counters diff --git a/include/nvethernetrm_export.h b/include/nvethernetrm_export.h new file mode 100644 index 0000000..bd5ea96 --- /dev/null +++ b/include/nvethernetrm_export.h @@ -0,0 +1,782 @@ +/* + * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef INCLUDED_NVETHERNETRM_EXPORT_H +#define INCLUDED_NVETHERNETRM_EXPORT_H + +#include "../osi/common/type.h" + +/** + * @addtogroup Helper MACROS + * + * @brief EQOS generic helper MACROS. + * @{ + */ +#define OSI_MAX_24BITS 0xFFFFFFU +#define OSI_MAX_28BITS 0xFFFFFFFU +#define OSI_MAX_32BITS 0xFFFFFFFFU +#define OSI_MASK_16BITS 0xFFFFU +#define OSI_MASK_20BITS 0xFFFFFU +#define OSI_MASK_24BITS 0xFFFFFFU +#define OSI_GCL_SIZE_64 64U +#define OSI_GCL_SIZE_128 128U +#define OSI_GCL_SIZE_256 256U +#define OSI_GCL_SIZE_512 512U +#define OSI_GCL_SIZE_1024 1024U + +/** + * @addtogroup Flexible Receive Parser related information + * + * @brief Flexible Receive Parser commands, table size and other defines + * @{ + */ +/* Match data defines */ +#define OSI_FRP_MATCH_DATA_MAX 12U +/** @} */ + +/** + * @addtogroup MTL queue operation mode + * + * @brief MTL queue operation mode options + * @{ + */ +#define OSI_MTL_QUEUE_AVB 0x1U +#define OSI_MTL_QUEUE_ENABLE 0x2U +#define OSI_MTL_QUEUE_MODEMAX 0x3U +/** @} */ + +/** + * @addtogroup EQOS_MTL MTL queue AVB algorithm mode + * + * @brief MTL AVB queue algorithm type + * @{ + */ +#define OSI_MTL_TXQ_AVALG_CBS 1U +#define OSI_MTL_TXQ_AVALG_SP 0U +/** @} */ + +/** + * @addtogroup Helper MACROS + * + * @brief EQOS generic helper MACROS. + * @{ + */ +/* L2 DA filter mode(enable/disable) */ +#define OSI_OPER_EN_L2_DA_INV OSI_BIT(4) +#define OSI_OPER_DIS_L2_DA_INV OSI_BIT(5) + +/* Ethernet Address length */ +#define OSI_ETH_ALEN 6U +#define OSI_MAX_TC_NUM 8U +/** @} */ + +#pragma pack(push, 1) +/** + * @brief FRP command structure for OSD to OSI + */ +struct osi_core_frp_cmd { + /** FRP Command type */ + nveu32_t cmd; + /** OSD FRP ID */ + nve32_t frp_id; + /** OSD match data type */ + nveu8_t match_type; + /** OSD match data */ + nveu8_t match[OSI_FRP_MATCH_DATA_MAX]; + /** OSD match data length */ + nveu8_t match_length; + /** OSD Offset */ + nveu8_t offset; + /** OSD FRP filter mode flag */ + nveu8_t filter_mode; + /** OSD FRP Link ID */ + nve32_t next_frp_id; + /** OSD DMA Channel Selection */ + nveu32_t dma_sel; +}; + +/** + * @brief OSI Core avb data structure per queue. + */ +struct osi_core_avb_algorithm { + /** TX Queue/TC index */ + nveu32_t qindex; + /** CBS Algorithm enable(1) or disable(0) */ + nveu32_t algo; + /** When this bit is set, the accumulated credit parameter in the + * credit-based shaper algorithm logic is not reset to zero when + * there is positive credit and no packet to transmit in Channel. + * + * Expected values are enable(1) or disable(0) */ + nveu32_t credit_control; + /** idleSlopeCredit value required for CBS */ + nveu32_t idle_slope; + /** sendSlopeCredit value required for CBS */ + nveu32_t send_slope; + /** hiCredit value required for CBS */ + nveu32_t hi_credit; + /** lowCredit value required for CBS */ + nveu32_t low_credit; + /** Transmit queue operating mode + * + * 00: disable + * + * 01: avb + * + * 10: enable */ + nveu32_t oper_mode; + /** TC index */ + nveu32_t tcindex; +}; + +/** + * @brief OSI Core EST structure + */ +struct osi_est_config { + /** enable/disable */ + nveu32_t en_dis; + /** 64 bit base time register + * if both vlaues are 0, take ptp time to avoid BTRE + * index 0 for nsec, index 1 for sec + */ + nveu32_t btr[2]; + /** 64 bit base time offset index 0 for nsec, index 1 for sec */ + nveu32_t btr_offset[2]; + /** 40 bit cycle time register, index 0 for nsec, index 1 for sec */ + nveu32_t ctr[2]; + /** Configured Time Interval width + 7 bit extension register */ + nveu32_t ter; + /** size of the gate control list */ + nveu32_t llr; + /** data array 8 bit gate op + 24 execution time + * MGBE HW support GCL depth 256 */ + nveu32_t gcl[OSI_GCL_SIZE_256]; +}; + +/** + * @brief OSI Core FPE structure + */ +struct osi_fpe_config { + /** Queue Mask 1 preemption 0- express bit representation */ + nveu32_t tx_queue_preemption_enable; + /** RQ for all preemptable packets which are not filtered + * based on user priority or SA-DA + */ + nveu32_t rq; +}; + +/** + * @brief OSI core structure for filters + */ +struct osi_filter { + /** indicates operation needs to perform. refer to OSI_OPER_* */ + nveu32_t oper_mode; + /** Indicates the index of the filter to be modified. + * Filter index must be between 0 - 127 */ + nveu32_t index; + /** Ethernet MAC address to be added */ + nveu8_t mac_address[OSI_ETH_ALEN]; + /** Indicates dma channel routing enable(1) disable (0) */ + nveu32_t dma_routing; + /** indicates dma channel number to program */ + nveu32_t dma_chan; + /** filter will not consider byte in comparison + * Bit 5: MAC_Address${i}_High[15:8] + * Bit 4: MAC_Address${i}_High[7:0] + * Bit 3: MAC_Address${i}_Low[31:24] + * .. + * Bit 0: MAC_Address${i}_Low[7:0] */ + nveu32_t addr_mask; + /** src_dest: SA(1) or DA(0) */ + nveu32_t src_dest; + /** indicates one hot encoded DMA receive channels to program */ + nveu32_t dma_chansel; +}; + +/** + * @brief L3/L4 filter function dependent parameter + */ +struct osi_l3_l4_filter { + /** Indicates the index of the filter to be modified. + * Filter index must be between 0 - 7 */ + nveu32_t filter_no; + /** filter enable(1) or disable(0) */ + nveu32_t filter_enb_dis; + /** source(0) or destination(1) */ + nveu32_t src_dst_addr_match; + /** perfect(0) or inverse(1) */ + nveu32_t perfect_inverse_match; + /** ipv4 address */ + nveu8_t ip4_addr[4]; + /** ipv6 address */ + nveu16_t ip6_addr[8]; + /** Port number */ + nveu16_t port_no; +}; + +/** + * @brief OSI Core TSN error stats structure + */ +struct osi_tsn_stats { + /** Constant Gate Control Error */ + nveu64_t const_gate_ctr_err; + /** Head-Of-Line Blocking due to Scheduling */ + nveu64_t head_of_line_blk_sch; + /** Per TC Schedule Error */ + nveu64_t hlbs_q[OSI_MAX_TC_NUM]; + /** Head-Of-Line Blocking due to Frame Size */ + nveu64_t head_of_line_blk_frm; + /** Per TC Frame Size Error */ + nveu64_t hlbf_q[OSI_MAX_TC_NUM]; + /** BTR Error */ + nveu64_t base_time_reg_err; + /** Switch to Software Owned List Complete */ + nveu64_t sw_own_list_complete; +}; + +/** + * @brief osi_mmc_counters - The structure to hold RMON counter values + */ +struct osi_mmc_counters { + /** This counter provides the number of bytes transmitted, exclusive of + * preamble and retried bytes, in good and bad packets */ + nveu64_t mmc_tx_octetcount_gb; + /** This counter provides upper 32 bits of transmitted octet count */ + nveu64_t mmc_tx_octetcount_gb_h; + /** This counter provides the number of good and + * bad packets transmitted, exclusive of retried packets */ + nveu64_t mmc_tx_framecount_gb; + /** This counter provides upper 32 bits of transmitted good and bad + * packets count */ + nveu64_t mmc_tx_framecount_gb_h; + /** This counter provides number of good broadcast + * packets transmitted */ + nveu64_t mmc_tx_broadcastframe_g; + /** This counter provides upper 32 bits of transmitted good broadcast + * packets count */ + nveu64_t mmc_tx_broadcastframe_g_h; + /** This counter provides number of good multicast + * packets transmitted */ + nveu64_t mmc_tx_multicastframe_g; + /** This counter provides upper 32 bits of transmitted good multicast + * packet count */ + nveu64_t mmc_tx_multicastframe_g_h; + /** This counter provides the number of good and bad packets + * transmitted with length 64 bytes, exclusive of preamble and + * retried packets */ + nveu64_t mmc_tx_64_octets_gb; + /** This counter provides upper 32 bits of transmitted 64 octet size + * good and bad packets count */ + nveu64_t mmc_tx_64_octets_gb_h; + /** This counter provides the number of good and bad packets + * transmitted with length 65-127 bytes, exclusive of preamble and + * retried packets */ + nveu64_t mmc_tx_65_to_127_octets_gb; + /** Provides upper 32 bits of transmitted 65-to-127 octet size good and + * bad packets count */ + nveu64_t mmc_tx_65_to_127_octets_gb_h; + /** This counter provides the number of good and bad packets + * transmitted with length 128-255 bytes, exclusive of preamble and + * retried packets */ + nveu64_t mmc_tx_128_to_255_octets_gb; + /** This counter provides upper 32 bits of transmitted 128-to-255 + * octet size good and bad packets count */ + nveu64_t mmc_tx_128_to_255_octets_gb_h; + /** This counter provides the number of good and bad packets + * transmitted with length 256-511 bytes, exclusive of preamble and + * retried packets */ + nveu64_t mmc_tx_256_to_511_octets_gb; + /** This counter provides upper 32 bits of transmitted 256-to-511 + * octet size good and bad packets count. */ + nveu64_t mmc_tx_256_to_511_octets_gb_h; + /** This counter provides the number of good and bad packets + * transmitted with length 512-1023 bytes, exclusive of preamble and + * retried packets */ + nveu64_t mmc_tx_512_to_1023_octets_gb; + /** This counter provides upper 32 bits of transmitted 512-to-1023 + * octet size good and bad packets count.*/ + nveu64_t mmc_tx_512_to_1023_octets_gb_h; + /** This counter provides the number of good and bad packets + * transmitted with length 1024-max bytes, exclusive of preamble and + * retried packets */ + nveu64_t mmc_tx_1024_to_max_octets_gb; + /** This counter provides upper 32 bits of transmitted 1024-tomaxsize + * octet size good and bad packets count. */ + nveu64_t mmc_tx_1024_to_max_octets_gb_h; + /** This counter provides the number of good and bad unicast packets */ + nveu64_t mmc_tx_unicast_gb; + /** This counter provides upper 32 bits of transmitted good bad + * unicast packets count */ + nveu64_t mmc_tx_unicast_gb_h; + /** This counter provides the number of good and bad + * multicast packets */ + nveu64_t mmc_tx_multicast_gb; + /** This counter provides upper 32 bits of transmitted good bad + * multicast packets count */ + nveu64_t mmc_tx_multicast_gb_h; + /** This counter provides the number of good and bad + * broadcast packets */ + nveu64_t mmc_tx_broadcast_gb; + /** This counter provides upper 32 bits of transmitted good bad + * broadcast packets count */ + nveu64_t mmc_tx_broadcast_gb_h; + /** This counter provides the number of abort packets due to + * underflow error */ + nveu64_t mmc_tx_underflow_error; + /** This counter provides upper 32 bits of abort packets due to + * underflow error */ + nveu64_t mmc_tx_underflow_error_h; + /** This counter provides the number of successfully transmitted + * packets after a single collision in the half-duplex mode */ + nveu64_t mmc_tx_singlecol_g; + /** This counter provides the number of successfully transmitted + * packets after a multi collision in the half-duplex mode */ + nveu64_t mmc_tx_multicol_g; + /** This counter provides the number of successfully transmitted + * after a deferral in the half-duplex mode */ + nveu64_t mmc_tx_deferred; + /** This counter provides the number of packets aborted because of + * late collision error */ + nveu64_t mmc_tx_latecol; + /** This counter provides the number of packets aborted because of + * excessive (16) collision errors */ + nveu64_t mmc_tx_exesscol; + /** This counter provides the number of packets aborted because of + * carrier sense error (no carrier or loss of carrier) */ + nveu64_t mmc_tx_carrier_error; + /** This counter provides the number of bytes transmitted, + * exclusive of preamble, only in good packets */ + nveu64_t mmc_tx_octetcount_g; + /** This counter provides upper 32 bytes of bytes transmitted, + * exclusive of preamble, only in good packets */ + nveu64_t mmc_tx_octetcount_g_h; + /** This counter provides the number of good packets transmitted */ + nveu64_t mmc_tx_framecount_g; + /** This counter provides upper 32 bytes of good packets transmitted */ + nveu64_t mmc_tx_framecount_g_h; + /** This counter provides the number of packets aborted because of + * excessive deferral error + * (deferred for more than two max-sized packet times) */ + nveu64_t mmc_tx_excessdef; + /** This counter provides the number of good Pause + * packets transmitted */ + nveu64_t mmc_tx_pause_frame; + /** This counter provides upper 32 bytes of good Pause + * packets transmitted */ + nveu64_t mmc_tx_pause_frame_h; + /** This counter provides the number of good VLAN packets transmitted */ + nveu64_t mmc_tx_vlan_frame_g; + /** This counter provides upper 32 bytes of good VLAN packets + * transmitted */ + nveu64_t mmc_tx_vlan_frame_g_h; + /** This counter provides the number of packets transmitted without + * errors and with length greater than the maxsize (1,518 or 1,522 bytes + * for VLAN tagged packets; 2000 bytes */ + nveu64_t mmc_tx_osize_frame_g; + /** This counter provides the number of good and bad packets received */ + nveu64_t mmc_rx_framecount_gb; + /** This counter provides upper 32 bytes of good and bad packets + * received */ + nveu64_t mmc_rx_framecount_gb_h; + /** This counter provides the number of bytes received by DWC_ther_qos, + * exclusive of preamble, in good and bad packets */ + nveu64_t mmc_rx_octetcount_gb; + /** This counter provides upper 32 bytes of bytes received by + * DWC_ether_qos, exclusive of preamble, in good and bad packets */ + nveu64_t mmc_rx_octetcount_gb_h; + /** This counter provides the number of bytes received by DWC_ether_qos, + * exclusive of preamble, in good and bad packets */ + nveu64_t mmc_rx_octetcount_g; + /** This counter provides upper 32 bytes of bytes received by + * DWC_ether_qos, exclusive of preamble, in good and bad packets */ + nveu64_t mmc_rx_octetcount_g_h; + /** This counter provides the number of good + * broadcast packets received */ + nveu64_t mmc_rx_broadcastframe_g; + /** This counter provides upper 32 bytes of good + * broadcast packets received */ + nveu64_t mmc_rx_broadcastframe_g_h; + /** This counter provides the number of good + * multicast packets received */ + nveu64_t mmc_rx_multicastframe_g; + /** This counter provides upper 32 bytes of good + * multicast packets received */ + nveu64_t mmc_rx_multicastframe_g_h; + /** This counter provides the number of packets + * received with CRC error */ + nveu64_t mmc_rx_crc_error; + /** This counter provides upper 32 bytes of packets + * received with CRC error */ + nveu64_t mmc_rx_crc_error_h; + /** This counter provides the number of packets received with + * alignment (dribble) error. It is valid only in 10/100 mode */ + nveu64_t mmc_rx_align_error; + /** This counter provides the number of packets received with + * runt (length less than 64 bytes and CRC error) error */ + nveu64_t mmc_rx_runt_error; + /** This counter provides the number of giant packets received with + * length (including CRC) greater than 1,518 bytes (1,522 bytes for + * VLAN tagged) and with CRC error */ + nveu64_t mmc_rx_jabber_error; + /** This counter provides the number of packets received with length + * less than 64 bytes, without any errors */ + nveu64_t mmc_rx_undersize_g; + /** This counter provides the number of packets received without error, + * with length greater than the maxsize */ + nveu64_t mmc_rx_oversize_g; + /** This counter provides the number of good and bad packets received + * with length 64 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_64_octets_gb; + /** This counter provides upper 32 bytes of good and bad packets + * received with length 64 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_64_octets_gb_h; + /** This counter provides the number of good and bad packets received + * with length 65-127 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_65_to_127_octets_gb; + /** This counter provides upper 32 bytes of good and bad packets + * received with length 65-127 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_65_to_127_octets_gb_h; + /** This counter provides the number of good and bad packets received + * with length 128-255 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_128_to_255_octets_gb; + /** This counter provides upper 32 bytes of good and bad packets + * received with length 128-255 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_128_to_255_octets_gb_h; + /** This counter provides the number of good and bad packets received + * with length 256-511 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_256_to_511_octets_gb; + /** This counter provides upper 32 bytes of good and bad packets + * received with length 256-511 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_256_to_511_octets_gb_h; + /** This counter provides the number of good and bad packets received + * with length 512-1023 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_512_to_1023_octets_gb; + /** This counter provides upper 32 bytes of good and bad packets + * received with length 512-1023 bytes, exclusive of the preamble */ + nveu64_t mmc_rx_512_to_1023_octets_gb_h; + /** This counter provides the number of good and bad packets received + * with length 1024-maxbytes, exclusive of the preamble */ + nveu64_t mmc_rx_1024_to_max_octets_gb; + /** This counter provides upper 32 bytes of good and bad packets + * received with length 1024-maxbytes, exclusive of the preamble */ + nveu64_t mmc_rx_1024_to_max_octets_gb_h; + /** This counter provides the number of good unicast packets received */ + nveu64_t mmc_rx_unicast_g; + /** This counter provides upper 32 bytes of good unicast packets + * received */ + nveu64_t mmc_rx_unicast_g_h; + /** This counter provides the number of packets received with length + * error (Length Type field not equal to packet size), for all packets + * with valid length field */ + nveu64_t mmc_rx_length_error; + /** This counter provides upper 32 bytes of packets received with + * length error (Length Type field not equal to packet size), for all + * packets with valid length field */ + nveu64_t mmc_rx_length_error_h; + /** This counter provides the number of packets received with length + * field not equal to the valid packet size (greater than 1,500 but + * less than 1,536) */ + nveu64_t mmc_rx_outofrangetype; + /** This counter provides upper 32 bytes of packets received with + * length field not equal to the valid packet size (greater than 1,500 + * but less than 1,536) */ + nveu64_t mmc_rx_outofrangetype_h; + /** This counter provides the number of good and valid Pause packets + * received */ + nveu64_t mmc_rx_pause_frames; + /** This counter provides upper 32 bytes of good and valid Pause packets + * received */ + nveu64_t mmc_rx_pause_frames_h; + /** This counter provides the number of missed received packets + * because of FIFO overflow in DWC_ether_qos */ + nveu64_t mmc_rx_fifo_overflow; + /** This counter provides upper 32 bytes of missed received packets + * because of FIFO overflow in DWC_ether_qos */ + nveu64_t mmc_rx_fifo_overflow_h; + /** This counter provides the number of good and bad VLAN packets + * received */ + nveu64_t mmc_rx_vlan_frames_gb; + /** This counter provides upper 32 bytes of good and bad VLAN packets + * received */ + nveu64_t mmc_rx_vlan_frames_gb_h; + /** This counter provides the number of packets received with error + * because of watchdog timeout error */ + nveu64_t mmc_rx_watchdog_error; + /** This counter provides the number of packets received with Receive + * error or Packet Extension error on the GMII or MII interface */ + nveu64_t mmc_rx_receive_error; + /** This counter provides the number of packets received with Receive + * error or Packet Extension error on the GMII or MII interface */ + nveu64_t mmc_rx_ctrl_frames_g; + /** This counter provides the number of microseconds Tx LPI is asserted + * in the MAC controller */ + nveu64_t mmc_tx_lpi_usec_cntr; + /** This counter provides the number of times MAC controller has + * entered Tx LPI. */ + nveu64_t mmc_tx_lpi_tran_cntr; + /** This counter provides the number of microseconds Rx LPI is asserted + * in the MAC controller */ + nveu64_t mmc_rx_lpi_usec_cntr; + /** This counter provides the number of times MAC controller has + * entered Rx LPI.*/ + nveu64_t mmc_rx_lpi_tran_cntr; + /** This counter provides the number of good IPv4 datagrams received + * with the TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv4_gd; + /** This counter provides upper 32 bytes of good IPv4 datagrams received + * with the TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv4_gd_h; + /** RxIPv4 Header Error Packets */ + nveu64_t mmc_rx_ipv4_hderr; + /** RxIPv4 of upper 32 bytes of Header Error Packets */ + nveu64_t mmc_rx_ipv4_hderr_h; + /** This counter provides the number of IPv4 datagram packets received + * that did not have a TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv4_nopay; + /** This counter provides upper 32 bytes of IPv4 datagram packets + * received that did not have a TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv4_nopay_h; + /** This counter provides the number of good IPv4 datagrams received + * with fragmentation */ + nveu64_t mmc_rx_ipv4_frag; + /** This counter provides upper 32 bytes of good IPv4 datagrams received + * with fragmentation */ + nveu64_t mmc_rx_ipv4_frag_h; + /** This counter provides the number of good IPv4 datagrams received + * that had a UDP payload with checksum disabled */ + nveu64_t mmc_rx_ipv4_udsbl; + /** This counter provides upper 32 bytes of good IPv4 datagrams received + * that had a UDP payload with checksum disabled */ + nveu64_t mmc_rx_ipv4_udsbl_h; + /** This counter provides the number of good IPv6 datagrams received + * with the TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv6_gd_octets; + /** This counter provides upper 32 bytes of good IPv6 datagrams received + * with the TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv6_gd_octets_h; + /** This counter provides the number of IPv6 datagrams received + * with header (length or version mismatch) errors */ + nveu64_t mmc_rx_ipv6_hderr_octets; + /** This counter provides the number of IPv6 datagrams received + * with header (length or version mismatch) errors */ + nveu64_t mmc_rx_ipv6_hderr_octets_h; + /** This counter provides the number of IPv6 datagram packets received + * that did not have a TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv6_nopay_octets; + /** This counter provides upper 32 bytes of IPv6 datagram packets + * received that did not have a TCP, UDP, or ICMP payload */ + nveu64_t mmc_rx_ipv6_nopay_octets_h; + /* Protocols */ + /** This counter provides the number of good IP datagrams received by + * DWC_ether_qos with a good UDP payload */ + nveu64_t mmc_rx_udp_gd; + /** This counter provides upper 32 bytes of good IP datagrams received + * by DWC_ether_qos with a good UDP payload */ + nveu64_t mmc_rx_udp_gd_h; + /** This counter provides the number of good IP datagrams received by + * DWC_ether_qos with a good UDP payload. This counter is not updated + * when the RxIPv4_UDP_Checksum_Disabled_Packets counter is + * incremented */ + nveu64_t mmc_rx_udp_err; + /** This counter provides upper 32 bytes of good IP datagrams received + * by DWC_ether_qos with a good UDP payload. This counter is not updated + * when the RxIPv4_UDP_Checksum_Disabled_Packets counter is + * incremented */ + nveu64_t mmc_rx_udp_err_h; + /** This counter provides the number of good IP datagrams received + * with a good TCP payload */ + nveu64_t mmc_rx_tcp_gd; + /** This counter provides the number of good IP datagrams received + * with a good TCP payload */ + nveu64_t mmc_rx_tcp_gd_h; + /** This counter provides upper 32 bytes of good IP datagrams received + * with a good TCP payload */ + nveu64_t mmc_rx_tcp_err; + /** This counter provides upper 32 bytes of good IP datagrams received + * with a good TCP payload */ + nveu64_t mmc_rx_tcp_err_h; + /** This counter provides the number of good IP datagrams received + * with a good ICMP payload */ + nveu64_t mmc_rx_icmp_gd; + /** This counter provides upper 32 bytes of good IP datagrams received + * with a good ICMP payload */ + nveu64_t mmc_rx_icmp_gd_h; + /** This counter provides the number of good IP datagrams received + * whose ICMP payload has a checksum error */ + nveu64_t mmc_rx_icmp_err; + /** This counter provides upper 32 bytes of good IP datagrams received + * whose ICMP payload has a checksum error */ + nveu64_t mmc_rx_icmp_err_h; + /** This counter provides the number of bytes received by DWC_ether_qos + * in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv4_gd_octets; + /** This counter provides upper 32 bytes received by DWC_ether_qos + * in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv4_gd_octets_h; + /** This counter provides the number of bytes received in IPv4 datagram + * with header errors (checksum, length, version mismatch). The value + * in the Length field of IPv4 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv4_hderr_octets; + /** This counter provides upper 32 bytes received in IPv4 datagram + * with header errors (checksum, length, version mismatch). The value + * in the Length field of IPv4 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv4_hderr_octets_h; + /** This counter provides the number of bytes received in IPv4 datagram + * that did not have a TCP, UDP, or ICMP payload. The value in the + * Length field of IPv4 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv4_nopay_octets; + /** This counter provides upper 32 bytes received in IPv4 datagram + * that did not have a TCP, UDP, or ICMP payload. The value in the + * Length field of IPv4 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv4_nopay_octets_h; + /** This counter provides the number of bytes received in fragmented + * IPv4 datagrams. The value in the Length field of IPv4 header is + * used to update this counter. (Ethernet header, FCS, pad, or IP pad + * bytes are not included in this counter */ + nveu64_t mmc_rx_ipv4_frag_octets; + /** This counter provides upper 32 bytes received in fragmented + * IPv4 datagrams. The value in the Length field of IPv4 header is + * used to update this counter. (Ethernet header, FCS, pad, or IP pad + * bytes are not included in this counter */ + nveu64_t mmc_rx_ipv4_frag_octets_h; + /** This counter provides the number of bytes received in a UDP segment + * that had the UDP checksum disabled. This counter does not count IP + * Header bytes. (Ethernet header, FCS, pad, or IP pad bytes are not + * included in this counter */ + nveu64_t mmc_rx_ipv4_udsbl_octets; + /** This counter provides upper 32 bytes received in a UDP segment + * that had the UDP checksum disabled. This counter does not count IP + * Header bytes. (Ethernet header, FCS, pad, or IP pad bytes are not + * included in this counter */ + nveu64_t mmc_rx_ipv4_udsbl_octets_h; + /** This counter provides the number of bytes received in good IPv6 + * datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, + * FCS, pad, or IP pad bytes are not included in this counter */ + nveu64_t mmc_rx_ipv6_gd; + /** This counter provides upper 32 bytes received in good IPv6 + * datagrams encapsulating TCP, UDP, or ICMP data. (Ethernet header, + * FCS, pad, or IP pad bytes are not included in this counter */ + nveu64_t mmc_rx_ipv6_gd_h; + /** This counter provides the number of bytes received in IPv6 datagrams + * with header errors (length, version mismatch). The value in the + * Length field of IPv6 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included in + * this counter */ + nveu64_t mmc_rx_ipv6_hderr; + /** This counter provides upper 32 bytes received in IPv6 datagrams + * with header errors (length, version mismatch). The value in the + * Length field of IPv6 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included in + * this counter */ + nveu64_t mmc_rx_ipv6_hderr_h; + /** This counter provides the number of bytes received in IPv6 + * datagrams that did not have a TCP, UDP, or ICMP payload. The value + * in the Length field of IPv6 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv6_nopay; + /** This counter provides upper 32 bytes received in IPv6 + * datagrams that did not have a TCP, UDP, or ICMP payload. The value + * in the Length field of IPv6 header is used to update this counter. + * (Ethernet header, FCS, pad, or IP pad bytes are not included + * in this counter */ + nveu64_t mmc_rx_ipv6_nopay_h; + /* Protocols */ + /** This counter provides the number of bytes received in a good UDP + * segment. This counter does not count IP header bytes */ + nveu64_t mmc_rx_udp_gd_octets; + /** This counter provides upper 32 bytes received in a good UDP + * segment. This counter does not count IP header bytes */ + nveu64_t mmc_rx_udp_gd_octets_h; + /** This counter provides the number of bytes received in a UDP + * segment that had checksum errors. This counter does not count + * IP header bytes */ + nveu64_t mmc_rx_udp_err_octets; + /** This counter provides upper 32 bytes received in a UDP + * segment that had checksum errors. This counter does not count + * IP header bytes */ + nveu64_t mmc_rx_udp_err_octets_h; + /** This counter provides the number of bytes received in a good + * TCP segment. This counter does not count IP header bytes */ + nveu64_t mmc_rx_tcp_gd_octets; + /** This counter provides upper 32 bytes received in a good + * TCP segment. This counter does not count IP header bytes */ + nveu64_t mmc_rx_tcp_gd_octets_h; + /** This counter provides the number of bytes received in a TCP + * segment that had checksum errors. This counter does not count + * IP header bytes */ + nveu64_t mmc_rx_tcp_err_octets; + /** This counter provides upper 32 bytes received in a TCP + * segment that had checksum errors. This counter does not count + * IP header bytes */ + nveu64_t mmc_rx_tcp_err_octets_h; + /** This counter provides the number of bytes received in a good + * ICMP segment. This counter does not count IP header bytes */ + nveu64_t mmc_rx_icmp_gd_octets; + /** This counter provides upper 32 bytes received in a good + * ICMP segment. This counter does not count IP header bytes */ + nveu64_t mmc_rx_icmp_gd_octets_h; + /** This counter provides the number of bytes received in a ICMP + * segment that had checksum errors. This counter does not count + * IP header bytes */ + nveu64_t mmc_rx_icmp_err_octets; + /** This counter provides upper 32 bytes received in a ICMP + * segment that had checksum errors. This counter does not count + * IP header bytes */ + nveu64_t mmc_rx_icmp_err_octets_h; + /** This counter provides the number of additional mPackets + * transmitted due to preemption */ + nveu64_t mmc_tx_fpe_frag_cnt; + /** This counter provides the count of number of times a hold + * request is given to MAC */ + nveu64_t mmc_tx_fpe_hold_req_cnt; + /** This counter provides the number of MAC frames with reassembly + * errors on the Receiver, due to mismatch in the fragment + * count value */ + nveu64_t mmc_rx_packet_reass_err_cnt; + /** This counter the number of received MAC frames rejected + * due to unknown SMD value and MAC frame fragments rejected due + * to arriving with an SMD-C when there was no preceding preempted + * frame */ + nveu64_t mmc_rx_packet_smd_err_cnt; + /** This counter provides the number of MAC frames that were + * successfully reassembled and delivered to MAC */ + nveu64_t mmc_rx_packet_asm_ok_cnt; + /** This counter provides the number of additional mPackets received + * due to preemption */ + nveu64_t mmc_rx_fpe_fragment_cnt; +}; + +#pragma pack(pop) +#endif /* INCLUDED_NVETHERNETRM_EXPORT_H */ diff --git a/include/osi_common.h b/include/osi_common.h index 3b1834c..6e3f27f 100644 --- a/include/osi_common.h +++ b/include/osi_common.h @@ -70,6 +70,22 @@ /** @} */ #ifndef OSI_STRIPPED_LIB + +/** + * @addtogroup Helper MACROS + * + * @brief EQOS generic helper MACROS. + * @{ + */ +#define OSI_PAUSE_FRAMES_ENABLE 0U +#define OSI_PTP_REQ_CLK_FREQ 250000000U +#define OSI_FLOW_CTRL_DISABLE 0U + +#define OSI_ADDRESS_32BIT 0 +#define OSI_ADDRESS_40BIT 1 +#define OSI_ADDRESS_48BIT 2 +/** @ } */ + /** * @addtogroup - LPI-Timers LPI configuration macros * @@ -117,34 +133,7 @@ /** @} */ #endif /* !OSI_STRIPPED_LIB */ -/** - * @addtogroup Helper Helper MACROS - * - * @brief EQOS generic helper MACROS. - * @{ - */ -#ifndef OSI_STRIPPED_LIB -#define OSI_PAUSE_FRAMES_ENABLE 0U -#define OSI_PTP_REQ_CLK_FREQ 250000000U -#define OSI_FLOW_CTRL_DISABLE 0U -#define OSI_MAX_24BITS 0xFFFFFFU -#define OSI_MAX_28BITS 0xFFFFFFFU -#define OSI_MASK_20BITS 0xFFFFFU -#define OSI_MASK_24BITS 0xFFFFFFU -#define OSI_GCL_SIZE_64 64U -#define OSI_GCL_SIZE_128 128U -#define OSI_GCL_SIZE_256 256U -#define OSI_GCL_SIZE_512 512U -#define OSI_GCL_SIZE_1024 1024U - -#define OSI_ADDRESS_32BIT 0 -#define OSI_ADDRESS_40BIT 1 -#define OSI_ADDRESS_48BIT 2 -#endif /* !OSI_STRIPPED_LIB */ - #define OSI_POLL_COUNT 1000U -#define OSI_MAX_32BITS 0xFFFFFFFFU -#define OSI_MASK_16BITS 0xFFFFU #ifndef UINT_MAX #define UINT_MAX (~0U) #endif @@ -165,15 +154,15 @@ /* log levels */ #define OSI_LOG_INFO 1U +#ifndef OSI_STRIPPED_LIB +#define OSI_LOG_WARN 2U +#endif /* OSI_STRIPPED_LIB */ #define OSI_LOG_ERR 3U /* Error types */ #define OSI_LOG_ARG_OUTOFBOUND 1U #define OSI_LOG_ARG_INVALID 2U #define OSI_LOG_ARG_HW_FAIL 4U -#ifndef OSI_STRIPPED_LIB -#define OSI_LOG_WARN 2U #define OSI_LOG_ARG_OPNOTSUPP 3U -#endif /* !OSI_STRIPPED_LIB */ /* Default maximum Giant Packet Size Limit is 16K */ #define OSI_MAX_MTU_SIZE 16383U @@ -256,30 +245,6 @@ #define OSI_DEBUG_TYPE_STRUCTS 3U #endif /* OSI_DEBUG */ -#ifndef OSI_STRIPPED_LIB -/** - * @addtogroup MTL queue operation mode - * - * @brief MTL queue operation mode options - * @{ - */ -#define OSI_MTL_QUEUE_DISABLED 0x0U -#define OSI_MTL_QUEUE_AVB 0x1U -#define OSI_MTL_QUEUE_ENABLE 0x2U -#define OSI_MTL_QUEUE_MODEMAX 0x3U -/** @} */ - -/** - * @addtogroup EQOS_MTL MTL queue AVB algorithm mode - * - * @brief MTL AVB queue algorithm type - * @{ - */ -#define OSI_MTL_TXQ_AVALG_CBS 1U -#define OSI_MTL_TXQ_AVALG_SP 0U -/** @} */ -#endif /* OSI_STRIPPED_LIB */ - /** * @brief unused function attribute */ diff --git a/include/osi_core.h b/include/osi_core.h index d101b03..6f092f0 100644 --- a/include/osi_core.h +++ b/include/osi_core.h @@ -23,6 +23,7 @@ #ifndef INCLUDED_OSI_CORE_H #define INCLUDED_OSI_CORE_H +#include "nvethernetrm_export.h" #include #include "mmc.h" @@ -65,16 +66,17 @@ typedef my_lint_64 nvel64_t; #define OSI_CMD_RESET_MMC 12U #define OSI_CMD_MDC_CONFIG 1U #define OSI_CMD_MAC_LB 14U -#define OSI_CMD_GET_AVB 23U #define OSI_CMD_FLOW_CTRL 15U #define OSI_CMD_CONFIG_TXSTATUS 27U #define OSI_CMD_CONFIG_RX_CRC_CHECK 25U #define OSI_CMD_CONFIG_EEE 32U #define OSI_CMD_ARP_OFFLOAD 30U #define OSI_CMD_UPDATE_VLAN_ID 26U -#define OSI_CMD_SET_AVB 24U #define OSI_CMD_VLAN_FILTER 31U #define OSI_CMD_VALIDATE_CORE_REG 11U +#define OSI_CMD_CONFIG_PTP_OFFLOAD 34U +#define OSI_CMD_PTP_RXQ_ROUTE 35U +#define OSI_CMD_CONFIG_RSS 37U /** * @addtogroup PTP-offload PTP offload defines @@ -94,7 +96,6 @@ typedef my_lint_64 nvel64_t; #define OSI_MAC_TCR_CSC OSI_BIT(19) #define OSI_MAC_TCR_AV8021ASMEN OSI_BIT(28) -#define OSI_FLOW_CTRL_TX OSI_BIT(0) #define OSI_FLOW_CTRL_RX OSI_BIT(1) #endif /* !OSI_STRIPPED_LIB */ @@ -163,7 +164,6 @@ typedef my_lint_64 nvel64_t; #define OSI_INV_MATCH 1U #define OSI_AMASK_DISABLE 0U #define OSI_CHAN_ANY 0xFFU -#define OSI_MAX_TC_NUM 8U #define OSI_DFLT_MTU_SIZE 1500U #define OSI_MTU_SIZE_9000 9000U @@ -172,8 +172,7 @@ typedef my_lint_64 nvel64_t; #define OSI_EQOS_MAX_HASH_REGS 4U #endif /* !OSI_STRIPPED_LIB */ -#define OSI_ETH_ALEN 6U - +#define OSI_FLOW_CTRL_TX OSI_BIT(0) #define OSI_FULL_DUPLEX 1 #define OSI_HALF_DUPLEX 0 @@ -190,8 +189,6 @@ typedef my_lint_64 nvel64_t; #define OSI_OPER_DIS_PROMISC OSI_BIT(1) #define OSI_OPER_EN_ALLMULTI OSI_BIT(2) #define OSI_OPER_DIS_ALLMULTI OSI_BIT(3) -#define OSI_OPER_EN_L2_DA_INV OSI_BIT(4) -#define OSI_OPER_DIS_L2_DA_INV OSI_BIT(5) #define OSI_OPER_EN_PERFECT OSI_BIT(6) #define OSI_OPER_DIS_PERFECT OSI_BIT(7) #define OSI_OPER_ADDR_UPDATE OSI_BIT(8) @@ -224,7 +221,6 @@ typedef my_lint_64 nvel64_t; #define OSI_USXGMII_MODE_10G 2U #define OSI_USXGMII_MODE_5G 3U - /** * @addtogroup IOCTL OPS MACROS * @@ -239,6 +235,7 @@ typedef my_lint_64 nvel64_t; #define OSI_CMD_PAD_CALIBRATION 8U #define OSI_CMD_READ_MMC 9U #define OSI_CMD_GET_MAC_VER 10U +#define OSI_CMD_RESET_MMC 12U #define OSI_CMD_SET_MODE 16U #define OSI_CMD_SET_SPEED 17U #define OSI_CMD_L2_FILTER 18U @@ -246,13 +243,12 @@ typedef my_lint_64 nvel64_t; #define OSI_CMD_ADJ_FREQ 20U #define OSI_CMD_ADJ_TIME 21U #define OSI_CMD_CONFIG_PTP 22U +#define OSI_CMD_GET_AVB 23U +#define OSI_CMD_SET_AVB 24U #define OSI_CMD_GET_HW_FEAT 28U #define OSI_CMD_CONFIG_FW_ERR 29U #define OSI_CMD_SET_SYSTOHW_TIME 33U -#define OSI_CMD_CONFIG_PTP_OFFLOAD 34U -#define OSI_CMD_PTP_RXQ_ROUTE 35U #define OSI_CMD_CONFIG_FRP 36U -#define OSI_CMD_CONFIG_RSS 37U #define OSI_CMD_CONFIG_EST 38U #define OSI_CMD_CONFIG_FPE 39U #define OSI_CMD_READ_REG 40U @@ -320,20 +316,22 @@ typedef my_lint_64 nvel64_t; #define OSI_PTP_SSINC_6 6U /** @} */ -#ifndef OSI_STRIPPED_LIB /** * @addtogroup Flexible Receive Parser related information * * @brief Flexible Receive Parser commands, table size and other defines * @{ */ +#ifndef OSI_STRIPPED_LIB +#define OSI_FRP_CMD_MAX 3U +#define OSI_FRP_MATCH_MAX 10U +#endif /* !OSI_STRIPPED_LIB */ #define OSI_FRP_MAX_ENTRY 256U #define OSI_FRP_OFFSET_MAX 64U /* FRP Command types */ #define OSI_FRP_CMD_ADD 0U #define OSI_FRP_CMD_UPDATE 1U #define OSI_FRP_CMD_DEL 2U -#define OSI_FRP_CMD_MAX 3U /* FRP Filter mode defines */ #define OSI_FRP_MODE_ROUTE 0U #define OSI_FRP_MODE_DROP 1U @@ -345,7 +343,6 @@ typedef my_lint_64 nvel64_t; #define OSI_FRP_MODE_IM_LINK 7U #define OSI_FRP_MODE_MAX 8U /* Match data defines */ -#define OSI_FRP_MATCH_DATA_MAX 12U #define OSI_FRP_MATCH_NORMAL 0U #define OSI_FRP_MATCH_L2_DA 1U #define OSI_FRP_MATCH_L2_SA 2U @@ -356,9 +353,7 @@ typedef my_lint_64 nvel64_t; #define OSI_FRP_MATCH_L4_S_TPORT 7U #define OSI_FRP_MATCH_L4_D_TPORT 8U #define OSI_FRP_MATCH_VLAN 9U -#define OSI_FRP_MATCH_MAX 10U /** @} */ -#endif /* !OSI_STRIPPED_LIB */ #ifdef HSI_SUPPORT /** @@ -428,34 +423,6 @@ extern nveu32_t hsi_err_code[][3]; struct osi_core_priv_data; -/** - * @brief OSI core structure for filters - */ -struct osi_filter { - /** indicates operation needs to perform. refer to OSI_OPER_* */ - nveu32_t oper_mode; - /** Indicates the index of the filter to be modified. - * Filter index must be between 0 - 127 */ - nveu32_t index; - /** Ethernet MAC address to be added */ - nveu8_t mac_address[OSI_ETH_ALEN]; - /** Indicates dma channel routing enable(1) disable (0) */ - nveu32_t dma_routing; - /** indicates dma channel number to program */ - nveu32_t dma_chan; - /** filter will not consider byte in comparison - * Bit 5: MAC_Address${i}_High[15:8] - * Bit 4: MAC_Address${i}_High[7:0] - * Bit 3: MAC_Address${i}_Low[31:24] - * .. - * Bit 0: MAC_Address${i}_Low[7:0] */ - nveu32_t addr_mask; - /** src_dest: SA(1) or DA(0) */ - nveu32_t src_dest; - /** indicates one hot encoded DMA receive channels to program */ - nveu32_t dma_chansel; -}; - #ifndef OSI_STRIPPED_LIB /** * @brief OSI core structure for RXQ route @@ -470,26 +437,6 @@ struct osi_rxq_route { nveu32_t idx; }; #endif -/** - * @brief L3/L4 filter function dependent parameter - */ -struct osi_l3_l4_filter { - /** Indicates the index of the filter to be modified. - * Filter index must be between 0 - 7 */ - nveu32_t filter_no; - /** filter enable(1) or disable(0) */ - nveu32_t filter_enb_dis; - /** source(0) or destination(1) */ - nveu32_t src_dst_addr_match; - /** perfect(0) or inverse(1) */ - nveu32_t perfect_inverse_match; - /** ipv4 address */ - nveu8_t ip4_addr[4]; - /** ipv6 address */ - nveu16_t ip6_addr[8]; - /** Port number */ - nveu16_t port_no; -}; /** * @brief struct osi_hw_features - MAC HW supported features. @@ -814,64 +761,6 @@ struct osi_vlan_filter { nveu32_t perfect_inverse_match; }; -/** - * @brief FRP Instruction configuration structure - */ -struct osi_core_frp_data { - /* Entry Match Data */ - nveu32_t match_data; - /* Entry Match Enable mask */ - nveu32_t match_en; - /* Entry Accept frame flag */ - nveu8_t accept_frame; - /* Entry Reject Frame flag */ - nveu8_t reject_frame; - /* Entry Inverse match flag */ - nveu8_t inverse_match; - /* Entry Next Instruction Control match flag */ - nveu8_t next_ins_ctrl; - /* Entry Frame offset in the packet data */ - nveu8_t frame_offset; - /* Entry OK Index - Next Instruction */ - nveu8_t ok_index; - /* Entry DMA Channel selection (1-bit for each channel) */ - nveu32_t dma_chsel; -}; - -/** - * @brief FRP command structure for OSD to OSI - */ -struct osi_core_frp_cmd { - /* FRP Command type */ - nveu32_t cmd; - /* OSD FRP ID */ - int frp_id; - /* OSD match data type */ - nveu8_t match_type; - /* OSD match data */ - nveu8_t match[OSI_FRP_MATCH_DATA_MAX]; - /* OSD match data length */ - nveu8_t match_length; - /* OSD Offset */ - nveu8_t offset; - /* OSD FRP filter mode flag */ - nveu8_t filter_mode; - /* OSD FRP Link ID */ - int next_frp_id; - /* OSD DMA Channel Selection */ - nveu32_t dma_sel; -}; - -/** - * @brief FRP Instruction table entry configuration structure - */ -struct osi_core_frp_entry { - /* FRP ID */ - int frp_id; - /* FRP Entry data structure */ - struct osi_core_frp_data data; -}; - /** * @brief L2 filter function dependent parameter */ @@ -882,40 +771,6 @@ struct osi_l2_da_filter { nveu32_t perfect_inverse_match; }; -/** - * @brief OSI Core avb data structure per queue. - */ -struct osi_core_avb_algorithm { - /** TX Queue/TC index */ - nveu32_t qindex; - /** CBS Algorithm enable(1) or disable(0) */ - nveu32_t algo; - /** When this bit is set, the accumulated credit parameter in the - * credit-based shaper algorithm logic is not reset to zero when - * there is positive credit and no packet to transmit in Channel. - * - * Expected values are enable(1) or disable(0) */ - nveu32_t credit_control; - /** idleSlopeCredit value required for CBS */ - nveu32_t idle_slope; - /** sendSlopeCredit value required for CBS */ - nveu32_t send_slope; - /** hiCredit value required for CBS */ - nveu32_t hi_credit; - /** lowCredit value required for CBS */ - nveu32_t low_credit; - /** Transmit queue operating mode - * - * 00: disable - * - * 01: avb - * - * 10: enable */ - nveu32_t oper_mode; - /** TC index */ - nveu32_t tcindex; -}; - /** * @brief struct ptp_offload_param - Parameter to support PTP offload. */ @@ -937,62 +792,6 @@ struct osi_pto_config { nveu32_t portid; }; -/** - * @brief OSI Core EST structure - */ -struct osi_est_config { - /** enable/disable */ - nveu32_t en_dis; - /** 64 bit base time register - * if both vlaues are 0, take ptp time to avoid BTRE - * index 0 for nsec, index 1 for sec - */ - nveu32_t btr[2]; - /** 64 bit base time offset index 0 for nsec, index 1 for sec */ - nveu32_t btr_offset[2]; - /** 40 bit cycle time register, index 0 for nsec, index 1 for sec */ - nveu32_t ctr[2]; - /** Configured Time Interval width + 7 bit extension register */ - nveu32_t ter; - /** size of the gate control list */ - nveu32_t llr; - /** data array 8 bit gate op + 24 execution time - * MGBE HW support GCL depth 256 */ - nveu32_t gcl[OSI_GCL_SIZE_256]; -}; - -/** - * @brief OSI Core FPE structure - */ -struct osi_fpe_config { - /** Queue Mask 1 preemption 0- express bit representation */ - nveu32_t tx_queue_preemption_enable; - /** RQ for all preemptable packets which are not filtered - * based on user priority or SA-DA - */ - nveu32_t rq; -}; - -/** - * @brief OSI Core TSN error stats structure - */ -struct osi_tsn_stats { - /** Constant Gate Control Error */ - nveu64_t const_gate_ctr_err; - /** Head-Of-Line Blocking due to Scheduling */ - nveu64_t head_of_line_blk_sch; - /** Per TC Schedule Error */ - nveu64_t hlbs_q[OSI_MAX_TC_NUM]; - /** Head-Of-Line Blocking due to Frame Size */ - nveu64_t head_of_line_blk_frm; - /** Per TC Frame Size Error */ - nveu64_t hlbf_q[OSI_MAX_TC_NUM]; - /** BTR Error */ - nveu64_t base_time_reg_err; - /** Switch to Software Owned List Complete */ - nveu64_t sw_own_list_complete; -}; - /** * @brief osi_core_rss - Struture used to store RSS Hash key and table * information. @@ -1073,7 +872,6 @@ struct osi_ptp_config { nveu32_t ptp_rx_queue; }; - /** * @brief osi_core_ptp_tsc_data - Struture used to store TSC and PTP time * information. @@ -1089,7 +887,6 @@ struct osi_core_ptp_tsc_data { nveu32_t tsc_low_bits; }; - /** * @brief OSI VM IRQ data */ @@ -1223,6 +1020,40 @@ struct osi_macsec_irq_stats { }; #endif /* MACSEC_SUPPORT */ +/** + * @brief FRP Instruction configuration structure + */ +struct osi_core_frp_data { + /** Entry Match Data */ + nveu32_t match_data; + /** Entry Match Enable mask */ + nveu32_t match_en; + /** Entry Accept frame flag */ + nveu8_t accept_frame; + /** Entry Reject Frame flag */ + nveu8_t reject_frame; + /** Entry Inverse match flag */ + nveu8_t inverse_match; + /** Entry Next Instruction Control match flag */ + nveu8_t next_ins_ctrl; + /** Entry Frame offset in the packet data */ + nveu8_t frame_offset; + /** Entry OK Index - Next Instruction */ + nveu8_t ok_index; + /** Entry DMA Channel selection (1-bit for each channel) */ + nveu32_t dma_chsel; +}; + +/** + * @brief FRP Instruction table entry configuration structure + */ +struct osi_core_frp_entry { + /** FRP ID */ + nve32_t frp_id; + /** FRP Entry data structure */ + struct osi_core_frp_data data; +}; + /** * @brief Core time stamp data strcuture */ @@ -1269,22 +1100,22 @@ struct osi_ioctl { struct osi_l3_l4_filter l3l4_filter; /* HW feature structure */ struct osi_hw_features hw_feat; -#ifndef OSI_STRIPPED_LIB - /* AVB structure */ + /** AVB structure */ struct osi_core_avb_algorithm avb; - /* VLAN filter structure */ +#ifndef OSI_STRIPPED_LIB + /** VLAN filter structure */ struct osi_vlan_filter vlan_filter; - /* PTP offload config structure*/ + /** PTP offload config structure*/ struct osi_pto_config pto_config; - /* FRP structure */ - struct osi_core_frp_cmd frp_cmd; - /* EST structure */ - struct osi_est_config est; - /* FRP structure */ - struct osi_fpe_config fpe; - /* RXQ route structure */ + /** RXQ route structure */ struct osi_rxq_route rxq_route; #endif /* !OSI_STRIPPED_LIB */ + /** FRP structure */ + struct osi_core_frp_cmd frp_cmd; + /** EST structure */ + struct osi_est_config est; + /** FRP structure */ + struct osi_fpe_config fpe; /** PTP configuration settings */ struct osi_ptp_config ptp_config; /** TX Timestamp structure */ @@ -1451,19 +1282,29 @@ struct osi_core_priv_data { struct osi_xtra_stat_counters xstats; /** Memory mapped base address of HV window */ void *hv_base; - /** Residual queue valid with FPE support */ - nveu32_t residual_queue; /** Functional safety config to do periodic read-verify of * certain safety critical registers */ void *safety_config; /** Backup config to save/restore registers during suspend/resume */ struct core_backup backup_config; + /** csr clock is to program LPI 1 us tick timer register. + * Value stored in MHz + */ + nveu32_t csr_clk_speed; + nveu64_t vf_bitmap; + /** Array to maintain VLAN filters */ + nveu16_t vid[VLAN_NUM_VID]; + /** Count of number of VLAN filters in vid array */ + nveu16_t vlan_filter_cnt; + /** RSS core structure */ + struct osi_core_rss rss; +#endif + /** Residual queue valid with FPE support */ + nveu32_t residual_queue; /** FRP Instruction Table */ struct osi_core_frp_entry frp_table[OSI_FRP_MAX_ENTRY]; /** Number of valid Entries in the FRP Instruction Table */ nveu32_t frp_cnt; - /** RSS core structure */ - struct osi_core_rss rss; /* Switch to Software Owned List Complete. * 1 - Successful and User configured GCL in placed */ @@ -1474,16 +1315,6 @@ struct osi_core_priv_data { nveu32_t fpe_ready; /** TSN stats counters */ struct osi_tsn_stats tsn_stats; - /** csr clock is to program LPI 1 us tick timer register. - * Value stored in MHz - */ - nveu32_t csr_clk_speed; - nveu64_t vf_bitmap; - /** Array to maintaion VLAN filters */ - nveu16_t vid[VLAN_NUM_VID]; - /** Count of number of VLAN filters in vid array */ - nveu16_t vlan_filter_cnt; -#endif /** eqos pad control structure */ struct core_padctrl padctrl; /** MDC clock rate */ diff --git a/osi/common/common.h b/osi/common/common.h index 3d37f14..5944292 100644 --- a/osi/common/common.h +++ b/osi/common/common.h @@ -49,7 +49,6 @@ */ #define MAX_MAC_IP_TYPES 2U -#ifndef OSI_STRIPPED_LIB /** * @brief osi_readl_poll_timeout - Periodically poll an address until * a condition is met or a timeout occurs @@ -67,9 +66,9 @@ */ #define osi_readl_poll_timeout(addr, fn, val, cond, delay_us, retry) \ ({ \ - unsigned int count = 0; \ + nveu32_t count = 0; \ while (count++ < retry) { \ - val = osi_readl((unsigned char *)addr); \ + val = osi_readl((nveu8_t *)addr); \ if ((cond)) { \ break; \ } \ @@ -77,7 +76,6 @@ } \ (cond) ? 0 : -1; \ }) -#endif /* !OSI_STRIPPED_LIB */ struct osi_core_priv_data; diff --git a/osi/core/core_common.c b/osi/core/core_common.c index 4d24ec5..c353206 100644 --- a/osi/core/core_common.c +++ b/osi/core/core_common.c @@ -462,7 +462,7 @@ nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "ptp_tsc: older IP\n", 0ULL); ret = -1; - goto exit; + goto done; } #endif /* !OSI_STRIPPED_LIB */ @@ -471,7 +471,7 @@ nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core, ret = poll_check(osi_core, ((nveu8_t *)addr + WRAP_SYNC_TSC_PTP_CAPTURE), OSI_ENABLE, &tsc_ptp); if (ret == -1) { - goto exit; + goto done; } data->tsc_low_bits = osi_readla(osi_core, (nveu8_t *)osi_core->base + @@ -482,7 +482,7 @@ nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core, WRAP_PTP_CAPTURE_LOW); data->ptp_high_bits = osi_readla(osi_core, (nveu8_t *)osi_core->base + WRAP_PTP_CAPTURE_HIGH); -exit: +done: return ret; } @@ -582,7 +582,6 @@ fail: return ret; } -#ifndef OSI_STRIPPED_LIB /** * @brief hw_est_read - indirect read the GCL to Software own list * (SWOL) @@ -611,8 +610,7 @@ static inline nve32_t hw_est_read(struct osi_core_priv_data *osi_core, nve32_t ret; const nveu32_t MTL_EST_GCL_CONTROL[MAX_MAC_IP_TYPES] = { EQOS_MTL_EST_GCL_CONTROL, MGBE_MTL_EST_GCL_CONTROL}; - const nveu32_t MTL_EST_DATA[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_DATA, - MGBE_MTL_EST_DATA}; + const nveu32_t MTL_EST_DATA[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_DATA, MGBE_MTL_EST_DATA}; *data = 0U; val &= ~MTL_EST_ADDR_MASK; @@ -659,11 +657,11 @@ err: * @retval 0 on success * @retval -1 on failure. */ -nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, - struct osi_est_config *const est, - const nveu32_t *btr, nveu32_t mac) +static nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, + struct osi_est_config *const est, + const nveu32_t *btr, nveu32_t mac) { - const struct core_local *l_core = (struct core_local *)osi_core; + const struct core_local *l_core = (struct core_local *)(void *)osi_core; const nveu32_t PTP_CYCLE_8[MAX_MAC_IP_TYPES] = {EQOS_8PTP_CYCLE, MGBE_8PTP_CYCLE}; const nveu32_t MTL_EST_CONTROL[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL, @@ -687,7 +685,7 @@ nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, nveu32_t bunk = 0U; nveu32_t est_status; nveu64_t old_btr, old_ctr; - nve32_t ret; + nve32_t ret = 0; nveu32_t val = 0U; nveu64_t rem = 0U; const struct est_read hw_read_arr[4] = { @@ -700,7 +698,8 @@ nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "input argument more than GCL depth\n", (nveul64_t)est->llr); - return -1; + ret = -1; + goto done; } ctr = ((nveu64_t)est->ctr[1] * OSI_NSEC_PER_SEC) + est->ctr[0]; @@ -713,12 +712,13 @@ nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, ((ctr - sum_tin) >= PTP_CYCLE_8[mac])) { continue; } else if (((ctr - sum_ti) != 0U) && - ((ctr - sum_ti) < PTP_CYCLE_8[mac])) { + ((ctr - sum_ti) < PTP_CYCLE_8[mac])) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "CTR issue due to trancate\n", (nveul64_t)i); - return -1; + ret = -1; + goto done; } else { //do nothing } @@ -729,16 +729,17 @@ nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "validation of GCL entry failed\n", (nveul64_t)i); - return -1; + ret = -1; + goto done; } /* Check for BTR in case of new ETS while current GCL enabled */ - val = osi_readla(osi_core, - (nveu8_t *)osi_core->base + + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + MTL_EST_CONTROL[mac]); if ((val & MTL_EST_CONTROL_EEST) != MTL_EST_CONTROL_EEST) { - return 0; + ret = 0; + goto done; } /* Read EST_STATUS for bunk */ @@ -758,7 +759,7 @@ nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Reading failed for index\n", (nveul64_t)i); - return ret; + goto done; } } @@ -769,19 +770,630 @@ nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, if ((rem != OSI_NONE) && (rem < PTP_CYCLE_8[mac])) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "invalid BTR", (nveul64_t)rem); - return -1; + ret = -1; + goto done; } } else if (btr_new > old_btr) { rem = (btr_new - old_btr) % old_ctr; if ((rem != OSI_NONE) && (rem < PTP_CYCLE_8[mac])) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "invalid BTR", (nveul64_t)rem); - return -1; + ret = -1; + goto done; } } else { // Nothing to do } - return 0; +done: + return ret; +} + +/** + * @brief hw_est_write - indirect write the GCL to Software own list + * (SWOL) + * + * @param[in] base: MAC base IOVA address. + * @param[in] addr_val: Address offset for indirect write. + * @param[in] data: Data to be written at offset. + * @param[in] gcla: Gate Control List Address, 0 for ETS register. + * 1 for GCL memory. + * + * @note MAC should be init and started. see osi_start_mac() + * + * @retval 0 on success + * @retval -1 on failure. + */ +static nve32_t hw_est_write(struct osi_core_priv_data *osi_core, + nveu32_t addr_val, nveu32_t data, + nveu32_t gcla) +{ + nve32_t retry = 1000; + nveu32_t val = 0x0; + nve32_t ret = 0; + const nveu32_t MTL_EST_DATA[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_DATA, + MGBE_MTL_EST_DATA}; + const nveu32_t MTL_EST_GCL_CONTROL[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_GCL_CONTROL, + MGBE_MTL_EST_GCL_CONTROL}; + + osi_writela(osi_core, data, (nveu8_t *)osi_core->base + + MTL_EST_DATA[osi_core->mac]); + + val &= ~MTL_EST_ADDR_MASK; + val |= (gcla == 1U) ? 0x0U : MTL_EST_GCRR; + val |= MTL_EST_SRWO; + val |= addr_val; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MTL_EST_GCL_CONTROL[osi_core->mac]); + + while (--retry > 0) { + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_EST_GCL_CONTROL[osi_core->mac]); + if ((val & MTL_EST_SRWO) == MTL_EST_SRWO) { + osi_core->osd_ops.udelay(OSI_DELAY_1US); + continue; + } + + break; + } + + if (((val & MTL_EST_ERR0) == MTL_EST_ERR0) || + (retry <= 0)) { + ret = -1; + } + + return ret; +} + +/** + * @brief hw_config_est - Read Setting for GCL from input and update + * registers. + * + * Algorithm: + * 1) Write TER, LLR and EST control register + * 2) Update GCL to sw own GCL (MTL_EST_Status bit SWOL will tell which is + * owned by SW) and store which GCL is in use currently in sw. + * 3) TODO set DBGB and DBGM for debugging + * 4) EST_data and GCRR to 1, update entry sno in ADDR and put data at + * est_gcl_data enable GCL MTL_EST_SSWL and wait for self clear or use + * SWLC in MTL_EST_Status. Please note new GCL will be pushed for each entry. + * 5) Configure btr. Update btr based on current time (current time + * should be updated based on PTP by this time) + * + * @param[in] osi_core: OSI core private data structure. + * @param[in] est: EST configuration input argument. + * + * @note MAC should be init and started. see osi_start_mac() + * + * @retval 0 on success + * @retval -1 on failure. + */ +nve32_t hw_config_est(struct osi_core_priv_data *const osi_core, + struct osi_est_config *const est) +{ + nveu32_t btr[2] = {0}; + nveu32_t val = 0x0; + void *base = osi_core->base; + nveu32_t i; + nve32_t ret = 0; + nveu32_t addr = 0x0; + const nveu32_t MTL_EST_CONTROL[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL, + MGBE_MTL_EST_CONTROL}; + const nveu32_t MTL_EST_BTR_LOW[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_BTR_LOW, + MGBE_MTL_EST_BTR_LOW}; + const nveu32_t MTL_EST_BTR_HIGH[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_BTR_HIGH, + MGBE_MTL_EST_BTR_HIGH}; + const nveu32_t MTL_EST_CTR_LOW[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CTR_LOW, + MGBE_MTL_EST_CTR_LOW}; + const nveu32_t MTL_EST_CTR_HIGH[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CTR_HIGH, + MGBE_MTL_EST_CTR_HIGH}; + const nveu32_t MTL_EST_TER[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_TER, + MGBE_MTL_EST_TER}; + const nveu32_t MTL_EST_LLR[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_LLR, + MGBE_MTL_EST_LLR}; + + if ((osi_core->hw_feature != OSI_NULL) && + (osi_core->hw_feature->est_sel == OSI_DISABLE)) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "EST not supported in HW\n", 0ULL); + ret = -1; + goto done; + } + + if (est->en_dis == OSI_DISABLE) { + val = osi_readla(osi_core, (nveu8_t *)base + + MTL_EST_CONTROL[osi_core->mac]); + val &= ~MTL_EST_EEST; + osi_writela(osi_core, val, (nveu8_t *)base + + MTL_EST_CONTROL[osi_core->mac]); + + ret = 0; + } else { + btr[0] = est->btr[0]; + btr[1] = est->btr[1]; + if ((btr[0] == 0U) && (btr[1] == 0U)) { + common_get_systime_from_mac(osi_core->base, + osi_core->mac, + &btr[1], &btr[0]); + } + + if (gcl_validate(osi_core, est, btr, osi_core->mac) < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL validation failed\n", 0LL); + ret = -1; + goto done; + } + + ret = hw_est_write(osi_core, MTL_EST_CTR_LOW[osi_core->mac], est->ctr[0], 0); + if (ret < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL CTR[0] failed\n", 0LL); + goto done; + } + /* check for est->ctr[i] not more than FF, TODO as per hw config + * parameter we can have max 0x3 as this value in sec */ + est->ctr[1] &= MTL_EST_CTR_HIGH_MAX; + ret = hw_est_write(osi_core, MTL_EST_CTR_HIGH[osi_core->mac], est->ctr[1], 0); + if (ret < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL CTR[1] failed\n", 0LL); + goto done; + } + + ret = hw_est_write(osi_core, MTL_EST_TER[osi_core->mac], est->ter, 0); + if (ret < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL TER failed\n", 0LL); + goto done; + } + + ret = hw_est_write(osi_core, MTL_EST_LLR[osi_core->mac], est->llr, 0); + if (ret < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL LLR failed\n", 0LL); + goto done; + } + + /* Write GCL table */ + for (i = 0U; i < est->llr; i++) { + addr = i; + addr = addr << MTL_EST_ADDR_SHIFT; + addr &= MTL_EST_ADDR_MASK; + ret = hw_est_write(osi_core, addr, est->gcl[i], 1); + if (ret < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL enties write failed\n", + (nveul64_t)i); + goto done; + } + } + + /* Write parameters */ + ret = hw_est_write(osi_core, MTL_EST_BTR_LOW[osi_core->mac], + btr[0] + est->btr_offset[0], OSI_DISABLE); + if (ret < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL BTR[0] failed\n", + (btr[0] + est->btr_offset[0])); + goto done; + } + + ret = hw_est_write(osi_core, MTL_EST_BTR_HIGH[osi_core->mac], + btr[1] + est->btr_offset[1], OSI_DISABLE); + if (ret < 0) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "GCL BTR[1] failed\n", + (btr[1] + est->btr_offset[1])); + goto done; + } + + val = osi_readla(osi_core, (nveu8_t *)base + + MTL_EST_CONTROL[osi_core->mac]); + /* Store table */ + val |= MTL_EST_SSWL; + val |= MTL_EST_EEST; + val |= MTL_EST_QHLBF; + osi_writela(osi_core, val, (nveu8_t *)base + + MTL_EST_CONTROL[osi_core->mac]); + } +done: + return ret; +} + +/** + * @brief hw_config_fpe - Read Setting for preemption and express for TC + * and update registers. + * + * Algorithm: + * 1) Check for TC enable and TC has masked for setting to preemptable. + * 2) update FPE control status register + * + * @param[in] osi_core: OSI core private data structure. + * @param[in] fpe: FPE configuration input argument. + * + * @note MAC should be init and started. see osi_start_mac() + * + * @retval 0 on success + * @retval -1 on failure. + */ +nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core, + struct osi_fpe_config *const fpe) +{ + nveu32_t i = 0U; + nveu32_t val = 0U; + nveu32_t temp = 0U, temp1 = 0U; + nveu32_t temp_shift = 0U; + nve32_t ret = 0; + const nveu32_t MTL_FPE_CTS[MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_CTS, + MGBE_MTL_FPE_CTS}; + const nveu32_t MAC_FPE_CTS[MAX_MAC_IP_TYPES] = {EQOS_MAC_FPE_CTS, + MGBE_MAC_FPE_CTS}; + const nveu32_t max_number_queue[MAX_MAC_IP_TYPES] = {OSI_EQOS_MAX_NUM_QUEUES, + OSI_MGBE_MAX_NUM_QUEUES}; + const nveu32_t MAC_RQC1R[MAX_MAC_IP_TYPES] = {EQOS_MAC_RQC1R, + MGBE_MAC_RQC1R}; + const nveu32_t MAC_RQC1R_RQ[MAX_MAC_IP_TYPES] = {EQOS_MAC_RQC1R_FPRQ, + MGBE_MAC_RQC1R_RQ}; + const nveu32_t MAC_RQC1R_RQ_SHIFT[MAX_MAC_IP_TYPES] = {EQOS_MAC_RQC1R_FPRQ_SHIFT, + MGBE_MAC_RQC1R_RQ_SHIFT}; + const nveu32_t MTL_FPE_ADV[MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_ADV, + MGBE_MTL_FPE_ADV}; + + if ((osi_core->hw_feature != OSI_NULL) && + (osi_core->hw_feature->fpe_sel == OSI_DISABLE)) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "FPE not supported in HW\n", 0ULL); + ret = -1; + goto error; + } + + if (osi_core->mac == OSI_MAC_HW_MGBE) { +#ifdef MACSEC_SUPPORT + osi_lock_irq_enabled(&osi_core->macsec_fpe_lock); + /* MACSEC and FPE cannot coexist on MGBE refer bug 3484034 */ + if (osi_core->is_macsec_enabled == OSI_ENABLE) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "FPE and MACSEC cannot co-exist\n", 0ULL); + ret = -1; + goto done; + } +#endif /* MACSEC_SUPPORT */ + } + + osi_core->fpe_ready = OSI_DISABLE; + + if (((fpe->tx_queue_preemption_enable << MTL_FPE_CTS_PEC_SHIFT) & + MTL_FPE_CTS_PEC) == OSI_DISABLE) { + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_FPE_CTS[osi_core->mac]); + val &= ~MTL_FPE_CTS_PEC; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MTL_FPE_CTS[osi_core->mac]); + + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MAC_FPE_CTS[osi_core->mac]); + val &= ~MAC_FPE_CTS_EFPE; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MAC_FPE_CTS[osi_core->mac]); + + if (osi_core->mac == OSI_MAC_HW_MGBE) { +#ifdef MACSEC_SUPPORT + osi_core->is_fpe_enabled = OSI_DISABLE; +#endif /* MACSEC_SUPPORT */ + } + ret = 0; + } else { + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_FPE_CTS[osi_core->mac]); + val &= ~MTL_FPE_CTS_PEC; + for (i = 0U; i < OSI_MAX_TC_NUM; i++) { + /* max 8 bit for this structure fot TC/TXQ. Set the TC for express or + * preemption. Default is express for a TC. DWCXG_NUM_TC = 8 */ + temp = OSI_BIT(i); + if ((fpe->tx_queue_preemption_enable & temp) == temp) { + temp_shift = i; + temp_shift += MTL_FPE_CTS_PEC_SHIFT; + /* set queue for preemtable */ + if (temp_shift < MTL_FPE_CTS_PEC_MAX_SHIFT) { + temp1 = OSI_ENABLE; + temp1 = temp1 << temp_shift; + val |= temp1; + } else { + /* Do nothing */ + } + } + } + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MTL_FPE_CTS[osi_core->mac]); + + if ((fpe->rq == 0x0U) || (fpe->rq >= max_number_queue[osi_core->mac])) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "FPE init failed due to wrong RQ\n", fpe->rq); + ret = -1; + goto done; + } + + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MAC_RQC1R[osi_core->mac]); + val &= ~MAC_RQC1R_RQ[osi_core->mac]; + temp = fpe->rq; + temp = temp << MAC_RQC1R_RQ_SHIFT[osi_core->mac]; + temp = (temp & MAC_RQC1R_RQ[osi_core->mac]); + val |= temp; + osi_core->residual_queue = fpe->rq; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MAC_RQC1R[osi_core->mac]); + + if (osi_core->mac == OSI_MAC_HW_MGBE) { + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MGBE_MAC_RQC4R); + val &= ~MGBE_MAC_RQC4R_PMCBCQ; + temp = fpe->rq; + temp = temp << MGBE_MAC_RQC4R_PMCBCQ_SHIFT; + temp = (temp & MGBE_MAC_RQC4R_PMCBCQ); + val |= temp; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MGBE_MAC_RQC4R); + } + /* initiate SVER for SMD-V and SMD-R */ + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_FPE_CTS[osi_core->mac]); + val |= MAC_FPE_CTS_SVER; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MAC_FPE_CTS[osi_core->mac]); + + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_FPE_ADV[osi_core->mac]); + val &= ~MTL_FPE_ADV_HADV_MASK; + //(minimum_fragment_size +IPG/EIPG + Preamble) *.8 ~98ns for10G + val |= MTL_FPE_ADV_HADV_VAL; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MTL_FPE_ADV[osi_core->mac]); + + if (osi_core->mac == OSI_MAC_HW_MGBE) { +#ifdef MACSEC_SUPPORT + osi_core->is_fpe_enabled = OSI_ENABLE; +#endif /* MACSEC_SUPPORT */ + } + } +done: + + if (osi_core->mac == OSI_MAC_HW_MGBE) { +#ifdef MACSEC_SUPPORT + osi_unlock_irq_enabled(&osi_core->macsec_fpe_lock); +#endif /* MACSEC_SUPPORT */ + } + +error: + return ret; +} + +/** + * @brief enable_mtl_interrupts - Enable MTL interrupts + * + * Algorithm: enable MTL interrupts for EST + * + * @param[in] osi_core: OSI core private data structure. + * + * @note MAC should be init and started. see osi_start_mac() + */ +static inline void enable_mtl_interrupts(struct osi_core_priv_data *osi_core) +{ + nveu32_t mtl_est_ir = OSI_DISABLE; + const nveu32_t MTL_EST_ITRE[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_ITRE, + MGBE_MTL_EST_ITRE}; + + mtl_est_ir = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_EST_ITRE[osi_core->mac]); + /* enable only MTL interrupt realted to + * Constant Gate Control Error + * Head-Of-Line Blocking due to Scheduling + * Head-Of-Line Blocking due to Frame Size + * BTR Error + * Switch to S/W owned list Complete + */ + mtl_est_ir |= (MTL_EST_ITRE_CGCE | MTL_EST_ITRE_IEHS | + MTL_EST_ITRE_IEHF | MTL_EST_ITRE_IEBE | + MTL_EST_ITRE_IECC); + osi_writela(osi_core, mtl_est_ir, (nveu8_t *)osi_core->base + + MTL_EST_ITRE[osi_core->mac]); +} + +/** + * @brief enable_fpe_interrupts - Enable MTL interrupts + * + * Algorithm: enable FPE interrupts + * + * @param[in] osi_core: OSI core private data structure. + * + * @note MAC should be init and started. see osi_start_mac() + */ +static inline void enable_fpe_interrupts(struct osi_core_priv_data *osi_core) +{ + nveu32_t value = OSI_DISABLE; + const nveu32_t MAC_IER[MAX_MAC_IP_TYPES] = {EQOS_MAC_IMR, + MGBE_MAC_IER}; + const nveu32_t IMR_FPEIE[MAX_MAC_IP_TYPES] = {EQOS_IMR_FPEIE, + MGBE_IMR_FPEIE}; + + /* Read MAC IER Register and enable Frame Preemption Interrupt + * Enable */ + value = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MAC_IER[osi_core->mac]); + value |= IMR_FPEIE[osi_core->mac]; + osi_writela(osi_core, value, (nveu8_t *)osi_core->base + + MAC_IER[osi_core->mac]); +} + +/** + * @brief save_gcl_params - save GCL configs in local core structure + * + * @param[in] osi_core: OSI core private data structure. + * + * @note MAC should be init and started. see osi_start_mac() + */ +static inline void save_gcl_params(struct osi_core_priv_data *osi_core) +{ + struct core_local *l_core = (struct core_local *)(void *)osi_core; + const nveu32_t gcl_widhth[4] = {0, OSI_MAX_24BITS, OSI_MAX_28BITS, + OSI_MAX_32BITS}; + const nveu32_t gcl_ti_mask[4] = {0, OSI_MASK_16BITS, OSI_MASK_20BITS, + OSI_MASK_24BITS}; + const nveu32_t gcl_depthth[6] = {0, OSI_GCL_SIZE_64, OSI_GCL_SIZE_128, + OSI_GCL_SIZE_256, OSI_GCL_SIZE_512, + OSI_GCL_SIZE_1024}; + + if ((osi_core->hw_feature->gcl_width == 0U) || + (osi_core->hw_feature->gcl_width > 3U)) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "Wrong HW feature GCL width\n", + (nveul64_t)osi_core->hw_feature->gcl_width); + } else { + l_core->gcl_width_val = + gcl_widhth[osi_core->hw_feature->gcl_width]; + l_core->ti_mask = gcl_ti_mask[osi_core->hw_feature->gcl_width]; + } + + if ((osi_core->hw_feature->gcl_depth == 0U) || + (osi_core->hw_feature->gcl_depth > 5U)) { + /* Do Nothing */ + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "Wrong HW feature GCL depth\n", + (nveul64_t)osi_core->hw_feature->gcl_depth); + } else { + l_core->gcl_dep = gcl_depthth[osi_core->hw_feature->gcl_depth]; + } +} + +/** + * @brief hw_tsn_init - initialize TSN feature + * + * Algorithm: + * 1) If hardware support EST, + * a) Set default EST configuration + * b) Set enable interrupts + * 2) If hardware supports FPE + * a) Set default FPE configuration + * b) enable interrupts + * + * @param[in] osi_core: OSI core private data structure. + * @param[in] est_sel: EST HW support present or not + * @param[in] fpe_sel: FPE HW support present or not + * + * @note MAC should be init and started. see osi_start_mac() + */ +void hw_tsn_init(struct osi_core_priv_data *osi_core, + nveu32_t est_sel, nveu32_t fpe_sel) +{ + nveu32_t val = 0x0; + nveu32_t temp = 0U; + const nveu32_t MTL_EST_CONTROL[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL, + MGBE_MTL_EST_CONTROL}; + const nveu32_t MTL_EST_CONTROL_PTOV[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL_PTOV, + MGBE_MTL_EST_CONTROL_PTOV}; + const nveu32_t MTL_EST_PTOV_RECOMMEND[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_PTOV_RECOMMEND, + MGBE_MTL_EST_PTOV_RECOMMEND}; + const nveu32_t MTL_EST_CONTROL_PTOV_SHIFT[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL_PTOV_SHIFT, + MGBE_MTL_EST_CONTROL_PTOV_SHIFT}; + const nveu32_t MTL_EST_CONTROL_CTOV[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL_CTOV, + MGBE_MTL_EST_CONTROL_CTOV}; + const nveu32_t MTL_EST_CTOV_RECOMMEND[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CTOV_RECOMMEND, + MGBE_MTL_EST_CTOV_RECOMMEND}; + const nveu32_t MTL_EST_CONTROL_CTOV_SHIFT[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL_CTOV_SHIFT, + MGBE_MTL_EST_CONTROL_CTOV_SHIFT}; + const nveu32_t MTL_EST_CONTROL_LCSE[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL_LCSE, + MGBE_MTL_EST_CONTROL_LCSE}; + const nveu32_t MTL_EST_CONTROL_LCSE_VAL[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL_LCSE_VAL, + MGBE_MTL_EST_CONTROL_LCSE_VAL}; + const nveu32_t MTL_EST_CONTROL_DDBF[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_CONTROL_DDBF, + MGBE_MTL_EST_CONTROL_DDBF}; + const nveu32_t MTL_EST_OVERHEAD[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_OVERHEAD, + MGBE_MTL_EST_OVERHEAD}; + const nveu32_t MTL_EST_OVERHEAD_OVHD[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_OVERHEAD_OVHD, + MGBE_MTL_EST_OVERHEAD_OVHD}; + const nveu32_t MTL_EST_OVERHEAD_RECOMMEND[MAX_MAC_IP_TYPES] = {EQOS_MTL_EST_OVERHEAD_RECOMMEND, + MGBE_MTL_EST_OVERHEAD_RECOMMEND}; + const nveu32_t MAC_RQC1R[MAX_MAC_IP_TYPES] = {EQOS_MAC_RQC1R, + MGBE_MAC_RQC1R}; + const nveu32_t MAC_RQC1R_RQ[MAX_MAC_IP_TYPES] = {EQOS_MAC_RQC1R_FPRQ, + MGBE_MAC_RQC1R_RQ}; + const nveu32_t MAC_RQC1R_RQ_SHIFT[MAX_MAC_IP_TYPES] = {EQOS_MAC_RQC1R_FPRQ_SHIFT, + MGBE_MAC_RQC1R_RQ_SHIFT}; + + if (est_sel == OSI_ENABLE) { + save_gcl_params(osi_core); + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_EST_CONTROL[osi_core->mac]); + + /* + * PTOV PTP clock period * 6 + * dual-port RAM based asynchronous FIFO controllers or + * Single-port RAM based synchronous FIFO controllers + * CTOV 96 x Tx clock period + * : + * : + * set other default value + */ + val &= ~MTL_EST_CONTROL_PTOV[osi_core->mac]; + temp = MTL_EST_PTOV_RECOMMEND[osi_core->mac]; + temp = temp << MTL_EST_CONTROL_PTOV_SHIFT[osi_core->mac]; + val |= temp; + + val &= ~MTL_EST_CONTROL_CTOV[osi_core->mac]; + temp = MTL_EST_CTOV_RECOMMEND[osi_core->mac]; + temp = temp << MTL_EST_CONTROL_CTOV_SHIFT[osi_core->mac]; + val |= temp; + + /*Loop Count to report Scheduling Error*/ + val &= ~MTL_EST_CONTROL_LCSE[osi_core->mac]; + val |= MTL_EST_CONTROL_LCSE_VAL[osi_core->mac]; + + if (osi_core->mac == OSI_MAC_HW_EQOS) { + val &= ~EQOS_MTL_EST_CONTROL_DFBS; + } + val &= ~MTL_EST_CONTROL_DDBF[osi_core->mac]; + val |= MTL_EST_CONTROL_DDBF[osi_core->mac]; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MTL_EST_CONTROL[osi_core->mac]); + + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MTL_EST_OVERHEAD[osi_core->mac]); + val &= ~MTL_EST_OVERHEAD_OVHD[osi_core->mac]; + /* As per hardware programming info */ + val |= MTL_EST_OVERHEAD_RECOMMEND[osi_core->mac]; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MTL_EST_OVERHEAD[osi_core->mac]); + + enable_mtl_interrupts(osi_core); + } + + if (fpe_sel == OSI_ENABLE) { + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MAC_RQC1R[osi_core->mac]); + val &= ~MAC_RQC1R_RQ[osi_core->mac]; + temp = osi_core->residual_queue; + temp = temp << MAC_RQC1R_RQ_SHIFT[osi_core->mac]; + temp = (temp & MAC_RQC1R_RQ[osi_core->mac]); + val |= temp; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MAC_RQC1R[osi_core->mac]); + + if (osi_core->mac == OSI_MAC_HW_MGBE) { + val = osi_readla(osi_core, (nveu8_t *)osi_core->base + + MGBE_MAC_RQC4R); + val &= ~MGBE_MAC_RQC4R_PMCBCQ; + temp = osi_core->residual_queue; + temp = temp << MGBE_MAC_RQC4R_PMCBCQ_SHIFT; + temp = (temp & MGBE_MAC_RQC4R_PMCBCQ); + val |= temp; + osi_writela(osi_core, val, (nveu8_t *)osi_core->base + + MGBE_MAC_RQC4R); + } + + enable_fpe_interrupts(osi_core); + } + + /* CBS setting for TC or TXQ for default configuration + user application should use IOCTL to set CBS as per requirement + */ } -#endif /* !OSI_STRIPPED_LIB */ diff --git a/osi/core/core_common.h b/osi/core/core_common.h index 8d1f6ea..cd281d9 100644 --- a/osi/core/core_common.h +++ b/osi/core/core_common.h @@ -24,9 +24,8 @@ #define INCLUDED_CORE_COMMON_H #include "core_local.h" - -#ifndef OSI_STRIPPED_LIB #define MAC_TCR_TSCTRLSSR OSI_BIT(9) +#define MTL_EST_ADDR_SHIFT 8 #define MTL_EST_ADDR_MASK (OSI_BIT(8) | OSI_BIT(9) | \ OSI_BIT(10) | OSI_BIT(11) | \ OSI_BIT(12) | OSI_BIT(13) | \ @@ -42,8 +41,28 @@ #define MTL_EST_CONTROL_EEST OSI_BIT(0) #define MTL_EST_STATUS_SWOL OSI_BIT(7) #define MAC_TCR_TSCFUPDT OSI_BIT(1) -#endif /* !OSI_STRIPPED_LIB */ - +/* EST control OSI_BIT map */ +#define MTL_EST_EEST OSI_BIT(0) +#define MTL_EST_SSWL OSI_BIT(1) +#define MTL_EST_QHLBF OSI_BIT(3) +#define MTL_EST_CTR_HIGH_MAX 0xFFU +#define MTL_EST_ITRE_CGCE OSI_BIT(4) +#define MTL_EST_ITRE_IEHS OSI_BIT(3) +#define MTL_EST_ITRE_IEHF OSI_BIT(2) +#define MTL_EST_ITRE_IEBE OSI_BIT(1) +#define MTL_EST_ITRE_IECC OSI_BIT(0) +/* MTL_FPE_CTRL_STS */ +#define MTL_FPE_CTS_PEC (OSI_BIT(8) | OSI_BIT(9) | \ + OSI_BIT(10) | OSI_BIT(11) | \ + OSI_BIT(12) | OSI_BIT(13) | \ + OSI_BIT(14) | OSI_BIT(15)) +#define MTL_FPE_CTS_PEC_SHIFT 8U +#define MTL_FPE_CTS_PEC_MAX_SHIFT 16U +#define MAC_FPE_CTS_EFPE OSI_BIT(0) +#define MAC_FPE_CTS_SVER OSI_BIT(1) +/* MTL FPE adv registers */ +#define MTL_FPE_ADV_HADV_MASK (0xFFFFU) +#define MTL_FPE_ADV_HADV_VAL 100U #define DMA_MODE_SWR OSI_BIT(0) #define MTL_QTOMR_FTQ OSI_BIT(0) #define MTL_RXQ_OP_MODE_FEP OSI_BIT(4) @@ -74,7 +93,6 @@ #define MAC_PKT_FILTER_REG 0x0008 -#ifndef OSI_STRIPPED_LIB /** * @addtogroup typedef related info * @@ -83,18 +101,14 @@ */ struct est_read { - /* variable pointer */ + /** variable pointer */ nveu32_t *var; - /* memory register/address offset */ + /** memory register/address offset */ nveu32_t addr; }; /** @} */ -nve32_t gcl_validate(struct osi_core_priv_data *const osi_core, - struct osi_est_config *const est, - const nveu32_t *btr, nveu32_t mac); -#endif /* !OSI_STRIPPED_LIB */ nve32_t hw_poll_for_swr(struct osi_core_priv_data *const osi_core); void hw_start_mac(struct osi_core_priv_data *const osi_core); void hw_stop_mac(struct osi_core_priv_data *const osi_core); @@ -118,4 +132,10 @@ nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core, const struct osi_filter *filter); nve32_t hw_config_l3_l4_filter_enable(struct osi_core_priv_data *const osi_core, const nveu32_t filter_enb_dis); +nve32_t hw_config_est(struct osi_core_priv_data *const osi_core, + struct osi_est_config *const est); +nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core, + struct osi_fpe_config *const fpe); +void hw_tsn_init(struct osi_core_priv_data *osi_core, + nveu32_t est_sel, nveu32_t fpe_sel); #endif /* INCLUDED_CORE_COMMON_H */ diff --git a/osi/core/core_local.h b/osi/core/core_local.h index 249d3cb..e069a5d 100644 --- a/osi/core/core_local.h +++ b/osi/core/core_local.h @@ -47,29 +47,30 @@ * @brief Dynamic configuration helper macros. */ #define DYNAMIC_CFG_L3_L4 OSI_BIT(0) -#define DYNAMIC_CFG_L3_L4_IDX 0U +#define DYNAMIC_CFG_AVB OSI_BIT(2) #define DYNAMIC_CFG_L2 OSI_BIT(3) #define DYNAMIC_CFG_L2_IDX 3U #define DYNAMIC_CFG_RXCSUM OSI_BIT(4) -#define DYNAMIC_CFG_RXCSUM_IDX 4U #define DYNAMIC_CFG_PTP OSI_BIT(7) -#define DYNAMIC_CFG_PTP_IDX 7U - -#ifndef OSI_STRIPPED_LIB -#define DYNAMIC_CFG_FC OSI_BIT(1) -#define DYNAMIC_CFG_AVB OSI_BIT(2) -#define DYNAMIC_CFG_VLAN OSI_BIT(5) -#define DYNAMIC_CFG_EEE OSI_BIT(6) #define DYNAMIC_CFG_EST OSI_BIT(8) #define DYNAMIC_CFG_FPE OSI_BIT(9) +#ifndef OSI_STRIPPED_LIB +#define DYNAMIC_CFG_FC OSI_BIT(1) +#define DYNAMIC_CFG_VLAN OSI_BIT(5) +#define DYNAMIC_CFG_EEE OSI_BIT(6) #define DYNAMIC_CFG_FC_IDX 1U -#define DYNAMIC_CFG_AVB_IDX 2U #define DYNAMIC_CFG_VLAN_IDX 5U #define DYNAMIC_CFG_EEE_IDX 6U +#endif /* !OSI_STRIPPED_LIB */ + +#define DYNAMIC_CFG_L3_L4_IDX 0U +#define DYNAMIC_CFG_AVB_IDX 2U +#define DYNAMIC_CFG_L2_IDX 3U +#define DYNAMIC_CFG_RXCSUM_IDX 4U +#define DYNAMIC_CFG_PTP_IDX 7U #define DYNAMIC_CFG_EST_IDX 8U #define DYNAMIC_CFG_FPE_IDX 9U -#endif /* !OSI_STRIPPED_LIB */ #define OSI_SUSPENDED OSI_BIT(0) @@ -210,13 +211,6 @@ struct core_ops { /** Called periodically to read and validate safety critical * registers against last written value */ nve32_t (*validate_regs)(struct osi_core_priv_data *const osi_core); - /** Called to set av parameter */ - nve32_t (*set_avb_algorithm)(struct osi_core_priv_data *const osi_core, - const struct osi_core_avb_algorithm *const avb); - /** Called to get av parameter */ - nve32_t (*get_avb_algorithm)(struct osi_core_priv_data *const osi_core, - struct osi_core_avb_algorithm *const avb); - /** Called to configure VLAN filtering */ nve32_t (*config_vlan_filtering)( struct osi_core_priv_data *const osi_core, @@ -240,22 +234,6 @@ struct core_ops { nve32_t (*config_mac_loopback)( struct osi_core_priv_data *const osi_core, const nveu32_t lb_mode); - /** Called to update GCL config */ - nve32_t (*hw_config_est)(struct osi_core_priv_data *const osi_core, - struct osi_est_config *const est); - /** Called to update FPE config */ - nve32_t (*hw_config_fpe)(struct osi_core_priv_data *const osi_core, - struct osi_fpe_config *const fpe); - /** Called to configure FRP engine */ - nve32_t (*config_frp)(struct osi_core_priv_data *const osi_core, - const nveu32_t enabled); - /** Called to update FRP Instruction Table entry */ - nve32_t (*update_frp_entry)(struct osi_core_priv_data *const osi_core, - const nveu32_t pos, - struct osi_core_frp_data *const data); - /** Called to update FRP NVE and */ - nve32_t (*update_frp_nve)(struct osi_core_priv_data *const osi_core, - const nveu32_t nve); /** Called to configure RSS for MAC */ nve32_t (*config_rss)(struct osi_core_priv_data *osi_core); /** Called to configure the PTP RX packets Queue */ @@ -263,6 +241,22 @@ struct core_ops { const nveu32_t rxq_idx, const nveu32_t enable); #endif /* !OSI_STRIPPED_LIB */ + /** Called to set av parameter */ + nve32_t (*set_avb_algorithm)(struct osi_core_priv_data *const osi_core, + const struct osi_core_avb_algorithm *const avb); + /** Called to get av parameter */ + nve32_t (*get_avb_algorithm)(struct osi_core_priv_data *const osi_core, + struct osi_core_avb_algorithm *const avb); + /** Called to configure FRP engine */ + nve32_t (*config_frp)(struct osi_core_priv_data *const osi_core, + const nveu32_t enabled); + /** Called to update FRP Instruction Table entry */ + nve32_t (*update_frp_entry)(struct osi_core_priv_data *const osi_core, + const nveu32_t pos, + struct osi_core_frp_data *const data); + /** Called to update FRP NVE and */ + nve32_t (*update_frp_nve)(struct osi_core_priv_data *const osi_core, + const nveu32_t nve); #ifdef HSI_SUPPORT /** Interface function called to initialize HSI */ nve32_t (*core_hsi_configure)(struct osi_core_priv_data *const osi_core, @@ -332,7 +326,6 @@ struct l3_l4_filters { struct osi_l3_l4_filter l3l4_filter; }; -#ifndef OSI_STRIPPED_LIB /** * @brief AVB dynamic config storage structure */ @@ -342,7 +335,6 @@ struct core_avb { /** AVB data structure */ struct osi_core_avb_algorithm avb_info; }; -#endif /* !OSI_STRIPPED_LIB */ /** * @brief VLAN dynamic config storage structure @@ -371,10 +363,8 @@ struct dynamic_cfg { struct l3_l4_filters l3_l4[OSI_MGBE_MAX_L3_L4_FILTER]; /** flow control */ nveu32_t flow_ctrl; -#ifndef OSI_STRIPPED_LIB /** AVB */ struct core_avb avb[OSI_MGBE_MAX_NUM_QUEUES]; -#endif /* !OSI_STRIPPED_LIB */ /** RXCSUM */ nveu32_t rxcsum; /** VLAN arguments storage */ @@ -384,12 +374,10 @@ struct dynamic_cfg { nveu32_t tx_lpi_timer; /** PTP information storage */ nveu32_t ptp; -#ifndef OSI_STRIPPED_LIB /** EST information storage */ struct osi_est_config est; /** FPE information storage */ struct osi_fpe_config fpe; -#endif /* !OSI_STRIPPED_LIB */ /** L2 filter storage */ struct osi_filter l2_filter; /** L2 filter configuration */ diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c index 38a3bc4..df7a0c8 100644 --- a/osi/core/eqos_core.c +++ b/osi/core/eqos_core.c @@ -917,7 +917,6 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t qinx, } /** \endcond */ -#ifndef OSI_STRIPPED_LIB /** * @brief eqos_config_frp - Enable/Disale RX Flexible Receive Parser in HW * @@ -935,7 +934,7 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t qinx, * @retval -1 on failure. */ static nve32_t eqos_config_frp(struct osi_core_priv_data *const osi_core, - const nveu32_t enabled) + const nveu32_t enabled) { nveu8_t *base = osi_core->base; nveu32_t op_mode = 0U, val = 0U; @@ -945,7 +944,8 @@ static nve32_t eqos_config_frp(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid enable input\n", enabled); - return -1; + ret = -1; + goto done; } /* Disable RE */ @@ -1000,6 +1000,7 @@ frp_enable_re: val |= EQOS_MCR_RE; osi_writela(osi_core, val, base + EQOS_MAC_MCR); +done: return ret; } @@ -1017,17 +1018,18 @@ frp_enable_re: * @retval -1 on failure. */ static nve32_t eqos_update_frp_nve(struct osi_core_priv_data *const osi_core, - const nveu32_t nve) + const nveu32_t nve) { nveu32_t val; nveu8_t *base = osi_core->base; + nve32_t ret = -1; /* Validate the NVE value */ if (nve >= OSI_FRP_MAX_ENTRY) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid NVE value\n", nve); - return -1; + goto done; } /* Update NVE and NPE in MTL_RXP_Control_Status register */ @@ -1039,7 +1041,10 @@ static nve32_t eqos_update_frp_nve(struct osi_core_priv_data *const osi_core, val |= ((nve << EQOS_MTL_RXP_CS_NPE_SHIFT) & EQOS_MTL_RXP_CS_NPE); osi_writela(osi_core, val, base + EQOS_MTL_RXP_CS); - return 0; + ret = 0; + +done: + return ret; } /** @@ -1057,8 +1062,8 @@ static nve32_t eqos_update_frp_nve(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ static nve32_t eqos_frp_write(struct osi_core_priv_data *osi_core, - nveu32_t addr, - nveu32_t data) + nveu32_t addr, + nveu32_t data) { nve32_t ret = 0; nveu8_t *base = osi_core->base; @@ -1076,7 +1081,8 @@ static nve32_t eqos_frp_write(struct osi_core_priv_data *osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to write\n", val); - return -1; + ret = -1; + goto done; } /* Write data into MTL_RXP_Indirect_Acc_Data */ @@ -1105,9 +1111,10 @@ static nve32_t eqos_frp_write(struct osi_core_priv_data *osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to write\n", val); - return -1; + ret = -1; } +done: return ret; } @@ -1126,8 +1133,8 @@ static nve32_t eqos_frp_write(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t eqos_update_frp_entry(struct osi_core_priv_data *const osi_core, - const nveu32_t pos, - struct osi_core_frp_data *const data) + const nveu32_t pos, + struct osi_core_frp_data *const data) { nveu32_t val = 0U, tmp = 0U; nve32_t ret = -1; @@ -1137,7 +1144,8 @@ static nve32_t eqos_update_frp_entry(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid FRP table entry\n", pos); - return -1; + ret = -1; + goto done; } /** Write Match Data into IE0 **/ @@ -1145,7 +1153,8 @@ static nve32_t eqos_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = eqos_frp_write(osi_core, EQOS_MTL_FRP_IE0(pos), val); if (ret < 0) { /* Match Data Write fail */ - return -1; + ret = -1; + goto done; } /** Write Match Enable into IE1 **/ @@ -1153,7 +1162,8 @@ static nve32_t eqos_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = eqos_frp_write(osi_core, EQOS_MTL_FRP_IE1(pos), val); if (ret < 0) { /* Match Enable Write fail */ - return -1; + ret = -1; + goto done; } /** Write AF, RF, IM, NIC, FO and OKI into IE2 **/ @@ -1183,7 +1193,8 @@ static nve32_t eqos_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = eqos_frp_write(osi_core, EQOS_MTL_FRP_IE2(pos), val); if (ret < 0) { /* FRP IE2 Write fail */ - return -1; + ret = -1; + goto done; } /** Write DCH into IE3 **/ @@ -1191,12 +1202,12 @@ static nve32_t eqos_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = eqos_frp_write(osi_core, EQOS_MTL_FRP_IE3(pos), val); if (ret < 0) { /* DCH Write fail */ - return -1; + ret = -1; } +done: return ret; } -#endif /* !OSI_STRIPPED_LIB */ /** \cond DO_NOT_DOCUMENT */ /** @@ -1411,6 +1422,7 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core, return 0; } #endif + /** * @brief eqos_configure_mac - Configure MAC * @@ -1625,188 +1637,6 @@ static void eqos_configure_dma(struct osi_core_priv_data *const osi_core) } /** \endcond */ -#ifndef OSI_STRIPPED_LIB -/** - * @brief eqos_enable_mtl_interrupts - Enable MTL interrupts - * - * Algorithm: enable MTL interrupts for EST - * - * @param[in] osi_core: OSI core private data structure. - * - * @note MAC should be init and started. see osi_start_mac() - */ -static inline void eqos_enable_mtl_interrupts( - struct osi_core_priv_data *const osi_core) -{ - nveu32_t mtl_est_ir = OSI_DISABLE; - void *addr = osi_core->base; - - mtl_est_ir = osi_readla(osi_core, (nveu8_t *) - addr + EQOS_MTL_EST_ITRE); - /* enable only MTL interrupt realted to - * Constant Gate Control Error - * Head-Of-Line Blocking due to Scheduling - * Head-Of-Line Blocking due to Frame Size - * BTR Error - * Switch to S/W owned list Complete - */ - mtl_est_ir |= (EQOS_MTL_EST_ITRE_CGCE | EQOS_MTL_EST_ITRE_IEHS | - EQOS_MTL_EST_ITRE_IEHF | EQOS_MTL_EST_ITRE_IEBE | - EQOS_MTL_EST_ITRE_IECC); - osi_writela(osi_core, mtl_est_ir, - (nveu8_t *)addr + EQOS_MTL_EST_ITRE); -} - -/** - * @brief eqos_enable_fpe_interrupts - Enable MTL interrupts - * - * Algorithm: enable FPE interrupts - * - * @param[in] osi_core: OSI core private data structure. - * - * @note MAC should be init and started. see osi_start_mac() - */ -static inline void eqos_enable_fpe_interrupts( - struct osi_core_priv_data *const osi_core) -{ - nveu32_t value = OSI_DISABLE; - void *addr = osi_core->base; - - /* Read MAC IER Register and enable Frame Preemption Interrupt - * Enable */ - value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_IMR); - value |= EQOS_IMR_FPEIE; - osi_writela(osi_core, value, (nveu8_t *)addr + EQOS_MAC_IMR); -} - -/** - * @brief eqos_save_gcl_params - save GCL configs in local core structure - * - * @param[in] osi_core: OSI core private data structure. - * - * @note MAC should be init and started. see osi_start_mac() - */ -static inline void eqos_save_gcl_params(struct osi_core_priv_data *osi_core) -{ - struct core_local *l_core = (struct core_local *)osi_core; - nveu32_t gcl_widhth[4] = {0, OSI_MAX_24BITS, OSI_MAX_28BITS, - OSI_MAX_32BITS}; - nveu32_t gcl_ti_mask[4] = {0, OSI_MASK_16BITS, OSI_MASK_20BITS, - OSI_MASK_24BITS}; - nveu32_t gcl_depthth[6] = {0, OSI_GCL_SIZE_64, OSI_GCL_SIZE_128, - OSI_GCL_SIZE_256, OSI_GCL_SIZE_512, - OSI_GCL_SIZE_1024}; - - if ((osi_core->hw_feature->gcl_width == 0U) || - (osi_core->hw_feature->gcl_width > 3U)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "Wrong HW feature GCL width\n", - (nveul64_t)osi_core->hw_feature->gcl_width); - } else { - l_core->gcl_width_val = - gcl_widhth[osi_core->hw_feature->gcl_width]; - l_core->ti_mask = gcl_ti_mask[osi_core->hw_feature->gcl_width]; - } - - if ((osi_core->hw_feature->gcl_depth == 0U) || - (osi_core->hw_feature->gcl_depth > 5U)) { - /* Do Nothing */ - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "Wrong HW feature GCL depth\n", - (nveul64_t)osi_core->hw_feature->gcl_depth); - } else { - l_core->gcl_dep = gcl_depthth[osi_core->hw_feature->gcl_depth]; - } -} - -/** - * @brief eqos_tsn_init - initialize TSN feature - * - * Algorithm: - * 1) If hardware support EST, - * a) Set default EST configuration - * b) Set enable interrupts - * 2) If hardware supports FPE - * a) Set default FPE configuration - * b) enable interrupts - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] est_sel: EST HW support present or not - * @param[in] fpe_sel: FPE HW support present or not - * - * @note MAC should be init and started. see osi_start_mac() - */ -static void eqos_tsn_init(struct osi_core_priv_data *osi_core, - nveu32_t est_sel, nveu32_t fpe_sel) -{ - nveu32_t val = 0x0; - nveu32_t temp = 0U; - - if (est_sel == OSI_ENABLE) { - eqos_save_gcl_params(osi_core); - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - EQOS_MTL_EST_CONTROL); - - /* - * PTOV PTP clock period * 6 - * dual-port RAM based asynchronous FIFO controllers or - * Single-port RAM based synchronous FIFO controllers - * CTOV 96 x Tx clock period - * : - * : - * set other default value - */ - val &= ~EQOS_MTL_EST_CONTROL_PTOV; - temp = EQOS_MTL_EST_PTOV_RECOMMEND; - temp = temp << EQOS_MTL_EST_CONTROL_PTOV_SHIFT; - val |= temp; - - val &= ~EQOS_MTL_EST_CONTROL_CTOV; - temp = EQOS_MTL_EST_CTOV_RECOMMEND; - temp = temp << EQOS_MTL_EST_CONTROL_CTOV_SHIFT; - val |= temp; - - /*Loop Count to report Scheduling Error*/ - val &= ~EQOS_MTL_EST_CONTROL_LCSE; - val |= EQOS_MTL_EST_CONTROL_LCSE_VAL; - - val &= ~(EQOS_MTL_EST_CONTROL_DDBF | - EQOS_MTL_EST_CONTROL_DFBS); - val |= EQOS_MTL_EST_CONTROL_DDBF; - - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - EQOS_MTL_EST_CONTROL); - - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - EQOS_MTL_EST_OVERHEAD); - val &= ~EQOS_MTL_EST_OVERHEAD_OVHD; - /* As per hardware team recommendation */ - val |= EQOS_MTL_EST_OVERHEAD_RECOMMEND; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - EQOS_MTL_EST_OVERHEAD); - - eqos_enable_mtl_interrupts(osi_core); - } - - if (fpe_sel == OSI_ENABLE) { - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - EQOS_MAC_RQC1R); - val &= ~EQOS_MAC_RQC1R_FPRQ; - temp = osi_core->residual_queue; - temp = temp << EQOS_MAC_RQC1R_FPRQ_SHIFT; - temp = (temp & EQOS_MAC_RQC1R_FPRQ); - val |= temp; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - EQOS_MAC_RQC1R); - - eqos_enable_fpe_interrupts(osi_core); - } - - /* CBS setting for TC should be by user application/IOCTL as - * per requirement */ -} -#endif /* !OSI_STRIPPED_LIB */ - /** * @brief Map DMA channels to a specific VM IRQ. * @@ -1990,13 +1820,11 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core, /* configure EQOS DMA */ eqos_configure_dma(osi_core); -#ifndef OSI_STRIPPED_LIB /* tsn initialization */ if (osi_core->hw_feature != OSI_NULL) { - eqos_tsn_init(osi_core, osi_core->hw_feature->est_sel, - osi_core->hw_feature->fpe_sel); + hw_tsn_init(osi_core, osi_core->hw_feature->est_sel, + osi_core->hw_feature->fpe_sel); } -#endif /* !OSI_STRIPPED_LIB */ /* initialize L3L4 Filters variable */ osi_core->l3l4_filter_bitmask = OSI_NONE; @@ -2006,7 +1834,6 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core, return ret; } -#ifndef OSI_STRIPPED_LIB /** * @brief eqos_handle_mac_fpe_intrs * @@ -2059,7 +1886,6 @@ static void eqos_handle_mac_fpe_intrs(struct osi_core_priv_data *osi_core) osi_writela(osi_core, val, (nveu8_t *)osi_core->base + EQOS_MAC_FPE_CTS); } -#endif /* !OSI_STRIPPED_LIB */ /** * @brief eqos_handle_mac_intrs - Handle MAC interrupts @@ -2136,12 +1962,10 @@ static void eqos_handle_mac_intrs(struct osi_core_priv_data *const osi_core, return; } -#ifndef OSI_STRIPPED_LIB if (((mac_isr & EQOS_MAC_IMR_FPEIS) == EQOS_MAC_IMR_FPEIS) && ((mac_imr & EQOS_IMR_FPEIE) == EQOS_IMR_FPEIE)) { eqos_handle_mac_fpe_intrs(osi_core); } -#endif /* !OSI_STRIPPED_LIB */ mac_pcs = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_PCS); @@ -2239,6 +2063,7 @@ static inline void update_dma_sr_stats( } } /** \endcond */ +#endif /* !OSI_STRIPPED_LIB */ /** * @brief eqos_handle_mtl_intrs - Handle MTL interrupts @@ -2263,7 +2088,7 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core) nveu32_t frm_err = 0U; nveu32_t temp = 0U; nveu32_t i = 0; - nveu64_t stat_val = 0U; + nveul64_t stat_val = 0U; nveu32_t value = 0U; val = osi_readla(osi_core, @@ -2274,7 +2099,7 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core) /* return if interrupt is not related to EST */ if (val == OSI_DISABLE) { - return; + goto done; } /* increase counter write 1 back will clear */ @@ -2374,8 +2199,10 @@ static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core) /* clear EST status register as interrupt is handled */ osi_writela(osi_core, val, (nveu8_t *)osi_core->base + EQOS_MTL_EST_STATUS); + +done: + return; } -#endif /* !OSI_STRIPPED_LIB */ #ifdef HSI_SUPPORT /** @@ -2488,10 +2315,8 @@ static void eqos_handle_common_intr(struct osi_core_priv_data *const osi_core) nveu32_t i = 0; nveu32_t dma_sr = 0; nveu32_t dma_ier = 0; -#ifndef OSI_STRIPPED_LIB nveu32_t mtl_isr = 0; nveu32_t frp_isr = 0U; -#endif /* !OSI_STRIPPED_LIB */ if (osi_core->mac_ver >= OSI_EQOS_MAC_5_30) { osi_writela(osi_core, EQOS_MAC_SBD_INTR, (nveu8_t *)osi_core->base + @@ -2547,7 +2372,6 @@ static void eqos_handle_common_intr(struct osi_core_priv_data *const osi_core) eqos_handle_mac_intrs(osi_core, dma_isr); -#ifndef OSI_STRIPPED_LIB /* Handle MTL inerrupts */ mtl_isr = osi_readla(osi_core, (nveu8_t *)base + EQOS_MTL_INTR_STATUS); @@ -2568,7 +2392,6 @@ static void eqos_handle_common_intr(struct osi_core_priv_data *const osi_core) EQOS_MTL_RXP_INTR_CS_PDRFIS); osi_writela(osi_core, frp_isr, (nveu8_t *)base + EQOS_MTL_RXP_INTR_CS); -#endif /* !OSI_STRIPPED_LIB */ } #if defined(MACSEC_SUPPORT) && !defined(OSI_STRIPPED_LIB) @@ -3819,314 +3642,6 @@ static nve32_t eqos_config_ptp_rxq(struct osi_core_priv_data *const osi_core, } #endif /* !OSI_STRIPPED_LIB */ -#ifndef OSI_STRIPPED_LIB -/** - * @brief eqos_hw_est_write - indirect write the GCL to Software own list - * (SWOL) - * - * @param[in] base: MAC base IOVA address. - * @param[in] addr_val: Address offset for indirect write. - * @param[in] data: Data to be written at offset. - * @param[in] gcla: Gate Control List Address, 0 for ETS register. - * 1 for GCL memory. - * - * @note MAC should be init and started. see osi_start_mac() - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t eqos_hw_est_write(struct osi_core_priv_data *osi_core, - nveu32_t addr_val, - nveu32_t data, nveu32_t gcla) -{ - void *base = osi_core->base; - nve32_t retry = 1000; - nveu32_t val = 0x0; - - osi_writela(osi_core, data, (nveu8_t *)base + EQOS_MTL_EST_DATA); - - val &= ~EQOS_MTL_EST_ADDR_MASK; - val |= (gcla == 1U) ? 0x0U : EQOS_MTL_EST_GCRR; - val |= EQOS_MTL_EST_SRWO; - val |= addr_val; - osi_writela(osi_core, val, - (nveu8_t *)base + EQOS_MTL_EST_GCL_CONTROL); - - while (--retry > 0) { - osi_core->osd_ops.udelay(OSI_DELAY_1US); - val = osi_readla(osi_core, (nveu8_t *)base + - EQOS_MTL_EST_GCL_CONTROL); - if ((val & EQOS_MTL_EST_SRWO) == EQOS_MTL_EST_SRWO) { - continue; - } - - break; - } - - if (((val & EQOS_MTL_EST_ERR0) == EQOS_MTL_EST_ERR0) || - (retry <= 0)) { - return -1; - } - - return 0; -} - -/** - * @brief eqos_hw_config_est - Read Setting for GCL from input and update - * registers. - * - * Algorithm: - * 1) Write TER, LLR and EST control register - * 2) Update GCL to sw own GCL (MTL_EST_Status bit SWOL will tell which is - * owned by SW) and store which GCL is in use currently in sw. - * 3) TODO set DBGB and DBGM for debugging - * 4) EST_data and GCRR to 1, update entry sno in ADDR and put data at - * est_gcl_data enable GCL MTL_EST_SSWL and wait for self clear or use - * SWLC in MTL_EST_Status. Please note new GCL will be pushed for each entry. - * 5) Configure btr. Update btr based on current time (current time - * should be updated based on PTP by this time) - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] est: EST configuration input argument. - * - * @note MAC should be init and started. see osi_start_mac() - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t eqos_hw_config_est(struct osi_core_priv_data *const osi_core, - struct osi_est_config *const est) -{ - void *base = osi_core->base; - nveu32_t btr[2] = {0}; - nveu32_t val = 0x0; - nveu32_t addr = 0x0; - nveu32_t i; - nve32_t ret = 0; - - if ((osi_core->hw_feature != OSI_NULL) && - (osi_core->hw_feature->est_sel == OSI_DISABLE)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "EST not supported in HW\n", 0ULL); - return -1; - } - - if (est->en_dis == OSI_DISABLE) { - val = osi_readla(osi_core, - (nveu8_t *)base + EQOS_MTL_EST_CONTROL); - val &= ~EQOS_MTL_EST_CONTROL_EEST; - osi_writela(osi_core, val, - (nveu8_t *)base + EQOS_MTL_EST_CONTROL); - return 0; - } - - btr[0] = est->btr[0]; - btr[1] = est->btr[1]; - - if ((btr[0] == 0U) && (btr[1] == 0U)) { - common_get_systime_from_mac(osi_core->base, osi_core->mac, - &btr[1], &btr[0]); - } - - if (gcl_validate(osi_core, est, btr, osi_core->mac) < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL validation failed\n", 0LL); - return -1; - } - - ret = eqos_hw_est_write(osi_core, EQOS_MTL_EST_CTR_LOW, est->ctr[0], - OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL CTR[0] failed\n", 0LL); - return ret; - } - /* check for est->ctr[i] not more than FF, TODO as per hw config - * parameter we can have max 0x3 as this value in sec */ - est->ctr[1] &= EQOS_MTL_EST_CTR_HIGH_MAX; - ret = eqos_hw_est_write(osi_core, EQOS_MTL_EST_CTR_HIGH, est->ctr[1], - OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL CTR[1] failed\n", 0LL); - return ret; - } - - ret = eqos_hw_est_write(osi_core, EQOS_MTL_EST_TER, est->ter, - OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL TER failed\n", 0LL); - return ret; - } - - ret = eqos_hw_est_write(osi_core, EQOS_MTL_EST_LLR, est->llr, - OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL LLR failed\n", 0LL); - return ret; - } - - /* Write GCL table */ - for (i = 0U; i < est->llr; i++) { - addr = i; - addr = addr << EQOS_MTL_EST_ADDR_SHIFT; - addr &= EQOS_MTL_EST_ADDR_MASK; - ret = eqos_hw_est_write(osi_core, addr, est->gcl[i], - OSI_ENABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL enties write failed\n", - (nveul64_t)i); - return ret; - } - } - - /* Write parameters */ - ret = eqos_hw_est_write(osi_core, EQOS_MTL_EST_BTR_LOW, - btr[0] + est->btr_offset[0], OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL BTR[0] failed\n", - (nveul64_t)(btr[0] + - est->btr_offset[0])); - return ret; - } - - ret = eqos_hw_est_write(osi_core, EQOS_MTL_EST_BTR_HIGH, - btr[1] + est->btr_offset[1], OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL BTR[1] failed\n", - (nveul64_t)(btr[1] + - est->btr_offset[1])); - return ret; - } - - val = osi_readla(osi_core, (nveu8_t *) - base + EQOS_MTL_EST_CONTROL); - /* Store table */ - val |= EQOS_MTL_EST_CONTROL_SSWL; - val |= EQOS_MTL_EST_CONTROL_EEST; - val |= EQOS_MTL_EST_CONTROL_QHLBF; - osi_writela(osi_core, val, (nveu8_t *)base + EQOS_MTL_EST_CONTROL); - - return ret; -} - -/** - * @brief eqos_hw_config_fep - Read Setting for preemption and express for TC - * and update registers. - * - * Algorithm: - * 1) Check for TC enable and TC has masked for setting to preemptable. - * 2) update FPE control status register - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] fpe: FPE configuration input argument. - * - * @note MAC should be init and started. see osi_start_mac() - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t eqos_hw_config_fpe(struct osi_core_priv_data *const osi_core, - struct osi_fpe_config *const fpe) -{ - nveu32_t i = 0U; - nveu32_t val = 0U; - nveu32_t temp = 0U, temp1 = 0U; - nveu32_t temp_shift = 0U; - - if ((osi_core->hw_feature != OSI_NULL) && - (osi_core->hw_feature->fpe_sel == OSI_DISABLE)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "FPE not supported in HW\n", 0ULL); - return -1; - } - - osi_core->fpe_ready = OSI_DISABLE; - - - if (((fpe->tx_queue_preemption_enable << EQOS_MTL_FPE_CTS_PEC_SHIFT) & - EQOS_MTL_FPE_CTS_PEC) == OSI_DISABLE) { - val = osi_readla(osi_core, - (nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS); - val &= ~EQOS_MTL_FPE_CTS_PEC; - osi_writela(osi_core, val, - (nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS); - - val = osi_readla(osi_core, - (nveu8_t *)osi_core->base + EQOS_MAC_FPE_CTS); - val &= ~EQOS_MAC_FPE_CTS_EFPE; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - EQOS_MAC_FPE_CTS); - - return 0; - } - - val = osi_readla(osi_core, - (nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS); - val &= ~EQOS_MTL_FPE_CTS_PEC; - for (i = 0U; i < OSI_MAX_TC_NUM; i++) { - /* max 8 bit for this structure fot TC/TXQ. Set the TC for express or - * preemption. Default is express for a TC. DWCXG_NUM_TC = 8 */ - temp = OSI_BIT(i); - if ((fpe->tx_queue_preemption_enable & temp) == temp) { - temp_shift = i; - temp_shift += EQOS_MTL_FPE_CTS_PEC_SHIFT; - /* set queue for preemtable */ - if (temp_shift < EQOS_MTL_FPE_CTS_PEC_MAX_SHIFT) { - temp1 = OSI_ENABLE; - temp1 = temp1 << temp_shift; - val |= temp1; - } else { - /* Do nothing */ - } - } - } - osi_writela(osi_core, val, - (nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS); - - /* Setting RQ as RxQ 0 is not allowed */ - if ((fpe->rq == 0x0U) || (fpe->rq >= OSI_EQOS_MAX_NUM_CHANS)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "EST init failed due to wrong RQ\n", fpe->rq); - return -1; - } - - val = osi_readla(osi_core, - (nveu8_t *)osi_core->base + EQOS_MAC_RQC1R); - val &= ~EQOS_MAC_RQC1R_FPRQ; - temp = fpe->rq; - temp = temp << EQOS_MAC_RQC1R_FPRQ_SHIFT; - temp = (temp & EQOS_MAC_RQC1R_FPRQ); - val |= temp; - /* update RQ in OSI CORE struct */ - osi_core->residual_queue = fpe->rq; - osi_writela(osi_core, val, - (nveu8_t *)osi_core->base + EQOS_MAC_RQC1R); - - /* initiate SVER for SMD-V and SMD-R */ - val = osi_readla(osi_core, - (nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS); - val |= EQOS_MAC_FPE_CTS_SVER; - osi_writela(osi_core, val, - (nveu8_t *)osi_core->base + EQOS_MAC_FPE_CTS); - - val = osi_readla(osi_core, - (nveu8_t *)osi_core->base + EQOS_MTL_FPE_ADV); - val &= ~EQOS_MTL_FPE_ADV_HADV_MASK; - /* (minimum_fragment_size +IPG/EIPG + Preamble) *.8 ~98ns for10G */ - val |= EQOS_MTL_FPE_ADV_HADV_VAL; - osi_writela(osi_core, val, - (nveu8_t *)osi_core->base + EQOS_MTL_FPE_ADV); - - return 0; -} -#endif /* !OSI_STRIPPED_LIB */ - /** \cond DO_NOT_DOCUMENT */ /** * @brief poll_for_mii_idle Query the status of an ongoing DMA transfer @@ -4674,6 +4189,7 @@ static nve32_t eqos_config_tx_status(struct osi_core_priv_data *const osi_core, return 0; } +#endif /* !OSI_STRIPPED_LIB */ /** * @brief eqos_set_avb_algorithm - Set TxQ/TC avb config @@ -4717,21 +4233,21 @@ static nve32_t eqos_set_avb_algorithm( if (avb == OSI_NULL) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "avb structure is NULL\n", 0ULL); - return ret; + goto done; } /* queue index in range */ if (avb->qindex >= OSI_EQOS_MAX_NUM_QUEUES) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid Queue index\n", (nveul64_t)avb->qindex); - return ret; + goto done; } /* queue oper_mode in range check*/ if (avb->oper_mode >= OSI_MTL_QUEUE_MODEMAX) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid Queue mode\n", (nveul64_t)avb->qindex); - return ret; + goto done; } /* can't set AVB mode for queue 0 */ @@ -4739,7 +4255,7 @@ static nve32_t eqos_set_avb_algorithm( OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_OPNOTSUPP, "Not allowed to set AVB for Q0\n", (nveul64_t)avb->qindex); - return ret; + goto done; } qinx = avb->qindex; @@ -4804,7 +4320,9 @@ static nve32_t eqos_set_avb_algorithm( EQOS_MTL_TXQ_ETS_LCR(qinx)); } - return 0; + ret = 0; +done: + return ret; } /** @@ -4848,13 +4366,13 @@ static nve32_t eqos_get_avb_algorithm(struct osi_core_priv_data *const osi_core, if (avb == OSI_NULL) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "avb structure is NULL\n", 0ULL); - return ret; + goto done; } if (avb->qindex >= OSI_EQOS_MAX_NUM_QUEUES) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid Queue index\n", (nveul64_t)avb->qindex); - return ret; + goto done; } qinx = avb->qindex; @@ -4895,9 +4413,13 @@ static nve32_t eqos_get_avb_algorithm(struct osi_core_priv_data *const osi_core, EQOS_MTL_TXQ_ETS_LCR(qinx)); avb->low_credit = value & EQOS_MTL_TXQ_ETS_LCR_LC_MASK; - return 0; + ret = 0; + +done: + return ret; } +#ifndef OSI_STRIPPED_LIB /** * @brief eqos_config_arp_offload - Enable/Disable ARP offload * @@ -5738,7 +5260,7 @@ static void eqos_config_for_macsec(struct osi_core_priv_data *const osi_core, if ((enable != OSI_ENABLE) && (enable != OSI_DISABLE)) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Failed to config EQOS per MACSEC\n", 0ULL); - goto exit; + goto done; } if (osi_core->mac_ver == OSI_EQOS_MAC_5_30) { /* stop MAC Tx */ @@ -5806,7 +5328,7 @@ static void eqos_config_for_macsec(struct osi_core_priv_data *const osi_core, OSI_LOG_ARG_HW_FAIL, "Error: osi_core->hw_feature is NULL\n", 0ULL); } -exit: +done: return; } @@ -5843,6 +5365,11 @@ void eqos_init_core_ops(struct core_ops *ops) ops->update_ip4_addr = eqos_update_ip4_addr; ops->read_reg = eqos_read_reg; ops->write_reg = eqos_write_reg; + ops->set_avb_algorithm = eqos_set_avb_algorithm; + ops->get_avb_algorithm = eqos_get_avb_algorithm; + ops->config_frp = eqos_config_frp; + ops->update_frp_entry = eqos_update_frp_entry; + ops->update_frp_nve = eqos_update_frp_nve; #ifdef MACSEC_SUPPORT ops->read_macsec_reg = eqos_read_macsec_reg; ops->write_macsec_reg = eqos_write_macsec_reg; @@ -5860,8 +5387,6 @@ void eqos_init_core_ops(struct core_ops *ops) ops->config_arp_offload = eqos_config_arp_offload; ops->config_ptp_offload = eqos_config_ptp_offload; ops->validate_regs = eqos_validate_core_regs; - ops->set_avb_algorithm = eqos_set_avb_algorithm; - ops->get_avb_algorithm = eqos_get_avb_algorithm; ops->config_vlan_filtering = eqos_config_vlan_filtering; ops->reset_mmc = eqos_reset_mmc; ops->configure_eee = eqos_configure_eee; @@ -5869,11 +5394,6 @@ void eqos_init_core_ops(struct core_ops *ops) ops->restore_registers = eqos_restore_registers; ops->set_mdc_clk_rate = eqos_set_mdc_clk_rate; ops->config_mac_loopback = eqos_config_mac_loopback; - ops->hw_config_est = eqos_hw_config_est; - ops->hw_config_fpe = eqos_hw_config_fpe; - ops->config_frp = eqos_config_frp; - ops->update_frp_entry = eqos_update_frp_entry; - ops->update_frp_nve = eqos_update_frp_nve; ops->config_rss = eqos_config_rss; ops->config_ptp_rxq = eqos_config_ptp_rxq; #endif /* !OSI_STRIPPED_LIB */ diff --git a/osi/core/eqos_core.h b/osi/core/eqos_core.h index 99142a3..fd963f0 100644 --- a/osi/core/eqos_core.h +++ b/osi/core/eqos_core.h @@ -28,20 +28,6 @@ #define EQOS_MAC_LPI_CSR 0x00D0 #define EQOS_MAC_LPI_TIMER_CTRL 0x00D4 #define EQOS_MAC_LPI_EN_TIMER 0x00D8 -#define EQOS_MTL_EST_CONTROL 0x0C50 -#define EQOS_MTL_EST_OVERHEAD 0x0C54 -#define EQOS_MTL_EST_STATUS 0x0C58 -#define EQOS_MTL_EST_SCH_ERR 0x0C60 -#define EQOS_MTL_EST_FRMS_ERR 0x0C64 -#define EQOS_MTL_EST_ITRE 0x0C70 -#define EQOS_MTL_EST_GCL_CONTROL 0x0C80 -#define EQOS_MTL_EST_DATA 0x0C84 -#define EQOS_MTL_FPE_CTS 0x0C90 -#define EQOS_MTL_FPE_ADV 0x0C94 -#define EQOS_MTL_RXP_CS 0x0CA0 -#define EQOS_MTL_RXP_INTR_CS 0x0CA4 -#define EQOS_MTL_RXP_IND_CS 0x0CB0 -#define EQOS_MTL_RXP_IND_DATA 0x0CB4 #define EQOS_MAC_RX_FLW_CTRL 0x0090 #define EQOS_MAC_STNSR 0x0B0C #define EQOS_MAC_STSR 0x0B08 @@ -52,17 +38,6 @@ #define EQOS_MAC_PIDR2 0x0BCC #define EQOS_MAC_PMTCSR 0x00C0 #define EQOS_MAC_QX_TX_FLW_CTRL(x) ((0x0004U * (x)) + 0x0070U) -#define EQOS_MTL_TXQ_ETS_CR(x) ((0x0040U * (x)) + 0x0D10U) -#define EQOS_MTL_TXQ_ETS_SSCR(x) ((0x0040U * (x)) + 0x0D1CU) -#define EQOS_MTL_TXQ_ETS_HCR(x) ((0x0040U * (x)) + 0x0D20U) -#define EQOS_MTL_TXQ_ETS_LCR(x) ((0x0040U * (x)) + 0x0D24U) -#define EQOS_MAC_HTR_REG(x) ((0x0004U * (x)) + 0x0010U) -#define EQOS_MAC_L3_AD2R(x) ((0x0030U * (x)) + 0x0918U) -#define EQOS_MAC_L3_AD3R(x) ((0x0030U * (x)) + 0x091CU) -#define EQOS_MAC_L4_ADR(x) ((0x0030U * (x)) + 0x0904U) -#define EQOS_MTL_INTR_STATUS 0x0C20 -#define EQOS_MTL_OP_MODE 0x0C00 -#define EQOS_MAC_FPE_CTS 0x0234 #define EQOS_MAC_MA0HR 0x0300 #define EQOS_4_10_MAC_ARPPA 0x0AE0 #define EQOS_5_00_MAC_ARPPA 0x0210 @@ -98,9 +73,11 @@ #define EQOS_MAC_IMR_MASK 0x67039U #define EQOS_MAC_HTR_MASK 0xFFFFFFFFU #define EQOS_MAC_HTR0_IDX 2U -#define EQOS_IMR_FPEIE OSI_BIT(17) +#define EQOS_MAC_HTR_REG(x) ((0x0004U * (x)) + 0x0010U) +#define EQOS_MAC_L3_AD2R(x) ((0x0030U * (x)) + 0x0918U) +#define EQOS_MAC_L3_AD3R(x) ((0x0030U * (x)) + 0x091CU) +#define EQOS_MAC_L4_ADR(x) ((0x0030U * (x)) + 0x0904U) #define EQOS_DMA_SBUS_MASK 0xDF1F3CFFU -#define EQOS_DMA_ISR_MTLIS OSI_BIT(16) #define EQOS_DMA_CHX_STATUS_FBE OSI_BIT(10) #define EQOS_DMA_CHX_STATUS_TBU OSI_BIT(2) #define EQOS_DMA_CHX_STATUS_RBU OSI_BIT(7) @@ -108,6 +85,88 @@ #define EQOS_DMA_CHX_STATUS_RWT OSI_BIT(9) #define EQOS_DMA_CHX_STATUS_TPS OSI_BIT(1) #define EQOS_MAC_L3L4_CTR_L4DPI_SHIFT 21 +#define EQOS_MAC_RQC0R_MASK 0xFFU +#define EQOS_MAC_QX_TX_FLW_CTRL_TFE OSI_BIT(1) +#define EQOS_MAC_QX_TXFC_MASK 0xFFFF00F2U +#define EQOS_MAC_Q0_TXFC_IDX 6U +#define EQOS_MAC_PTO_CR_ASYNCEN OSI_BIT(1) +#define EQOS_MAC_RQC1R_OMCBCQ OSI_BIT(28) +#define EQOS_MAC_PIDR_PID_MASK 0XFFFFU +#define EQOS_MAC_PFR_MASK 0x803107FFU +#define EQOS_MAC_PAUSE_TIME 0xFFFF0000U +#define EQOS_MAC_PAUSE_TIME_MASK 0xFFFF0000U +#define EQOS_MAC_MCR_MASK 0xFFFFFF7FU +#define EQOS_MAC_MA0LR_IDX 12U +#define EQOS_MAC_MA0LR_MASK 0xFFFFFFFFU +#define EQOS_MAC_PTO_CR_DN (OSI_BIT(15) | OSI_BIT(14) | \ + OSI_BIT(13) | OSI_BIT(12) | \ + OSI_BIT(11) | OSI_BIT(10) | \ + OSI_BIT(9) | OSI_BIT(8)) +#define EQOS_MAC_PTO_CR_DN_SHIFT 8U +#define EQOS_MAC_PTO_CR_APDREQEN OSI_BIT(2) +#define EQOS_MAC_PTO_CR_PTOEN OSI_BIT(0) + +#define EQOS_MCR_IPG_MASK 0x7000000U +#define EQOS_MCR_IPG_SHIFT 24U +#define EQOS_MCR_IPG 0x7U +#define EQOS_MAC_TCR_TSENMACADDR OSI_BIT(18) +#define EQOS_MAC_TCR_SNAPTYPSEL_SHIFT 16U +#define EQOS_MAC_TAR_IDX 15U +#define EQOS_MAC_SSIR_IDX 14U +#define EQOS_MAC_RX_FLW_CTRL_RFE OSI_BIT(0) +#define EQOS_MAC_TCR_MASK 0x1107FF03U +#define EQOS_MAC_TAR_MASK 0xFFFFFFFFU +#define EQOS_MAC_SSIR_MASK 0xFFFF00U +#define EQOS_MAC_RQC2R_MASK 0xFFFFFFFFU +#define EQOS_MAC_RQC1R_TPQC (OSI_BIT(22) | OSI_BIT(23)) +#define EQOS_MAC_RQC1R_TPQC0 OSI_BIT(22) +#define EQOS_MAC_RQC1R_PTPQ (OSI_BIT(6) | OSI_BIT(5) | \ + OSI_BIT(4)) +#define EQOS_MAC_RQC1R_PTPQ_SHIFT 4U +/** + * @addtogroup EQOS-MDC MDC Clock Selection defines + * + * @brief MDC Clock defines + * @{ + */ +#define EQOS_CSR_60_100M 0x0 /* MDC = clk_csr/42 */ +#define EQOS_CSR_100_150M 0x1 /* MDC = clk_csr/62 */ +#define EQOS_CSR_20_35M 0x2 /* MDC = clk_csr/16 */ +#define EQOS_CSR_35_60M 0x3 /* MDC = clk_csr/26 */ +#define EQOS_CSR_150_250M 0x4 /* MDC = clk_csr/102 */ +#define EQOS_CSR_250_300M 0x5 /* MDC = clk_csr/124 */ +#define EQOS_CSR_300_500M 0x6 /* MDC = clk_csr/204 */ +#define EQOS_CSR_500_800M 0x7 /* MDC = clk_csr/324 */ +/** @} */ +#define EQOS_MAC_LPI_CSR_LPITE OSI_BIT(20) +#define EQOS_MAC_LPI_CSR_LPITXA OSI_BIT(19) +#define EQOS_MAC_LPI_CSR_PLS OSI_BIT(17) +#define EQOS_MAC_LPI_CSR_LPIEN OSI_BIT(16) +#endif /* !OSI_STRIPPED_LIB */ +#define EQOS_MTL_EST_CONTROL 0x0C50 +#define EQOS_MTL_EST_OVERHEAD 0x0C54 +#define EQOS_MTL_EST_STATUS 0x0C58 +#define EQOS_MTL_EST_SCH_ERR 0x0C60 +#define EQOS_MTL_EST_FRMS_ERR 0x0C64 +#define EQOS_MTL_EST_ITRE 0x0C70 +#define EQOS_MTL_EST_GCL_CONTROL 0x0C80 +#define EQOS_MTL_EST_DATA 0x0C84 +#define EQOS_MTL_FPE_CTS 0x0C90 +#define EQOS_MTL_FPE_ADV 0x0C94 +#define EQOS_MTL_RXP_CS 0x0CA0 +#define EQOS_MTL_RXP_INTR_CS 0x0CA4 +#define EQOS_MTL_RXP_IND_CS 0x0CB0 +#define EQOS_MTL_RXP_IND_DATA 0x0CB4 +#define EQOS_MTL_TXQ_ETS_CR(x) ((0x0040U * (x)) + 0x0D10U) +#define EQOS_MTL_TXQ_ETS_SSCR(x) ((0x0040U * (x)) + 0x0D1CU) +#define EQOS_MTL_TXQ_ETS_HCR(x) ((0x0040U * (x)) + 0x0D20U) +#define EQOS_MTL_TXQ_ETS_LCR(x) ((0x0040U * (x)) + 0x0D24U) +#define EQOS_MTL_INTR_STATUS 0x0C20 +#define EQOS_MTL_OP_MODE 0x0C00 +#define EQOS_MAC_FPE_CTS 0x0234 +#define EQOS_IMR_FPEIE OSI_BIT(17) +#define EQOS_MTL_FRP_IE2_DCH_SHIFT 24U +#define EQOS_DMA_ISR_MTLIS OSI_BIT(16) /** * @addtogroup EQOS-MTL FRP Indirect Access register defines * @@ -148,10 +207,14 @@ #define EQOS_MTL_RXP_INTR_CS_NPEOVIS OSI_BIT(1) #define EQOS_MTL_RXP_INTR_CS_NVEOVIS OSI_BIT(0) +#ifndef OSI_STRIPPED_LIB #define EQOS_RXQ_DMA_MAP0_MASK 0x13131313U #define EQOS_MTL_TXQ_QW_MASK 0x1FFFFFU #define EQOS_PAD_AUTO_CAL_CFG_MASK 0x7FFFFFFFU #define EQOS_MTL_TXQ_OP_MODE_MASK 0xFF007EU +#define EQOS_MTL_RXQ_OP_MODE_MASK 0xFFFFFFBU +#define EQOS_MAC_RQC1R_MASK 0xF77077U +#endif /* !OSI_STRIPPED_LIB */ #define EQOS_MTL_TXQ_ETS_SSCR_SSC_MASK 0x00003FFFU #define EQOS_MTL_TXQ_ETS_QW_ISCQW_MASK 0x000FFFFFU #define EQOS_MTL_TXQ_ETS_HCR_HC_MASK 0x1FFFFFFFU @@ -160,32 +223,9 @@ #define EQOS_MTL_TXQ_ETS_CR_AVALG OSI_BIT(2) #define EQOS_MTL_TXQ_ETS_CR_CC_SHIFT 3U #define EQOS_MTL_TXQ_ETS_CR_AVALG_SHIFT 2U -#define EQOS_MTL_RXQ_OP_MODE_MASK 0xFFFFFFBU -#define EQOS_MAC_RQC1R_MASK 0xF77077U #define EQOS_MAC_RQC1R_FPRQ (OSI_BIT(26) | OSI_BIT(25) | \ OSI_BIT(24)) #define EQOS_MAC_RQC1R_FPRQ_SHIFT 24U -#define EQOS_MAC_RQC0R_MASK 0xFFU -#define EQOS_MAC_QX_TX_FLW_CTRL_TFE OSI_BIT(1) -#define EQOS_MAC_QX_TXFC_MASK 0xFFFF00F2U -#define EQOS_MAC_Q0_TXFC_IDX 6U -#define EQOS_MAC_PTO_CR_ASYNCEN OSI_BIT(1) -#define EQOS_MAC_RQC1R_OMCBCQ OSI_BIT(28) -#define EQOS_MAC_PIDR_PID_MASK 0XFFFFU -#define EQOS_MAC_PFR_MASK 0x803107FFU -#define EQOS_MAC_PAUSE_TIME 0xFFFF0000U -#define EQOS_MAC_PAUSE_TIME_MASK 0xFFFF0000U -#define EQOS_MAC_MCR_MASK 0xFFFFFF7FU -#define EQOS_MAC_MA0LR_IDX 12U -#define EQOS_MAC_MA0LR_MASK 0xFFFFFFFFU -#define EQOS_MAC_PTO_CR_DN (OSI_BIT(15) | OSI_BIT(14) | \ - OSI_BIT(13) | OSI_BIT(12) | \ - OSI_BIT(11) | OSI_BIT(10) | \ - OSI_BIT(9) | OSI_BIT(8)) -#define EQOS_MAC_PTO_CR_DN_SHIFT 8U -#define EQOS_MAC_PTO_CR_APDREQEN OSI_BIT(2) -#define EQOS_MAC_PTO_CR_PTOEN OSI_BIT(0) - /* Indirect Instruction Table defines */ #define EQOS_MTL_FRP_IE0(x) (((x) * 0x4U) + 0x0U) #define EQOS_MTL_FRP_IE1(x) (((x) * 0x4U) + 0x1U) @@ -209,44 +249,6 @@ #define EQOS_MTL_FRP_IE2_RF OSI_BIT(1) #define EQOS_MTL_FRP_IE2_AF OSI_BIT(0) -#define EQOS_MCR_IPG_MASK 0x7000000U -#define EQOS_MCR_IPG_SHIFT 24U -#define EQOS_MCR_IPG 0x7U -#define EQOS_MAC_TCR_TSENMACADDR OSI_BIT(18) -#define EQOS_MAC_TCR_SNAPTYPSEL_SHIFT 16U -#define EQOS_MAC_TAR_IDX 15U -#define EQOS_MAC_SSIR_IDX 14U -#define EQOS_MAC_RX_FLW_CTRL_RFE OSI_BIT(0) -#define EQOS_MAC_TCR_MASK 0x1107FF03U -#define EQOS_MAC_TAR_MASK 0xFFFFFFFFU -#define EQOS_MAC_SSIR_MASK 0xFFFF00U -#define EQOS_MAC_RQC2R_MASK 0xFFFFFFFFU -#define EQOS_MAC_RQC1R_TPQC (OSI_BIT(22) | OSI_BIT(23)) -#define EQOS_MAC_RQC1R_TPQC0 OSI_BIT(22) -#define EQOS_MAC_RQC1R_PTPQ (OSI_BIT(6) | OSI_BIT(5) | \ - OSI_BIT(4)) -#define EQOS_MAC_RQC1R_PTPQ_SHIFT 4U -/** - * @addtogroup EQOS-MDC MDC Clock Selection defines - * - * @brief MDC Clock defines - * @{ - */ -#define EQOS_CSR_60_100M 0x0 /* MDC = clk_csr/42 */ -#define EQOS_CSR_100_150M 0x1 /* MDC = clk_csr/62 */ -#define EQOS_CSR_20_35M 0x2 /* MDC = clk_csr/16 */ -#define EQOS_CSR_35_60M 0x3 /* MDC = clk_csr/26 */ -#define EQOS_CSR_150_250M 0x4 /* MDC = clk_csr/102 */ -#define EQOS_CSR_250_300M 0x5 /* MDC = clk_csr/124 */ -#define EQOS_CSR_300_500M 0x6 /* MDC = clk_csr/204 */ -#define EQOS_CSR_500_800M 0x7 /* MDC = clk_csr/324 */ -/** @} */ -#define EQOS_MTL_FRP_IE2_DCH_SHIFT 24U -#define EQOS_MAC_LPI_CSR_LPITE OSI_BIT(20) -#define EQOS_MAC_LPI_CSR_LPITXA OSI_BIT(19) -#define EQOS_MAC_LPI_CSR_PLS OSI_BIT(17) -#define EQOS_MAC_LPI_CSR_LPIEN OSI_BIT(16) -#endif /* !OSI_STRIPPED_LIB */ /** * @addtogroup EQOS-SIZE SIZE calculation helper Macros * @@ -440,8 +442,6 @@ #define EQOS_MAC_ENABLE_LM OSI_BIT(12) #define EQOS_MCR_ARPEN OSI_BIT(31) #define EQOS_RX_CLK_SEL OSI_BIT(8) -#define EQOS_MTL_TXQEN_MASK (OSI_BIT(3) | OSI_BIT(2)) -#define EQOS_MTL_TXQEN_MASK_SHIFT 2U #define EQOS_MTL_OP_MODE_DTXSTS OSI_BIT(1) #define EQOS_MAC_VLAN_TR 0x0050U #define EQOS_MAC_VLAN_TR_VTIM OSI_BIT(17) @@ -449,14 +449,25 @@ #define EQOS_MAC_VLAN_TR_VTHM OSI_BIT(25) #define EQOS_MAC_STNSR_TSSS_MASK 0x7FFFFFFFU #define EQOS_MAC_PFR_SHIFT 16 -#define EQOS_MTL_OP_MODE_FRPE OSI_BIT(15) #define EQOS_MTL_OP_MODE_DTXSTS OSI_BIT(1) #define EQOS_MAC_EXTR_DCRCC OSI_BIT(16) +#define EQOS_MTL_TXQ_ETS_SSCR_SSC_MASK 0x00003FFFU +#define EQOS_MTL_TXQ_ETS_QW_ISCQW_MASK 0x000FFFFFU +#define EQOS_MTL_TXQ_ETS_HCR_HC_MASK 0x1FFFFFFFU +#define EQOS_MTL_TXQ_ETS_LCR_LC_MASK 0x1FFFFFFFU +#define EQOS_MTL_TXQ_ETS_CR_AVALG OSI_BIT(2) +#define EQOS_MTL_TXQ_ETS_CR_AVALG_SHIFT 2U +#define EQOS_MTL_TXQ_ETS_CR_CC OSI_BIT(3) +#define EQOS_MTL_TXQ_ETS_CR_CC_SHIFT 3U +#define EQOS_MAC_EXTR_PDC OSI_BIT(19) #define EQOS_MAC_EXTR_EIPGEN OSI_BIT(24) #define EQOS_MAC_EXTR_EIPG_MASK 0x3E000000U #define EQOS_MAC_EXTR_EIPG_SHIFT 25U #define EQOS_MAC_EXTR_EIPG 0x3U #endif /* !OSI_STRIPPED_LIB */ +#define EQOS_MTL_TXQEN_MASK (OSI_BIT(3) | OSI_BIT(2)) +#define EQOS_MTL_TXQEN_MASK_SHIFT 2U +#define EQOS_MTL_OP_MODE_FRPE OSI_BIT(15) #define EQOS_MAC_EXTR_PDC OSI_BIT(19) #define EQOS_MTL_RXQ_OP_MODE_EHFC OSI_BIT(7) #define EQOS_MTL_RXQ_OP_MODE_RFA_SHIFT 8U @@ -563,26 +574,14 @@ (TEGRA_SID_EQOS)) #define EQOS_MMC_INTR_DISABLE 0xFFFFFFFFU -#ifndef OSI_STRIPPED_LIB /* MAC FPE control/statusOSI_BITmap */ #define EQOS_MAC_FPE_CTS_EFPE OSI_BIT(0) #define EQOS_MAC_FPE_CTS_TRSP OSI_BIT(19) #define EQOS_MAC_FPE_CTS_TVER OSI_BIT(18) #define EQOS_MAC_FPE_CTS_RRSP OSI_BIT(17) #define EQOS_MAC_FPE_CTS_RVER OSI_BIT(16) -#define EQOS_MAC_FPE_CTS_SVER OSI_BIT(1) #define EQOS_MAC_FPE_CTS_SRSP OSI_BIT(2) -/* MTL_FPE_CTRL_STS */ -#define EQOS_MTL_FPE_CTS_PEC (OSI_BIT(8) | OSI_BIT(9) | \ - OSI_BIT(10) | OSI_BIT(11) | \ - OSI_BIT(12) | OSI_BIT(13) | \ - OSI_BIT(14) | OSI_BIT(15)) -#define EQOS_MTL_FPE_CTS_PEC_SHIFT 8U -#define EQOS_MTL_FPE_CTS_PEC_MAX_SHIFT 16U -/* MTL FPE adv registers */ -#define EQOS_MTL_FPE_ADV_HADV_MASK (0xFFFFU) -#define EQOS_MTL_FPE_ADV_HADV_VAL 100U /* MTL_EST_CONTROL */ #define EQOS_MTL_EST_CONTROL_PTOV (OSI_BIT(24) | OSI_BIT(25) | \ OSI_BIT(26) | OSI_BIT(27) | \ @@ -599,14 +598,10 @@ #define EQOS_MTL_EST_CONTROL_CTOV_SHIFT 12U #define EQOS_MTL_EST_CTOV_RECOMMEND 94U #define EQOS_8PTP_CYCLE 40U -#define EQOS_MTL_EST_CONTROL_TILS (OSI_BIT(8) | OSI_BIT(9) | \ - OSI_BIT(10)) #define EQOS_MTL_EST_CONTROL_LCSE (OSI_BIT(6) | OSI_BIT(5)) #define EQOS_MTL_EST_CONTROL_LCSE_VAL 0U #define EQOS_MTL_EST_CONTROL_DFBS OSI_BIT(5) #define EQOS_MTL_EST_CONTROL_DDBF OSI_BIT(4) -#define EQOS_MTL_EST_CONTROL_QHLBF OSI_BIT(3) -#define EQOS_MTL_EST_CONTROL_SSWL OSI_BIT(1) #define EQOS_MTL_EST_CONTROL_EEST OSI_BIT(0) #define EQOS_MTL_EST_OVERHEAD_OVHD (OSI_BIT(5) | OSI_BIT(4) | \ OSI_BIT(3) | OSI_BIT(2) | \ @@ -614,15 +609,6 @@ #define EQOS_MTL_EST_OVERHEAD_RECOMMEND 0x17U /* EST GCL controlOSI_BITmap */ #define EQOS_MTL_EST_ADDR_SHIFT 8U -#define EQOS_MTL_EST_ADDR_MASK (OSI_BIT(8) | OSI_BIT(9) | \ - OSI_BIT(10) | OSI_BIT(11) | \ - OSI_BIT(12) | OSI_BIT(13) | \ - OSI_BIT(14) | OSI_BIT(15) | \ - OSI_BIT(16) | OSI_BIT(17) | \ - OSI_BIT(18) | OSI_BIT(19)) -#define EQOS_MTL_EST_SRWO OSI_BIT(0) -#define EQOS_MTL_EST_GCRR OSI_BIT(2) -#define EQOS_MTL_EST_ERR0 OSI_BIT(20) /* EST GCRA addresses */ #define EQOS_MTL_EST_BTR_LOW ((nveu32_t)0x0 << \ EQOS_MTL_EST_ADDR_SHIFT) @@ -632,7 +618,6 @@ EQOS_MTL_EST_ADDR_SHIFT) #define EQOS_MTL_EST_CTR_HIGH ((nveu32_t)0x3 << \ EQOS_MTL_EST_ADDR_SHIFT) -#define EQOS_MTL_EST_CTR_HIGH_MAX 0xFFU #define EQOS_MTL_EST_TER ((nveu32_t)0x4 << \ EQOS_MTL_EST_ADDR_SHIFT) #define EQOS_MTL_EST_LLR ((nveu32_t)0x5 << \ @@ -645,12 +630,6 @@ #define EQOS_MTL_EST_STATUS_HLBF OSI_BIT(2) #define EQOS_MTL_EST_STATUS_BTRE OSI_BIT(1) #define EQOS_MTL_EST_STATUS_SWLC OSI_BIT(0) -#define EQOS_MTL_EST_ITRE_CGCE OSI_BIT(4) -#define EQOS_MTL_EST_ITRE_IEHS OSI_BIT(3) -#define EQOS_MTL_EST_ITRE_IEHF OSI_BIT(2) -#define EQOS_MTL_EST_ITRE_IEBE OSI_BIT(1) -#define EQOS_MTL_EST_ITRE_IECC OSI_BIT(0) -#endif /* !OSI_STRIPPED_LIB */ #if defined(MACSEC_SUPPORT) && !defined(OSI_STRIPPED_LIB) /* MACSEC Recommended value*/ #define EQOS_MTL_EST_CTOV_MACSEC_RECOMMEND 758U diff --git a/osi/core/frp.c b/osi/core/frp.c index 41075b5..dab09d1 100644 --- a/osi/core/frp.c +++ b/osi/core/frp.c @@ -23,7 +23,6 @@ #include "../osi/common/common.h" #include "frp.h" -#ifndef OSI_STRIPPED_LIB /** * @brief frp_entry_copy - Copy FRP entry * @@ -34,7 +33,7 @@ * */ static void frp_entry_copy(struct osi_core_frp_entry *dst, - struct osi_core_frp_entry *src) + struct osi_core_frp_entry *const src) { dst->frp_id = src->frp_id; dst->data.match_data = src->data.match_data; @@ -63,12 +62,13 @@ static void frp_entry_copy(struct osi_core_frp_entry *dst, * @retval -1 on failure. */ static nve32_t frp_entry_find(struct osi_core_priv_data *const osi_core, - nve32_t frp_id, - nveu8_t *start, - nveu8_t *no_entries) + nve32_t frp_id, + nveu8_t *start, + nveu8_t *no_entries) { nveu8_t count = OSI_NONE, found = OSI_NONE; struct osi_core_frp_entry *entry = OSI_NULL; + nve32_t ret = 0; /* Parse the FRP table for give frp_id */ for (count = 0U; count < osi_core->frp_cnt; count++) { @@ -81,17 +81,17 @@ static nve32_t frp_entry_find(struct osi_core_priv_data *const osi_core, found = OSI_ENABLE; } else { /* Increment entries */ - *no_entries = (nveu8_t) (*no_entries + 1U); + *no_entries = (nveu8_t)(*no_entries + 1U); } } } if (found == OSI_NONE) { /* No entry found return error */ - return -1; + ret = -1; } - return 0; + return ret; } /** @@ -106,33 +106,37 @@ static nve32_t frp_entry_find(struct osi_core_priv_data *const osi_core, * @retval No of FRP entries required. */ static nveu8_t frp_req_entries(nveu8_t offset, - nveu8_t match_length) + nveu8_t match_length) { nveu8_t req = 0U; + nveu8_t temp_match_length = match_length; - /* Validate for match_length */ - if ((match_length == OSI_NONE) || - (match_length > OSI_FRP_MATCH_DATA_MAX)) { + /* Validate for temp_match_length */ + if ((temp_match_length == OSI_NONE) || + (temp_match_length > OSI_FRP_MATCH_DATA_MAX)) { /* return zero */ - return req; + goto done; } /* Check does the given length can fit in fist entry */ - if (match_length <= (nveu8_t) FRP_OFFSET_BYTES(offset)) { + if (temp_match_length <= (nveu8_t)FRP_OFFSET_BYTES(offset)) { /* Require one entry */ - return 1U; + req = 1U; + goto done; } /* Initialize req as 1U and decrement length by FRP_OFFSET_BYTES */ req = 1U; - match_length = (nveu8_t) (match_length - (nveu8_t) FRP_OFFSET_BYTES(offset)); - if ((match_length / FRP_MD_SIZE) < OSI_FRP_MATCH_DATA_MAX) { - req = (nveu8_t) (req + (match_length / FRP_MD_SIZE)); - if ((match_length % FRP_MD_SIZE) != OSI_NONE) { + temp_match_length = (nveu8_t)(temp_match_length - + (nveu8_t)FRP_OFFSET_BYTES(offset)); + if ((temp_match_length / FRP_MD_SIZE) < OSI_FRP_MATCH_DATA_MAX) { + req = (nveu8_t)(req + (temp_match_length / FRP_MD_SIZE)); + if ((temp_match_length % FRP_MD_SIZE) != OSI_NONE) { /* Need one more entry */ - req = (nveu8_t) (req + 1U); + req = (nveu8_t)(req + 1U); } } +done: return req; } @@ -217,14 +221,14 @@ static void frp_entry_mode_parse(nveu8_t filter_mode, * @retval -1 on failure. */ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, - nve32_t frp_id, - nveu8_t pos, - nveu8_t *const match, - nveu8_t length, - nveu8_t offset, - nveu8_t filter_mode, - nve32_t next_frp_id, - nveu32_t dma_sel) + nve32_t frp_id, + nveu8_t pos, + nveu8_t *const match, + nveu8_t length, + nveu8_t offset, + nveu8_t filter_mode, + nve32_t next_frp_id, + nveu32_t dma_sel) { struct osi_core_frp_entry *entry = OSI_NULL; struct osi_core_frp_data *data = OSI_NULL; @@ -233,13 +237,16 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, nveu8_t fo_t = 0U; nveu8_t fp_t = 0U; nveu8_t i = 0U, j = 0U, md_pos = 0U; + nveu8_t temp_pos = pos; + nve32_t ret; /* Validate length */ if (length > OSI_FRP_MATCH_DATA_MAX) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_OUTOFBOUND, "Invalid match length\n", length); - return -1; + ret = -1; + goto done; } /* Validate filter_mode */ @@ -247,7 +254,8 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid filter mode argment\n", filter_mode); - return -1; + ret = -1; + goto done; } /* Validate offset */ @@ -255,17 +263,19 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid offset value\n", offset); - return -1; + ret = -1; + goto done; } /* Check for avilable space */ req_entries = frp_req_entries(offset, length); if ((req_entries >= OSI_FRP_MAX_ENTRY) || - ((req_entries + pos) >= OSI_FRP_MAX_ENTRY)) { + ((req_entries + temp_pos) >= OSI_FRP_MAX_ENTRY)) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "No space to update FRP ID\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Validate next_frp_id index ok_index */ @@ -275,7 +285,7 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "No Link FRP ID index found\n", OSI_NONE); - i = (nveu8_t) next_frp_id; + i = (nveu8_t)next_frp_id; } ok_index = i; } @@ -286,7 +296,7 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, md_pos = 0U; for (i = 0U; i < req_entries; i++) { /* Get FRP entry*/ - entry = &osi_core->frp_table[pos]; + entry = &osi_core->frp_table[temp_pos]; data = &entry->data; /* Fill FRP ID */ @@ -324,10 +334,10 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, data->next_ins_ctrl = OSI_ENABLE; /* Init next FRP entry */ - pos++; + temp_pos++; fo_t++; fp_t = OSI_NONE; - data->ok_index = pos; + data->ok_index = temp_pos; } else { data->next_ins_ctrl = OSI_DISABLE; data->ok_index = OSI_DISABLE; @@ -342,7 +352,9 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, data->ok_index = ok_index; } - return 0; + ret = 0; +done: + return ret; } /** @@ -356,9 +368,9 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ static nve32_t frp_hw_write(struct osi_core_priv_data *const osi_core, - struct core_ops *ops_p) + struct core_ops *const ops_p) { - nve32_t ret = -1, tmp = -1; + nve32_t ret, tmp; struct osi_core_frp_entry *entry; nveu32_t frp_cnt = osi_core->frp_cnt, i = OSI_NONE; @@ -411,10 +423,10 @@ hw_write_enable_frp: * @retval -1 on failure. */ static nve32_t frp_add_proto(struct osi_core_priv_data *const osi_core, - struct osi_core_frp_cmd *const cmd, - nveu8_t *pos) + struct osi_core_frp_cmd *const cmd, + nveu8_t *pos) { - nve32_t ret = -1, proto_oki = -1; + nve32_t ret, proto_oki; nveu8_t proto_entry = OSI_DISABLE; nveu8_t req = 0U; nveu8_t proto_match[FRP_PROTO_LENGTH]; @@ -463,16 +475,18 @@ static nve32_t frp_add_proto(struct osi_core_priv_data *const osi_core, /* Check and Add protocol FRP entire */ if (proto_entry == OSI_ENABLE) { /* Check for space */ - req = (nveu8_t) (frp_req_entries(cmd->offset, cmd->match_length) + 1U); + req = (nveu8_t)(frp_req_entries(cmd->offset, cmd->match_length) + 1U); if (*pos > (OSI_FRP_MAX_ENTRY - req)) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail add FRP protocol entry\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Add protocol FRP entire */ - proto_oki = *pos + 1; + proto_oki = (nve32_t)*pos; + proto_oki += 1; ret = frp_entry_add(osi_core, cmd->frp_id, *pos, proto_match, proto_lendth, proto_offset, OSI_FRP_MODE_LINK, @@ -481,14 +495,16 @@ static nve32_t frp_add_proto(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail add FRP protocol entry\n", OSI_NONE); - return ret; + goto done; } /* Increment pos value */ - *pos = (nveu8_t) (*pos + 1U); + *pos = (nveu8_t)(*pos + (nveu8_t)1); } - return 0; + ret = 0; +done: + return ret; } /** @@ -496,12 +512,10 @@ static nve32_t frp_add_proto(struct osi_core_priv_data *const osi_core, * * Algorithm: Parse give FRP command match type and update it's offset. * - * @param[in] osi_core: OSI core private data structure. * @param[in] cmd: OSI FRP command structure. * */ -static void frp_parse_mtype(OSI_UNUSED struct osi_core_priv_data *const osi_core, - struct osi_core_frp_cmd *const cmd) +static void frp_parse_mtype(struct osi_core_frp_cmd *const cmd) { nveu8_t offset; nveu8_t match_type = cmd->match_type; @@ -556,10 +570,10 @@ static void frp_parse_mtype(OSI_UNUSED struct osi_core_priv_data *const osi_core * @retval -1 on failure. */ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core, - struct core_ops *ops_p, - struct osi_core_frp_cmd *const cmd) + struct core_ops *ops_p, + struct osi_core_frp_cmd *const cmd) { - nve32_t ret = -1; + nve32_t ret; nveu8_t i = 0U, pos = 0U, count = 0U; nve32_t frp_id = cmd->frp_id; nveu32_t frp_cnt = osi_core->frp_cnt; @@ -569,7 +583,8 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "No FRP entries in the table\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Find the FRP entry */ @@ -577,7 +592,8 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "No FRP entry found to delete\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Validate pos and count */ @@ -585,7 +601,8 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Invalid FRP entry index\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Update the frp_table entry */ @@ -593,7 +610,7 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core, (sizeof(struct osi_core_frp_entry) * count)); /* Move in FRP table entries by count */ - for (i = (nveu8_t) (pos + count); i <= frp_cnt; i++) { + for (i = (nveu8_t)(pos + count); i <= frp_cnt; i++) { frp_entry_copy(&osi_core->frp_table[pos], &osi_core->frp_table[i]); pos++; @@ -610,6 +627,7 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core, /* Update the frp_cnt entry */ osi_core->frp_cnt = (frp_cnt - count); +done: return ret; } @@ -625,10 +643,10 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ static nve32_t frp_update(struct osi_core_priv_data *const osi_core, - struct core_ops *ops_p, - struct osi_core_frp_cmd *const cmd) + struct core_ops *ops_p, + struct osi_core_frp_cmd *const cmd) { - nve32_t ret = -1; + nve32_t ret; nveu8_t pos = 0U, count = 0U, req = 0U; nve32_t frp_id = cmd->frp_id; @@ -637,11 +655,12 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "No FRP entry found\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Parse match type and update command offset */ - frp_parse_mtype(osi_core, cmd); + frp_parse_mtype(cmd); /* Calculate the required FRP entries for Update Command. */ req = frp_req_entries(cmd->offset, cmd->match_length); @@ -663,7 +682,8 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Old and New required FRP entries mismatch\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Process and update FRP Command Protocal Entry */ @@ -672,7 +692,7 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to parse match type\n", OSI_NONE); - return ret; + goto done; } /* Update FRP entries */ @@ -684,7 +704,7 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to update FRP entry\n", OSI_NONE); - return ret; + goto done; } /* Write FRP Table into HW */ @@ -695,6 +715,7 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core, OSI_NONE); } +done: return ret; } @@ -710,10 +731,10 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ static nve32_t frp_add(struct osi_core_priv_data *const osi_core, - struct core_ops *ops_p, - struct osi_core_frp_cmd *const cmd) + struct core_ops *ops_p, + struct osi_core_frp_cmd *const cmd) { - nve32_t ret = -1; + nve32_t ret; nveu8_t pos = 0U, count = 0U; nve32_t frp_id = cmd->frp_id; nveu32_t nve = osi_core->frp_cnt; @@ -723,7 +744,8 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_OUTOFBOUND, "FRP etries are full\n", nve); - return -1; + ret = -1; + goto done; } /* Check the FRP entry already exists */ @@ -732,11 +754,12 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "FRP entry already exists\n", OSI_NONE); - return -1; + ret = -1; + goto done; } /* Parse match type and update command offset */ - frp_parse_mtype(osi_core, cmd); + frp_parse_mtype(cmd); /* Process and add FRP Command Protocal Entry */ ret = frp_add_proto(osi_core, cmd, (nveu8_t *)&nve); @@ -744,7 +767,7 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to parse match type\n", OSI_NONE); - return ret; + goto done; } /* Add Match data FRP Entry */ @@ -756,7 +779,7 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to add FRP entry\n", nve); - return ret; + goto done; } osi_core->frp_cnt = nve + frp_req_entries(cmd->offset, cmd->match_length); @@ -769,6 +792,7 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core, OSI_NONE); } +done: return ret; } @@ -784,8 +808,8 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ nve32_t setup_frp(struct osi_core_priv_data *const osi_core, - struct core_ops *ops_p, - struct osi_core_frp_cmd *const cmd) + struct core_ops *ops_p, + struct osi_core_frp_cmd *const cmd) { nve32_t ret = -1; @@ -835,4 +859,3 @@ void init_frp(struct osi_core_priv_data *const osi_core) osi_memset(osi_core->frp_table, 0U, (sizeof(struct osi_core_frp_entry) * OSI_FRP_MAX_ENTRY)); } -#endif /* !OSI_STRIPPED_LIB */ diff --git a/osi/core/frp.h b/osi/core/frp.h index b8525e3..aefdb10 100644 --- a/osi/core/frp.h +++ b/osi/core/frp.h @@ -23,7 +23,6 @@ #ifndef FRP_H #define FRP_H -#ifndef OSI_STRIPPED_LIB #include #include #include "core_local.h" @@ -66,8 +65,8 @@ * @retval -1 on failure. */ nve32_t setup_frp(struct osi_core_priv_data *const osi_core, - struct core_ops *ops_p, - struct osi_core_frp_cmd *const cmd); + struct core_ops *ops_p, + struct osi_core_frp_cmd *const cmd); /** * @brief init_frp - Init the FRP Instruction Table. @@ -81,6 +80,5 @@ nve32_t setup_frp(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ void init_frp(struct osi_core_priv_data *const osi_core); -#endif /* !OSI_STRIPPED_LIB */ #endif /* FRP_H */ diff --git a/osi/core/ivc_core.c b/osi/core/ivc_core.c index c0023cd..aec2d6e 100644 --- a/osi/core/ivc_core.c +++ b/osi/core/ivc_core.c @@ -69,11 +69,14 @@ static nve32_t ivc_handle_ioctl(struct osi_core_priv_data *osi_core, if (data->cmd == OSI_CMD_READ_MMC) { msg.status = osi_memcpy((void *)&osi_core->mmc, - (void *)&msg.data.mmc, - sizeof(struct osi_mmc_counters)); + (void *)&msg.data.mmc, + sizeof(struct osi_mmc_counters)); + msg.status = osi_memcpy((void *)&osi_core->tsn_stats, + (void *)&msg.data.eth_stats.tsn_s, + sizeof(struct osi_tsn_stats)); } else { msg.status = osi_memcpy((void *)data, - (void *)&msg.data.ioctl_data, + (void *)&msg.data.ioctl_data, sizeof(struct osi_ioctl)); } return ret; @@ -217,13 +220,13 @@ static nve32_t ivc_macsec_dbg_events_config( ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { - goto exit; + goto done; } msg.status = osi_memcpy((void *)dbg_buf_config, (void *)&msg.data.dbg_buf_config, sizeof(struct osi_macsec_dbg_buf_config)); -exit: +done: return ret; } @@ -253,13 +256,13 @@ static nve32_t ivc_macsec_dbg_buf_config( ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { - goto exit; + goto done; } msg.status = osi_memcpy((void *)dbg_buf_config, (void *) &msg.data.dbg_buf_config, sizeof(struct osi_macsec_dbg_buf_config)); -exit: +done: return ret; } #endif /* DEBUG_MACSEC */ @@ -362,11 +365,11 @@ static nve32_t ivc_macsec_config(struct osi_core_priv_data *const osi_core, ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { - goto exit; + goto done; } *kt_idx = msg.data.macsec_cfg.kt_idx; -exit: +done: return ret; } @@ -505,13 +508,13 @@ static nve32_t ivc_macsec_lut_config(struct osi_core_priv_data *const osi_core, ret = osi_core->osd_ops.ivc_send(osi_core, &msg, sizeof(msg)); if (ret != 0) { - goto exit; + goto done; } msg.status = osi_memcpy((void *)lut_config, (void *)&msg.data.lut_config, sizeof(struct osi_macsec_lut_config)); -exit: +done: return ret; } diff --git a/osi/core/mgbe_core.c b/osi/core/mgbe_core.c index 77950c4..f3100e3 100644 --- a/osi/core/mgbe_core.c +++ b/osi/core/mgbe_core.c @@ -47,7 +47,7 @@ * @retval Queue size that need to be programmed. */ static nveu32_t mgbe_calculate_per_queue_fifo(nveu32_t fifo_size, - nveu32_t queue_count) + nveu32_t queue_count) { nveu32_t q_fifo_size = 0; /* calculated fifo size per queue */ nveu32_t p_fifo = 0; /* per queue fifo size program value */ @@ -159,9 +159,9 @@ static nve32_t mgbe_poll_for_mac_acrtl(struct osi_core_priv_data *osi_core) * @retval -1 on failure. */ static nve32_t mgbe_mac_indir_addr_write(struct osi_core_priv_data *osi_core, - nveu32_t mc_no, - nveu32_t addr_offset, - nveu32_t value) + nveu32_t mc_no, + nveu32_t addr_offset, + nveu32_t value) { void *base = osi_core->base; nveu32_t addr = 0; @@ -217,9 +217,9 @@ static nve32_t mgbe_mac_indir_addr_write(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t mgbe_mac_indir_addr_read(struct osi_core_priv_data *osi_core, - nveu32_t mc_no, - nveu32_t addr_offset, - nveu32_t *value) + nveu32_t mc_no, + nveu32_t addr_offset, + nveu32_t *value) { void *base = osi_core->base; nveu32_t addr = 0; @@ -274,7 +274,7 @@ static nve32_t mgbe_mac_indir_addr_read(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t mgbe_filter_args_validate(struct osi_core_priv_data *const osi_core, - const struct osi_filter *filter) + const struct osi_filter *filter) { nveu32_t idx = filter->index; nveu32_t dma_routing_enable = filter->dma_routing; @@ -511,9 +511,9 @@ static nve32_t mgbe_poll_for_l3l4crtl(struct osi_core_priv_data *osi_core) * @retval -1 on failure. */ static nve32_t mgbe_l3l4_filter_write(struct osi_core_priv_data *osi_core, - nveu32_t filter_no, - nveu32_t filter_type, - nveu32_t value) + nveu32_t filter_no, + nveu32_t filter_type, + nveu32_t value) { void *base = osi_core->base; nveu32_t addr = 0; @@ -573,9 +573,9 @@ static nve32_t mgbe_l3l4_filter_write(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t mgbe_l3l4_filter_read(struct osi_core_priv_data *osi_core, - nveu32_t filter_no, - nveu32_t filter_type, - nveu32_t *value) + nveu32_t filter_no, + nveu32_t filter_type, + nveu32_t *value) { void *base = osi_core->base; nveu32_t addr = 0; @@ -687,6 +687,7 @@ static nve32_t mgbe_update_ip4_addr(struct osi_core_priv_data *const osi_core, return ret; } + #ifndef OSI_STRIPPED_LIB /** * @brief mgbe_update_ip6_addr - add ipv6 address in register @@ -844,9 +845,9 @@ static nve32_t mgbe_update_l4_port_no(struct osi_core_priv_data *osi_core, * @retval updated nveu32_t value param */ static inline nveu32_t mgbe_set_dcs(struct osi_core_priv_data *osi_core, - nveu32_t value, - nveu32_t dma_routing_enable, - nveu32_t dma_chan) + nveu32_t value, + nveu32_t dma_routing_enable, + nveu32_t dma_chan) { if ((dma_routing_enable == OSI_ENABLE) && (dma_chan < OSI_MGBE_MAX_NUM_CHANS) && (osi_core->dcs_en == @@ -1104,13 +1105,13 @@ static nve32_t mgbe_config_l3_filters(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t mgbe_config_l4_filters(struct osi_core_priv_data *const osi_core, - const nveu32_t filter_no, - const nveu32_t enb_dis, - const nveu32_t tcp_udp_match, - const nveu32_t src_dst_port_match, - const nveu32_t perfect_inverse_match, - const nveu32_t dma_routing_enable, - const nveu32_t dma_chan) + const nveu32_t filter_no, + const nveu32_t enb_dis, + const nveu32_t tcp_udp_match, + const nveu32_t src_dst_port_match, + const nveu32_t perfect_inverse_match, + const nveu32_t dma_routing_enable, + const nveu32_t dma_chan) { nveu32_t value = 0U; nve32_t ret = 0; @@ -1310,8 +1311,8 @@ static nve32_t mgbe_config_vlan_filtering(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t mgbe_config_ptp_rxq(struct osi_core_priv_data *const osi_core, - const nveu32_t rxq_idx, - const nveu32_t enable) + const nveu32_t rxq_idx, + const nveu32_t enable) { nveu8_t *base = osi_core->base; nveu32_t value = 0U; @@ -1435,8 +1436,8 @@ static nve32_t mgbe_config_mac_loopback(struct osi_core_priv_data *const osi_cor * @retval -1 on failure. */ static nve32_t mgbe_config_arp_offload(struct osi_core_priv_data *const osi_core, - const nveu32_t enable, - const nveu8_t *ip_addr) + const nveu32_t enable, + const nveu8_t *ip_addr) { nveu32_t mac_rmcr; nveu32_t val; @@ -1466,6 +1467,7 @@ static nve32_t mgbe_config_arp_offload(struct osi_core_priv_data *const osi_core return 0; } +#endif /* !OSI_STRIPPED_LIB */ /** * @brief mgbe_config_frp - Enable/Disale RX Flexible Receive Parser in HW @@ -1484,17 +1486,18 @@ static nve32_t mgbe_config_arp_offload(struct osi_core_priv_data *const osi_core * @retval -1 on failure. */ static nve32_t mgbe_config_frp(struct osi_core_priv_data *const osi_core, - const nveu32_t enabled) + const nveu32_t enabled) { nveu8_t *base = osi_core->base; nveu32_t op_mode = 0U, val = 0U; - nve32_t ret = -1; + nve32_t ret = 0; if ((enabled != OSI_ENABLE) && (enabled != OSI_DISABLE)) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid enable input\n", enabled); - return -1; + ret = -1; + goto done; } op_mode = osi_readla(osi_core, base + MGBE_MTL_OP_MODE); @@ -1515,7 +1518,8 @@ static nve32_t mgbe_config_frp(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to enable FRP\n", val); - return -1; + ret = -1; + goto done; } /* Enable FRP Interrupts in MTL_RXP_Interrupt_Control_Status */ @@ -1542,7 +1546,8 @@ static nve32_t mgbe_config_frp(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to disable FRP\n", val); - return -1; + ret = -1; + goto done; } /* Disable FRP Interrupts in MTL_RXP_Interrupt_Control_Status */ @@ -1554,7 +1559,8 @@ static nve32_t mgbe_config_frp(struct osi_core_priv_data *const osi_core, osi_writela(osi_core, val, base + MGBE_MTL_RXP_INTR_CS); } - return 0; +done: + return ret; } /** @@ -1575,9 +1581,9 @@ static nve32_t mgbe_config_frp(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ static nve32_t mgbe_frp_write(struct osi_core_priv_data *osi_core, - nveu32_t acc_sel, - nveu32_t addr, - nveu32_t data) + nveu32_t acc_sel, + nveu32_t addr, + nveu32_t data) { nve32_t ret = 0; nveu8_t *base = osi_core->base; @@ -1587,7 +1593,8 @@ static nve32_t mgbe_frp_write(struct osi_core_priv_data *osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid acc_sel argment\n", acc_sel); - return -1; + ret = -1; + goto done; } /* Wait for ready */ @@ -1602,7 +1609,8 @@ static nve32_t mgbe_frp_write(struct osi_core_priv_data *osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to write\n", val); - return -1; + ret = -1; + goto done; } /* Write data into MTL_RXP_Indirect_Acc_Data */ @@ -1639,9 +1647,10 @@ static nve32_t mgbe_frp_write(struct osi_core_priv_data *osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, "Fail to write\n", val); - return -1; + ret = -1; } +done: return ret; } @@ -1660,8 +1669,8 @@ static nve32_t mgbe_frp_write(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t mgbe_update_frp_entry(struct osi_core_priv_data *const osi_core, - const nveu32_t pos, - struct osi_core_frp_data *const data) + const nveu32_t pos, + struct osi_core_frp_data *const data) { nveu32_t val = 0U, tmp = 0U; nve32_t ret = -1; @@ -1671,7 +1680,8 @@ static nve32_t mgbe_update_frp_entry(struct osi_core_priv_data *const osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid FRP table entry\n", pos); - return -1; + ret = -1; + goto done; } /** Write Match Data into IE0 **/ @@ -1679,7 +1689,8 @@ static nve32_t mgbe_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = mgbe_frp_write(osi_core, OSI_DISABLE, MGBE_MTL_FRP_IE0(pos), val); if (ret < 0) { /* Match Data Write fail */ - return -1; + ret = -1; + goto done; } /** Write Match Enable into IE1 **/ @@ -1687,7 +1698,8 @@ static nve32_t mgbe_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = mgbe_frp_write(osi_core, OSI_DISABLE, MGBE_MTL_FRP_IE1(pos), val); if (ret < 0) { /* Match Enable Write fail */ - return -1; + ret = -1; + goto done; } /** Write AF, RF, IM, NIC, FO and OKI into IE2 **/ @@ -1717,7 +1729,8 @@ static nve32_t mgbe_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = mgbe_frp_write(osi_core, OSI_DISABLE, MGBE_MTL_FRP_IE2(pos), val); if (ret < 0) { /* FRP IE2 Write fail */ - return -1; + ret = -1; + goto done; } /** Write DCH into IE3 **/ @@ -1725,9 +1738,10 @@ static nve32_t mgbe_update_frp_entry(struct osi_core_priv_data *const osi_core, ret = mgbe_frp_write(osi_core, OSI_DISABLE, MGBE_MTL_FRP_IE3(pos), val); if (ret < 0) { /* DCH Write fail */ - return -1; + ret = -1; } +done: return ret; } @@ -1745,17 +1759,19 @@ static nve32_t mgbe_update_frp_entry(struct osi_core_priv_data *const osi_core, * @retval -1 on failure. */ static nve32_t mgbe_update_frp_nve(struct osi_core_priv_data *const osi_core, - const nveu32_t nve) + const nveu32_t nve) { nveu32_t val; nveu8_t *base = osi_core->base; + nve32_t ret; /* Validate the NVE value */ if (nve >= OSI_FRP_MAX_ENTRY) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid NVE value\n", nve); - return -1; + ret = -1; + goto done; } /* Update NVE and NPE in MTL_RXP_Control_Status register */ @@ -1767,9 +1783,11 @@ static nve32_t mgbe_update_frp_nve(struct osi_core_priv_data *const osi_core, val |= ((nve << MGBE_MTL_RXP_CS_NPE_SHIFT) & MGBE_MTL_RXP_CS_NPE); osi_writela(osi_core, val, base + MGBE_MTL_RXP_CS); - return 0; + ret = 0; + +done: + return ret; } -#endif /* !OSI_STRIPPED_LIB */ /** * @brief update_rfa_rfd - Update RFD and RSA values @@ -1888,9 +1906,9 @@ static void update_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value) * @retval -1 on failure. */ static nve32_t mgbe_configure_mtl_queue(nveu32_t qinx, - struct osi_core_priv_data *osi_core, - nveu32_t tx_fifo, - nveu32_t rx_fifo) + struct osi_core_priv_data *osi_core, + nveu32_t tx_fifo, + nveu32_t rx_fifo) { nveu32_t value = 0; nve32_t ret = 0; @@ -2002,9 +2020,9 @@ end: * @retval -1 on failure. */ static nve32_t mgbe_rss_write_reg(struct osi_core_priv_data *osi_core, - nveu32_t idx, - nveu32_t value, - nveu32_t is_key) + nveu32_t idx, + nveu32_t value, + nveu32_t is_key) { nveu8_t *addr = (nveu8_t *)osi_core->base; nveu32_t retry = 100; @@ -2118,7 +2136,7 @@ static nve32_t mgbe_config_rss(struct osi_core_priv_data *osi_core) * @retval -1 on failure. */ static nve32_t mgbe_config_flow_control(struct osi_core_priv_data *const osi_core, - const nveu32_t flw_ctrl) + const nveu32_t flw_ctrl) { nveu32_t val; void *addr = osi_core->base; @@ -2188,7 +2206,7 @@ static nve32_t mgbe_config_flow_control(struct osi_core_priv_data *const osi_cor * @retval -1 on failure */ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core, - const nveu32_t enable) + const nveu32_t enable) { nveu32_t value = 0U; nve32_t ret = 0; @@ -2643,195 +2661,6 @@ static void mgbe_core_backup_init(struct osi_core_priv_data *const osi_core) /* TODO: Add wrapper register backup */ } - -/** - * @brief mgbe_enable_mtl_interrupts - Enable MTL interrupts - * - * Algorithm: enable MTL interrupts for EST - * - * @param[in] osi_core: OSI core private data structure. - * - * @note MAC should be init and started. see osi_start_mac() - */ -static inline void mgbe_enable_mtl_interrupts( - struct osi_core_priv_data *osi_core) -{ - nveu32_t mtl_est_ir = OSI_DISABLE; - - mtl_est_ir = osi_readla(osi_core, (nveu8_t *) - osi_core->base + MGBE_MTL_EST_ITRE); - /* enable only MTL interrupt realted to - * Constant Gate Control Error - * Head-Of-Line Blocking due to Scheduling - * Head-Of-Line Blocking due to Frame Size - * BTR Error - * Switch to S/W owned list Complete - */ - mtl_est_ir |= (MGBE_MTL_EST_ITRE_CGCE | MGBE_MTL_EST_ITRE_IEHS | - MGBE_MTL_EST_ITRE_IEHF | MGBE_MTL_EST_ITRE_IEBE | - MGBE_MTL_EST_ITRE_IECC); - osi_writela(osi_core, mtl_est_ir, - (nveu8_t *)osi_core->base + MGBE_MTL_EST_ITRE); -} - -/** - * @brief mgbe_enable_fpe_interrupts - Enable MTL interrupts - * - * Algorithm: enable FPE interrupts - * - * @param[in] osi_core: OSI core private data structure. - * - * @note MAC should be init and started. see osi_start_mac() - */ -static inline void mgbe_enable_fpe_interrupts( - struct osi_core_priv_data *osi_core) -{ - nveu32_t value = OSI_DISABLE; - - /* Read MAC IER Register and enable Frame Preemption Interrupt - * Enable */ - value = osi_readla(osi_core, (nveu8_t *) - osi_core->base + MGBE_MAC_IER); - value |= MGBE_IMR_FPEIE; - osi_writela(osi_core, value, (nveu8_t *) - osi_core->base + MGBE_MAC_IER); -} - -/** - * @brief mgbe_save_gcl_params - save GCL configs in local core structure - * - * @param[in] osi_core: OSI core private data structure. - * - * @note MAC should be init and started. see osi_start_mac() - */ -static inline void mgbe_save_gcl_params(struct osi_core_priv_data *osi_core) -{ - struct core_local *l_core = (struct core_local *)osi_core; - nveu32_t gcl_widhth[4] = {0, OSI_MAX_24BITS, OSI_MAX_28BITS, - OSI_MAX_32BITS}; - nveu32_t gcl_ti_mask[4] = {0, OSI_MASK_16BITS, OSI_MASK_20BITS, - OSI_MASK_24BITS}; - nveu32_t gcl_depthth[6] = {0, OSI_GCL_SIZE_64, OSI_GCL_SIZE_128, - OSI_GCL_SIZE_256, OSI_GCL_SIZE_512, - OSI_GCL_SIZE_1024}; - - if ((osi_core->hw_feature->gcl_width == 0U) || - (osi_core->hw_feature->gcl_width > 3U)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "Wrong HW feature GCL width\n", - (nveul64_t)osi_core->hw_feature->gcl_width); - } else { - l_core->gcl_width_val = - gcl_widhth[osi_core->hw_feature->gcl_width]; - l_core->ti_mask = gcl_ti_mask[osi_core->hw_feature->gcl_width]; - } - - if ((osi_core->hw_feature->gcl_depth == 0U) || - (osi_core->hw_feature->gcl_depth > 5U)) { - /* Do Nothing */ - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "Wrong HW feature GCL depth\n", - (nveul64_t)osi_core->hw_feature->gcl_depth); - } else { - l_core->gcl_dep = gcl_depthth[osi_core->hw_feature->gcl_depth]; - } -} - -/** - * @brief mgbe_tsn_init - initialize TSN feature - * - * Algorithm: - * 1) If hardware support EST, - * a) Set default EST configuration - * b) Set enable interrupts - * 2) If hardware supports FPE - * a) Set default FPE configuration - * b) enable interrupts - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] est_sel: EST HW support present or not - * @param[in] fpe_sel: FPE HW support present or not - * - * @note MAC should be init and started. see osi_start_mac() - */ -static void mgbe_tsn_init(struct osi_core_priv_data *osi_core, - nveu32_t est_sel, nveu32_t fpe_sel) -{ - nveu32_t val = 0x0; - nveu32_t temp = 0U; - - if (est_sel == OSI_ENABLE) { - mgbe_save_gcl_params(osi_core); - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MTL_EST_CONTROL); - - /* - * PTOV PTP clock period * 6 - * dual-port RAM based asynchronous FIFO controllers or - * Single-port RAM based synchronous FIFO controllers - * CTOV 96 x Tx clock period - * : - * : - * set other default value - */ - val &= ~MGBE_MTL_EST_CONTROL_PTOV; - temp = MGBE_MTL_EST_PTOV_RECOMMEND; - temp = temp << MGBE_MTL_EST_CONTROL_PTOV_SHIFT; - val |= temp; - - val &= ~MGBE_MTL_EST_CONTROL_CTOV; - temp = MGBE_MTL_EST_CTOV_RECOMMEND; - temp = temp << MGBE_MTL_EST_CONTROL_CTOV_SHIFT; - val |= temp; - - /*Loop Count to report Scheduling Error*/ - val &= ~MGBE_MTL_EST_CONTROL_LCSE; - val |= MGBE_MTL_EST_CONTROL_LCSE_VAL; - - val &= ~MGBE_MTL_EST_CONTROL_DDBF; - val |= MGBE_MTL_EST_CONTROL_DDBF; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MTL_EST_CONTROL); - - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MTL_EST_OVERHEAD); - val &= ~MGBE_MTL_EST_OVERHEAD_OVHD; - /* As per hardware programming info */ - val |= MGBE_MTL_EST_OVERHEAD_RECOMMEND; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MTL_EST_OVERHEAD); - - mgbe_enable_mtl_interrupts(osi_core); - } - - if (fpe_sel == OSI_ENABLE) { - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MAC_RQC1R); - val &= ~MGBE_MAC_RQC1R_RQ; - temp = osi_core->residual_queue; - temp = temp << MGBE_MAC_RQC1R_RQ_SHIFT; - temp = (temp & MGBE_MAC_RQC1R_RQ); - val |= temp; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MAC_RQC1R); - - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MAC_RQC4R); - val &= ~MGBE_MAC_RQC4R_PMCBCQ; - temp = osi_core->residual_queue; - temp = temp << MGBE_MAC_RQC4R_PMCBCQ_SHIFT; - temp = (temp & MGBE_MAC_RQC4R_PMCBCQ); - val |= temp; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MAC_RQC4R); - - mgbe_enable_fpe_interrupts(osi_core); - } - - /* CBS setting for TC or TXQ for default configuration - user application should use IOCTL to set CBS as per requirement - */ -} #endif /* !OSI_STRIPPED_LIB */ /** @@ -2918,8 +2747,8 @@ static nve32_t mgbe_dma_chan_to_vmirq_map(struct osi_core_priv_data *osi_core) * @retval -1 on failure. */ static nve32_t mgbe_core_init(struct osi_core_priv_data *const osi_core, - nveu32_t tx_fifo_size, - nveu32_t rx_fifo_size) + nveu32_t tx_fifo_size, + nveu32_t rx_fifo_size) { nve32_t ret = 0; nveu32_t qinx = 0; @@ -2995,18 +2824,15 @@ static nve32_t mgbe_core_init(struct osi_core_priv_data *const osi_core, /* configure MGBE DMA */ mgbe_configure_dma(osi_core); -#ifndef OSI_STRIPPED_LIB /* tsn initialization */ if (osi_core->hw_feature != OSI_NULL) { - mgbe_tsn_init(osi_core, osi_core->hw_feature->est_sel, - osi_core->hw_feature->fpe_sel); + hw_tsn_init(osi_core, osi_core->hw_feature->est_sel, + osi_core->hw_feature->fpe_sel); } -#endif /* !OSI_STRIPPED_LIB */ return mgbe_dma_chan_to_vmirq_map(osi_core); } -#ifndef OSI_STRIPPED_LIB /** * @brief mgbe_handle_mac_fpe_intrs * @@ -3060,7 +2886,6 @@ static void mgbe_handle_mac_fpe_intrs(struct osi_core_priv_data *osi_core) osi_writela(osi_core, val, (nveu8_t *) osi_core->base + MGBE_MAC_FPE_CTS); } -#endif /* !OSI_STRIPPED_LIB */ /** * @brief Get free timestamp index from TS array by validating in_use param @@ -3100,8 +2925,8 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core, { struct core_local *l_core = (struct core_local *)osi_core; nveu32_t mac_isr = 0; -#ifndef OSI_STRIPPED_LIB nveu32_t mac_ier = 0; +#ifndef OSI_STRIPPED_LIB nveu32_t tx_errors = 0; #endif /* !OSI_STRIPPED_LIB */ @@ -3124,7 +2949,6 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core, } } -#ifndef OSI_STRIPPED_LIB mac_ier = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_IER); if (((mac_isr & MGBE_MAC_IMR_FPEIS) == MGBE_MAC_IMR_FPEIS) && @@ -3132,6 +2956,7 @@ static void mgbe_handle_mac_intrs(struct osi_core_priv_data *osi_core, mgbe_handle_mac_fpe_intrs(osi_core); } +#ifndef OSI_STRIPPED_LIB /* Check for any MAC Transmit Error Status Interrupt */ if ((mac_isr & MGBE_IMR_TXESIE) == MGBE_IMR_TXESIE) { /* Check for the type of Tx error by reading MAC_Rx_Tx_Status @@ -3268,6 +3093,7 @@ static inline void mgbe_update_dma_sr_stats(struct osi_core_priv_data *osi_core, osi_update_stats_counter(val, 1U); } } +#endif /* !OSI_STRIPPED_LIB */ /** * @brief mgbe_set_avb_algorithm - Set TxQ/TC avb config @@ -3305,7 +3131,7 @@ static nve32_t mgbe_set_avb_algorithm( OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "avb structure is NULL\n", 0ULL); - return ret; + goto done; } /* queue index in range */ @@ -3313,7 +3139,7 @@ static nve32_t mgbe_set_avb_algorithm( OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid Queue index\n", (nveul64_t)avb->qindex); - return ret; + goto done; } /* queue oper_mode in range check*/ @@ -3321,7 +3147,7 @@ static nve32_t mgbe_set_avb_algorithm( OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid Queue mode\n", (nveul64_t)avb->qindex); - return ret; + goto done; } /* Validate algo is valid */ @@ -3329,7 +3155,7 @@ static nve32_t mgbe_set_avb_algorithm( OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid Algo input\n", (nveul64_t)avb->tcindex); - return ret; + goto done; } /* can't set AVB mode for queue 0 */ @@ -3337,7 +3163,7 @@ static nve32_t mgbe_set_avb_algorithm( OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_OPNOTSUPP, "Not allowed to set AVB for Q0\n", (nveul64_t)avb->qindex); - return ret; + goto done; } /* TC index range check */ @@ -3345,7 +3171,7 @@ static nve32_t mgbe_set_avb_algorithm( OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Invalid Queue TC mapping\n", (nveul64_t)avb->tcindex); - return ret; + goto done; } qinx = avb->qindex; @@ -3427,7 +3253,10 @@ static nve32_t mgbe_set_avb_algorithm( MGBE_MTL_CHX_TX_OP_MODE(qinx)); } - return 0; + ret = 0; + +done: + return ret; } /** @@ -3454,7 +3283,7 @@ static nve32_t mgbe_set_avb_algorithm( * @retval -1 on failure. */ static nve32_t mgbe_get_avb_algorithm(struct osi_core_priv_data *const osi_core, - struct osi_core_avb_algorithm *const avb) + struct osi_core_avb_algorithm *const avb) { nveu32_t value; nve32_t ret = -1; @@ -3547,7 +3376,7 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core, nveu32_t frm_err = 0U; nveu32_t temp = 0U; nveu32_t i = 0; - unsigned long stat_val = 0U; + nveul64_t stat_val = 0U; nveu32_t value = 0U; nveu32_t qstatus = 0U; nveu32_t qinx = 0U; @@ -3555,12 +3384,12 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core, /* Check for all MTL queues */ for (i = 0; i < osi_core->num_mtl_queues; i++) { qinx = osi_core->mtl_queues[i]; - if (mtl_isr & OSI_BIT(qinx)) { + if ((mtl_isr & OSI_BIT(qinx)) == OSI_BIT(qinx)) { /* check if Q has underflow error */ qstatus = osi_readl((nveu8_t *)osi_core->base + MGBE_MTL_QINT_STATUS(qinx)); /* Transmit Queue Underflow Interrupt Status */ - if (qstatus & MGBE_MTL_QINT_TXUNIFS) { + if ((qstatus & MGBE_MTL_QINT_TXUNIFS) == MGBE_MTL_QINT_TXUNIFS) { #ifndef OSI_STRIPPED_LIB osi_core->pkt_err_stats.mgbe_tx_underflow_err = osi_update_stats_counter( @@ -3575,7 +3404,7 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core, } if ((mtl_isr & MGBE_MTL_IS_ESTIS) != MGBE_MTL_IS_ESTIS) { - return; + goto done; } val = osi_readla(osi_core, @@ -3586,7 +3415,7 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core, /* return if interrupt is not related to EST */ if (val == OSI_DISABLE) { - return; + goto done; } /* increase counter write 1 back will clear */ @@ -3684,11 +3513,12 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core, osi_writela(osi_core, val, (nveu8_t *)osi_core->base + MGBE_MTL_EST_STATUS); - mtl_isr &= ~MGBE_MTL_IS_ESTIS; - osi_writela(osi_core, mtl_isr, (nveu8_t *)osi_core->base + - MGBE_MTL_INTR_STATUS); +done: + return; } +#ifndef OSI_STRIPPED_LIB + /** * @brief mgbe_config_ptp_offload - Enable/Disable PTP offload * @@ -3705,7 +3535,7 @@ static void mgbe_handle_mtl_intrs(struct osi_core_priv_data *osi_core, */ static nve32_t mgbe_config_ptp_offload(struct osi_core_priv_data *const osi_core, - struct osi_pto_config *const pto_config) + struct osi_pto_config *const pto_config) { nveu8_t *addr = (nveu8_t *)osi_core->base; nve32_t ret = 0; @@ -3929,10 +3759,8 @@ static void mgbe_handle_common_intr(struct osi_core_priv_data *const osi_core) nveu32_t i = 0; nveu32_t dma_sr = 0; nveu32_t dma_ier = 0; -#ifndef OSI_STRIPPED_LIB nveu32_t mtl_isr = 0; nveu32_t val = 0; -#endif /* !OSI_STRIPPED_LIB */ #ifdef HSI_SUPPORT if (osi_core->hsi.enabled == OSI_ENABLE) { @@ -3941,7 +3769,7 @@ static void mgbe_handle_common_intr(struct osi_core_priv_data *const osi_core) #endif dma_isr = osi_readla(osi_core, (nveu8_t *)base + MGBE_DMA_ISR); if (dma_isr == OSI_NONE) { - return; + goto done; } //FIXME Need to check how we can get the DMA channel here instead of @@ -3985,7 +3813,6 @@ static void mgbe_handle_common_intr(struct osi_core_priv_data *const osi_core) mgbe_handle_mac_intrs(osi_core, dma_isr); -#ifndef OSI_STRIPPED_LIB /* Handle MTL inerrupts */ mtl_isr = osi_readla(osi_core, (nveu8_t *)base + MGBE_MTL_INTR_STATUS); @@ -4009,7 +3836,9 @@ static void mgbe_handle_common_intr(struct osi_core_priv_data *const osi_core) MGBE_MTL_RXP_INTR_CS_FOOVIS | MGBE_MTL_RXP_INTR_CS_PDRFIS); osi_writela(osi_core, val, (nveu8_t *)base + MGBE_MTL_RXP_INTR_CS); -#endif /* !OSI_STRIPPED_LIB */ + +done: + return; } /** @@ -4274,9 +4103,9 @@ static inline nve32_t mgbe_restore_registers( * @retval -1 on failure. */ static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *osi_core, - nveu32_t phyaddr, - nveu32_t phyreg, - nveu16_t phydata) + nveu32_t phyaddr, + nveu32_t phyreg, + nveu16_t phydata) { nve32_t ret = 0; nveu32_t reg; @@ -4346,8 +4175,8 @@ static nve32_t mgbe_write_phy_reg(struct osi_core_priv_data *osi_core, * @retval -1 on failure. */ static nve32_t mgbe_read_phy_reg(struct osi_core_priv_data *osi_core, - nveu32_t phyaddr, - nveu32_t phyreg) + nveu32_t phyaddr, + nveu32_t phyreg) { nveu32_t reg; nveu32_t data; @@ -4405,340 +4234,6 @@ static nve32_t mgbe_read_phy_reg(struct osi_core_priv_data *osi_core, } #ifndef OSI_STRIPPED_LIB -/** - * @brief mgbe_hw_est_write - indirect write the GCL to Software own list - * (SWOL) - * - * @param[in] base: MAC base IOVA address. - * @param[in] addr_val: Address offset for indirect write. - * @param[in] data: Data to be written at offset. - * @param[in] gcla: Gate Control List Address, 0 for ETS register. - * 1 for GCL memory. - * - * @note MAC should be init and started. see osi_start_mac() - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t mgbe_hw_est_write(struct osi_core_priv_data *osi_core, - nveu32_t addr_val, nveu32_t data, - nveu32_t gcla) -{ - nve32_t retry = 1000; - nveu32_t val = 0x0; - - osi_writela(osi_core, data, (nveu8_t *)osi_core->base + - MGBE_MTL_EST_DATA); - - val &= ~MGBE_MTL_EST_ADDR_MASK; - val |= (gcla == 1U) ? 0x0U : MGBE_MTL_EST_GCRR; - val |= MGBE_MTL_EST_SRWO; - val |= addr_val; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MTL_EST_GCL_CONTROL); - - while (--retry > 0) { - osi_core->osd_ops.udelay(OSI_DELAY_1US); - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MTL_EST_GCL_CONTROL); - if ((val & MGBE_MTL_EST_SRWO) == MGBE_MTL_EST_SRWO) { - continue; - } - - break; - } - - if (((val & MGBE_MTL_EST_ERR0) == MGBE_MTL_EST_ERR0) || - (retry <= 0)) { - return -1; - } - - return 0; -} - -/** - * @brief mgbe_hw_config_est - Read Setting for GCL from input and update - * registers. - * - * Algorithm: - * 1) Write TER, LLR and EST control register - * 2) Update GCL to sw own GCL (MTL_EST_Status bit SWOL will tell which is - * owned by SW) and store which GCL is in use currently in sw. - * 3) TODO set DBGB and DBGM for debugging - * 4) EST_data and GCRR to 1, update entry sno in ADDR and put data at - * est_gcl_data enable GCL MTL_EST_SSWL and wait for self clear or use - * SWLC in MTL_EST_Status. Please note new GCL will be pushed for each entry. - * 5) Configure btr. Update btr based on current time (current time - * should be updated based on PTP by this time) - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] est: EST configuration input argument. - * - * @note MAC should be init and started. see osi_start_mac() - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t mgbe_hw_config_est(struct osi_core_priv_data *const osi_core, - struct osi_est_config *const est) -{ - nveu32_t btr[2] = {0}; - nveu32_t val = 0x0; - void *base = osi_core->base; - nveu32_t i; - nve32_t ret = 0; - nveu32_t addr = 0x0; - - if ((osi_core->hw_feature != OSI_NULL) && - (osi_core->hw_feature->est_sel == OSI_DISABLE)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "EST not supported in HW\n", 0ULL); - return -1; - } - - if (est->en_dis == OSI_DISABLE) { - val = osi_readla(osi_core, (nveu8_t *) - base + MGBE_MTL_EST_CONTROL); - val &= ~MGBE_MTL_EST_EEST; - osi_writela(osi_core, val, (nveu8_t *) - base + MGBE_MTL_EST_CONTROL); - - return 0; - } - - btr[0] = est->btr[0]; - btr[1] = est->btr[1]; - if ((btr[0] == 0U) && (btr[1] == 0U)) { - common_get_systime_from_mac(osi_core->base, - osi_core->mac, - &btr[1], &btr[0]); - } - - if (gcl_validate(osi_core, est, btr, osi_core->mac) < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL validation failed\n", 0LL); - return -1; - } - - ret = mgbe_hw_est_write(osi_core, MGBE_MTL_EST_CTR_LOW, est->ctr[0], 0); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL CTR[0] failed\n", 0LL); - return ret; - } - /* check for est->ctr[i] not more than FF, TODO as per hw config - * parameter we can have max 0x3 as this value in sec */ - est->ctr[1] &= MGBE_MTL_EST_CTR_HIGH_MAX; - ret = mgbe_hw_est_write(osi_core, MGBE_MTL_EST_CTR_HIGH, est->ctr[1], 0); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL CTR[1] failed\n", 0LL); - return ret; - } - - ret = mgbe_hw_est_write(osi_core, MGBE_MTL_EST_TER, est->ter, 0); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL TER failed\n", 0LL); - return ret; - } - - ret = mgbe_hw_est_write(osi_core, MGBE_MTL_EST_LLR, est->llr, 0); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL LLR failed\n", 0LL); - return ret; - } - - /* Write GCL table */ - for (i = 0U; i < est->llr; i++) { - addr = i; - addr = addr << MGBE_MTL_EST_ADDR_SHIFT; - addr &= MGBE_MTL_EST_ADDR_MASK; - ret = mgbe_hw_est_write(osi_core, addr, est->gcl[i], 1); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL enties write failed\n", - (nveul64_t)i); - return ret; - } - } - - /* Write parameters */ - ret = mgbe_hw_est_write(osi_core, MGBE_MTL_EST_BTR_LOW, - btr[0] + est->btr_offset[0], OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL BTR[0] failed\n", - (nveul64_t)(btr[0] + - est->btr_offset[0])); - return ret; - } - - ret = mgbe_hw_est_write(osi_core, MGBE_MTL_EST_BTR_HIGH, - btr[1] + est->btr_offset[1], OSI_DISABLE); - if (ret < 0) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "GCL BTR[1] failed\n", - (nveul64_t)(btr[1] + - est->btr_offset[1])); - return ret; - } - - val = osi_readla(osi_core, (nveu8_t *) - base + MGBE_MTL_EST_CONTROL); - /* Store table */ - val |= MGBE_MTL_EST_SSWL; - val |= MGBE_MTL_EST_EEST; - val |= MGBE_MTL_EST_QHLBF; - osi_writela(osi_core, val, (nveu8_t *) - base + MGBE_MTL_EST_CONTROL); - - return ret; -} - -/** - * @brief mgbe_hw_config_fep - Read Setting for preemption and express for TC - * and update registers. - * - * Algorithm: - * 1) Check for TC enable and TC has masked for setting to preemptable. - * 2) update FPE control status register - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] fpe: FPE configuration input argument. - * - * @note MAC should be init and started. see osi_start_mac() - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t mgbe_hw_config_fpe(struct osi_core_priv_data *const osi_core, - struct osi_fpe_config *const fpe) -{ - nveu32_t i = 0U; - nveu32_t val = 0U; - nveu32_t temp = 0U, temp1 = 0U; - nveu32_t temp_shift = 0U; - nve32_t ret = 0; - - if ((osi_core->hw_feature != OSI_NULL) && - (osi_core->hw_feature->fpe_sel == OSI_DISABLE)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "FPE not supported in HW\n", 0ULL); - return -1; - } - -#ifdef MACSEC_SUPPORT - osi_lock_irq_enabled(&osi_core->macsec_fpe_lock); - /* MACSEC and FPE cannot coexist on MGBE refer bug 3484034 */ - if (osi_core->is_macsec_enabled == OSI_ENABLE) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "FPE and MACSEC cannot co-exist\n", 0ULL); - ret = -1; - goto exit; - } -#endif /* MACSEC_SUPPORT */ - - osi_core->fpe_ready = OSI_DISABLE; - - if (((fpe->tx_queue_preemption_enable << MGBE_MTL_FPE_CTS_PEC_SHIFT) & - MGBE_MTL_FPE_CTS_PEC) == OSI_DISABLE) { - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MTL_FPE_CTS); - val &= ~MGBE_MTL_FPE_CTS_PEC; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MTL_FPE_CTS); - - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MAC_FPE_CTS); - val &= ~MGBE_MAC_FPE_CTS_EFPE; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MAC_FPE_CTS); - -#ifdef MACSEC_SUPPORT - osi_core->is_fpe_enabled = OSI_DISABLE; -#endif /* MACSEC_SUPPORT */ - ret = 0; - goto exit; - } - - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + - MGBE_MTL_FPE_CTS); - val &= ~MGBE_MTL_FPE_CTS_PEC; - for (i = 0U; i < OSI_MAX_TC_NUM; i++) { - /* max 8 bit for this structure fot TC/TXQ. Set the TC for express or - * preemption. Default is express for a TC. DWCXG_NUM_TC = 8 */ - temp = OSI_BIT(i); - if ((fpe->tx_queue_preemption_enable & temp) == temp) { - temp_shift = i; - temp_shift += MGBE_MTL_FPE_CTS_PEC_SHIFT; - /* set queue for preemtable */ - if (temp_shift < MGBE_MTL_FPE_CTS_PEC_MAX_SHIFT) { - temp1 = OSI_ENABLE; - temp1 = temp1 << temp_shift; - val |= temp1; - } else { - /* Do nothing */ - } - } - } - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + - MGBE_MTL_FPE_CTS); - - if ((fpe->rq == 0x0U) || (fpe->rq >= OSI_MGBE_MAX_NUM_CHANS)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "FPE init failed due to wrong RQ\n", fpe->rq); - ret = -1; - goto exit; - } - - val = osi_readla(osi_core, (nveu8_t *) - osi_core->base + MGBE_MAC_RQC1R); - val &= ~MGBE_MAC_RQC1R_RQ; - temp = fpe->rq; - temp = temp << MGBE_MAC_RQC1R_RQ_SHIFT; - temp = (temp & MGBE_MAC_RQC1R_RQ); - val |= temp; - osi_core->residual_queue = fpe->rq; - osi_writela(osi_core, val, (nveu8_t *) - osi_core->base + MGBE_MAC_RQC1R); - - val = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_RQC4R); - val &= ~MGBE_MAC_RQC4R_PMCBCQ; - temp = fpe->rq; - temp = temp << MGBE_MAC_RQC4R_PMCBCQ_SHIFT; - temp = (temp & MGBE_MAC_RQC4R_PMCBCQ); - val |= temp; - osi_writela(osi_core, val, (nveu8_t *)osi_core->base + MGBE_MAC_RQC4R); - - /* initiate SVER for SMD-V and SMD-R */ - val = osi_readla(osi_core, (nveu8_t *) - osi_core->base + MGBE_MTL_FPE_CTS); - val |= MGBE_MAC_FPE_CTS_SVER; - osi_writela(osi_core, val, (nveu8_t *) - osi_core->base + MGBE_MAC_FPE_CTS); - - val = osi_readla(osi_core, (nveu8_t *) - osi_core->base + MGBE_MTL_FPE_ADV); - val &= ~MGBE_MTL_FPE_ADV_HADV_MASK; - //(minimum_fragment_size +IPG/EIPG + Preamble) *.8 ~98ns for10G - val |= MGBE_MTL_FPE_ADV_HADV_VAL; - osi_writela(osi_core, val, (nveu8_t *) - osi_core->base + MGBE_MTL_FPE_ADV); - -#ifdef MACSEC_SUPPORT - osi_core->is_fpe_enabled = OSI_ENABLE; -#endif /* MACSEC_SUPPORT */ - -exit: - -#ifdef MACSEC_SUPPORT - osi_unlock_irq_enabled(&osi_core->macsec_fpe_lock); -#endif /* MACSEC_SUPPORT */ - return ret; -} - /** * @brief mgbe_disable_tx_lpi - Helper function to disable Tx LPI. * @@ -4866,7 +4361,7 @@ static void mgbe_configure_eee(struct osi_core_priv_data *const osi_core, #endif /* !OSI_STRIPPED_LIB */ static nve32_t mgbe_get_hw_features(struct osi_core_priv_data *const osi_core, - struct osi_hw_features *hw_feat) + struct osi_hw_features *hw_feat) { nveu8_t *base = (nveu8_t *)osi_core->base; nveu32_t mac_hfr0 = 0; @@ -5086,9 +4581,9 @@ static inline nve32_t mgbe_poll_for_update_ts_complete( * @retval -1 on failure. */ static nve32_t mgbe_adjust_mactime(struct osi_core_priv_data *osi_core, - nveu32_t sec, nveu32_t nsec, - nveu32_t add_sub, - nveu32_t one_nsec_accuracy) + nveu32_t sec, nveu32_t nsec, + nveu32_t add_sub, + nveu32_t one_nsec_accuracy) { void *addr = osi_core->base; nveu32_t mac_tcr; @@ -5169,7 +4664,7 @@ static nve32_t mgbe_adjust_mactime(struct osi_core_priv_data *osi_core, * @retval 0 */ static nveu32_t mgbe_read_reg(struct osi_core_priv_data *const osi_core, - const nve32_t reg) + const nve32_t reg) { return osi_readla(osi_core, (nveu8_t *)osi_core->base + reg); } @@ -5354,7 +4849,7 @@ static void mgbe_config_for_macsec(struct osi_core_priv_data *const osi_core, if ((enable != OSI_ENABLE) && (enable != OSI_DISABLE)) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "Failed to config MGBE per MACSEC\n", 0ULL); - goto exit; + goto done; } /* stop MAC Tx */ mgbe_config_mac_tx(osi_core, OSI_DISABLE); @@ -5416,7 +4911,7 @@ static void mgbe_config_for_macsec(struct osi_core_priv_data *const osi_core, 0ULL); } } -exit: +done: return; } #endif /* MACSEC_SUPPORT */ @@ -5439,6 +4934,11 @@ void mgbe_init_core_ops(struct core_ops *ops) ops->update_ip4_addr = mgbe_update_ip4_addr; ops->read_reg = mgbe_read_reg; ops->write_reg = mgbe_write_reg; + ops->set_avb_algorithm = mgbe_set_avb_algorithm; + ops->get_avb_algorithm = mgbe_get_avb_algorithm; + ops->config_frp = mgbe_config_frp; + ops->update_frp_entry = mgbe_update_frp_entry; + ops->update_frp_nve = mgbe_update_frp_nve; #ifdef MACSEC_SUPPORT ops->read_macsec_reg = mgbe_read_macsec_reg; ops->write_macsec_reg = mgbe_write_macsec_reg; @@ -5456,8 +4956,6 @@ void mgbe_init_core_ops(struct core_ops *ops) ops->config_arp_offload = mgbe_config_arp_offload; ops->config_ptp_offload = mgbe_config_ptp_offload; ops->validate_regs = mgbe_validate_core_regs; - ops->set_avb_algorithm = mgbe_set_avb_algorithm; - ops->get_avb_algorithm = mgbe_get_avb_algorithm, ops->config_vlan_filtering = mgbe_config_vlan_filtering; ops->reset_mmc = mgbe_reset_mmc; ops->configure_eee = mgbe_configure_eee; @@ -5465,11 +4963,6 @@ void mgbe_init_core_ops(struct core_ops *ops) ops->restore_registers = mgbe_restore_registers; ops->set_mdc_clk_rate = mgbe_set_mdc_clk_rate; ops->config_mac_loopback = mgbe_config_mac_loopback; - ops->hw_config_est = mgbe_hw_config_est; - ops->hw_config_fpe = mgbe_hw_config_fpe; - ops->config_frp = mgbe_config_frp; - ops->update_frp_entry = mgbe_update_frp_entry; - ops->update_frp_nve = mgbe_update_frp_nve; ops->config_rss = mgbe_config_rss; ops->config_ptp_rxq = mgbe_config_ptp_rxq; #endif /* !OSI_STRIPPED_LIB */ diff --git a/osi/core/mgbe_core.h b/osi/core/mgbe_core.h index 8a2a498..90de78e 100644 --- a/osi/core/mgbe_core.h +++ b/osi/core/mgbe_core.h @@ -26,6 +26,7 @@ #ifndef OSI_STRIPPED_LIB #define MGBE_MAC_PFR 0x0008 #define MGBE_MAC_RX_FLW_CTRL 0x0090 +#define MGBE_MAC_RQC2R 0x00A8 #define MGBE_MAC_QX_TX_FLW_CTRL(x) ((0x0004U * (x)) + 0x0070U) #define MGBE_MAC_ARPPA 0x0C10 #define MGBE_MAC_LPI_CSR 0x00D0 @@ -34,84 +35,31 @@ #define MGBE_MAC_RSS_CTRL 0x0C80 #define MGBE_MAC_RSS_ADDR 0x0C88 #define MGBE_MAC_RSS_DATA 0x0C8C +#define MGBE_MAC_STSR 0x0D08 +#define MGBE_MAC_STNSR 0x0D0C #define MGBE_MAC_PTO_CR 0x0DC0 #define MGBE_MAC_PIDR0 0x0DC4 #define MGBE_MAC_PIDR1 0x0DC8 #define MGBE_MAC_PIDR2 0x0DCC #define MGBE_MAC_PMTCSR 0x00C0 #define MGBE_MAC_HTR_REG(x) ((0x0004U * (x)) + 0x0010U) -#define MGBE_MTL_EST_CONTROL 0x1050 -#define MGBE_MTL_EST_OVERHEAD 0x1054 -#define MGBE_MTL_EST_STATUS 0x1058 -#define MGBE_MTL_EST_SCH_ERR 0x1060 -#define MGBE_MTL_EST_FRMS_ERR 0x1064 -#define MGBE_MTL_EST_ITRE 0x1070 -#define MGBE_MTL_EST_GCL_CONTROL 0x1080 -#define MGBE_MTL_EST_DATA 0x1084 -#define MGBE_MAC_STSR 0x0D08 -#define MGBE_MAC_STNSR 0x0D0C #define MGBE_MAC_RX_TX_STS 0x00B8 -#define MGBE_MAC_RQC4R 0x0094 -#define MGBE_MAC_RQC2R 0x00A8 -#define MGBE_MAC_FPE_CTS 0x0280 -#define MGBE_MTL_TCQ_ETS_HCR(x) ((0x0080U * (x)) + 0x1120U) -#define MGBE_MTL_TCQ_ETS_LCR(x) ((0x0080U * (x)) + 0x1124U) -#define MGBE_MTL_TCQ_ETS_SSCR(x) ((0x0080U * (x)) + 0x111CU) #define MGBE_WRAP_AXI_ASID0_CTRL 0x8400 #define MGBE_WRAP_AXI_ASID1_CTRL 0x8404 #define MGBE_WRAP_AXI_ASID2_CTRL 0x8408 -#define MGBE_MTL_RXP_CS 0x10A0 -#define MGBE_MTL_RXP_INTR_CS 0x10A4 -#define MGBE_MTL_RXP_IND_CS 0x10B0 -#define MGBE_MTL_RXP_IND_DATA 0x10B4 -#define MGBE_MTL_QINT_STATUS(x) ((0x0080U * (x)) + 0x1174U) -#define MGBE_MTL_OP_MODE 0x1000 -#define MGBE_MTL_INTR_STATUS 0x1020 -#define MGBE_MTL_FPE_CTS 0x1090 -#define MGBE_MTL_FPE_ADV 0x1094 - #define MGBE_MAC_PFR_VTFE OSI_BIT(16) #define MGBE_MAC_PFR_IPFE OSI_BIT(20) #define MGBE_MAC_PFR_IPFE_SHIFT 20 -#define MGBE_MTL_TCQ_ETS_CR_AVALG_SHIFT 0U -#define MGBE_MTL_QINT_TXUNIFS OSI_BIT(0) -#define MGBE_MTL_TX_OP_MODE_Q2TCMAP (OSI_BIT(10) | OSI_BIT(9) |\ - OSI_BIT(8)) -#define MGBE_MTL_TX_OP_MODE_Q2TCMAP_SHIFT 8U -#define MGBE_MTL_TX_OP_MODE_TXQEN (OSI_BIT(3) | OSI_BIT(2)) -#define MGBE_MTL_TX_OP_MODE_TXQEN_SHIFT 2U #define MGBE_SID_VAL1(x) (((x) << 24U) |\ ((x) << 16U) |\ ((x) << 8U) |\ (x)) #define MGBE_SID_VAL2(x) (((x) << 8U) |\ (x)) - -#define MGBE_MTL_TCQ_ETS_CR_CC OSI_BIT(3) -#define MGBE_MTL_TCQ_ETS_CR_CC_SHIFT 3U -#define MGBE_MTL_TCQ_ETS_QW_ISCQW_MASK 0x001FFFFFU -#define MGBE_MTL_TCQ_ETS_SSCR_SSC_MASK 0x0000FFFFU -#define MGBE_MTL_TCQ_ETS_HCR_HC_MASK 0x1FFFFFFFU -#define MGBE_MTL_TCQ_ETS_LCR_LC_MASK 0x1FFFFFFFU - #define MGBE0_SID ((nveu32_t)0x6U) #define MGBE1_SID ((nveu32_t)0x49U) #define MGBE2_SID ((nveu32_t)0x4AU) #define MGBE3_SID ((nveu32_t)0x4BU) -#define MGBE_8PTP_CYCLE 26U -#define MGBE_DMA_ISR_MTLIS OSI_BIT(16) -#define MGBE_IMR_FPEIE OSI_BIT(15) -#define MGBE_MAC_EXT_CNF_EIPG 0x1U -#define MGBE_MAC_EXT_CNF_EIPG_MASK 0x7FU -#define MGBE_MAC_RQC4R_PMCBCQ (OSI_BIT(27) | OSI_BIT(26) | \ - OSI_BIT(25) | OSI_BIT(24)) -#define MGBE_MAC_RQC4R_PMCBCQ_SHIFT 24U -#define MGBE_MAC_RX_FLW_CTRL_RFE OSI_BIT(0) -#define MGBE_MAC_STNSR_TSSS_MASK 0x7FFFFFFFU -#define MGBE_MAC_TCR_SNAPTYPSEL_SHIFT 16U -#define MGBE_MAC_TCR_TSENMACADDR OSI_BIT(18) -#define MGBE_MAC_TMCR_IPG_MASK 0x700U -#define MGBE_MAC_RQC1R_RQ_SHIFT 4U #define MGBE_MAC_PAUSE_TIME 0xFFFF0000U #define MGBE_MAC_PAUSE_TIME_MASK 0xFFFF0000U #define MGBE_MAC_TX_TJT OSI_BIT(0) @@ -130,83 +78,16 @@ /** @} */ #define MGBE_MAX_VLAN_FILTER 32U -/* EST controlOSI_BITmap */ -#define MGBE_MTL_EST_EEST OSI_BIT(0) -#define MGBE_MTL_EST_SSWL OSI_BIT(1) -#define MGBE_MTL_EST_QHLBF OSI_BIT(3) -/* EST GCL controlOSI_BITmap */ -#define MGBE_MTL_EST_ADDR_SHIFT 8 -#define MGBE_MTL_EST_ADDR_MASK (OSI_BIT(8) | OSI_BIT(9) | \ - OSI_BIT(10) | OSI_BIT(11) | \ - OSI_BIT(12) | OSI_BIT(13) | \ - OSI_BIT(14) | OSI_BIT(15) | \ - OSI_BIT(16) | OSI_BIT(17) | \ - OSI_BIT(18) | OSI_BIT(19)) -#define MGBE_MTL_EST_SRWO OSI_BIT(0) -#define MGBE_MTL_EST_GCRR OSI_BIT(2) -#define MGBE_MTL_EST_ERR0 OSI_BIT(20) -/*EST MTL interrupt STATUS and ERR*/ -#define MGBE_MTL_IS_ESTIS OSI_BIT(18) -/* MTL_EST_STATUS*/ -#define MGBE_MTL_EST_STATUS_CGCE OSI_BIT(4) -#define MGBE_MTL_EST_STATUS_HLBS OSI_BIT(3) -#define MGBE_MTL_EST_STATUS_HLBF OSI_BIT(2) -#define MGBE_MTL_EST_STATUS_BTRE OSI_BIT(1) -#define MGBE_MTL_EST_STATUS_SWLC OSI_BIT(0) -#define MGBE_MTL_EST_ITRE_CGCE OSI_BIT(4) -#define MGBE_MTL_EST_ITRE_IEHS OSI_BIT(3) -#define MGBE_MTL_EST_ITRE_IEHF OSI_BIT(2) -#define MGBE_MTL_EST_ITRE_IEBE OSI_BIT(1) -#define MGBE_MTL_EST_ITRE_IECC OSI_BIT(0) -/* EST GCRA addresses */ -#define MGBE_MTL_EST_BTR_LOW ((nveu32_t)0x0 << \ - MGBE_MTL_EST_ADDR_SHIFT) -#define MGBE_MTL_EST_BTR_HIGH ((nveu32_t)0x1 << \ - MGBE_MTL_EST_ADDR_SHIFT) -#define MGBE_MTL_EST_CTR_LOW ((nveu32_t)0x2 << \ - MGBE_MTL_EST_ADDR_SHIFT) -#define MGBE_MTL_EST_CTR_HIGH ((nveu32_t)0x3 << \ - MGBE_MTL_EST_ADDR_SHIFT) -#define MGBE_MTL_EST_CTR_HIGH_MAX 0xFFU -#define MGBE_MTL_EST_TER ((nveu32_t)0x4 << \ - MGBE_MTL_EST_ADDR_SHIFT) -#define MGBE_MTL_EST_LLR ((nveu32_t)0x5 << \ - MGBE_MTL_EST_ADDR_SHIFT) - -#define MGBE_MTL_EST_CONTROL_LCSE (OSI_BIT(7) | OSI_BIT(6)) -#define MGBE_MTL_EST_CONTROL_LCSE_VAL 0U -#define MGBE_MTL_EST_CONTROL_DDBF OSI_BIT(4) -#define MGBE_MTL_EST_OVERHEAD_OVHD (OSI_BIT(0) | OSI_BIT(1) | \ - OSI_BIT(2) | OSI_BIT(3) | \ - OSI_BIT(4) | OSI_BIT(5)) -#define MGBE_MTL_EST_OVERHEAD_RECOMMEND 56U - -#define MGBE_MAC_TX_PCE OSI_BIT(13) -/* MAC FPE control/statusOSI_BITmap */ -#define MGBE_MAC_FPE_CTS_EFPE OSI_BIT(0) -#define MGBE_MAC_FPE_CTS_TRSP OSI_BIT(19) -#define MGBE_MAC_FPE_CTS_TVER OSI_BIT(18) -#define MGBE_MAC_FPE_CTS_RVER OSI_BIT(16) -#define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1) -#define MGBE_MAC_FPE_CTS_SRSP OSI_BIT(2) -/* MTL_FPE_CTRL_STS */ -#define MGBE_MTL_FPE_CTS_PEC (OSI_BIT(8) | OSI_BIT(9) | \ - OSI_BIT(10) | OSI_BIT(11) | \ - OSI_BIT(12) | OSI_BIT(13) | \ - OSI_BIT(14) | OSI_BIT(15)) -#define MGBE_MTL_FPE_CTS_PEC_SHIFT 8U -#define MGBE_MTL_FPE_CTS_PEC_MAX_SHIFT 16U -/* MTL FPE adv registers */ -#define MGBE_MTL_FPE_ADV_HADV_MASK (0xFFFFU) -#define MGBE_MTL_FPE_ADV_HADV_VAL 100U - -#define MGBE_MAC_IMR_FPEIS OSI_BIT(16) #define MGBE_MAC_L3L4_CTR_L4DPIM0_SHIFT 21 #define MGBE_MAC_L3L4_CTR_L4PEN0 OSI_BIT(16) #define MGBE_MAC_L3L4_CTR_L4SPIM0_SHIFT 19 #define MGBE_MAC_L3_AD2R 0x6 #define MGBE_MAC_L3_AD3R 0x7 -#define MGBE_MAC_FPE_CTS_RRSP OSI_BIT(17) +#define MGBE_MAC_RX_FLW_CTRL_RFE OSI_BIT(0) +#define MGBE_MAC_STNSR_TSSS_MASK 0x7FFFFFFFU +#define MGBE_MAC_TCR_SNAPTYPSEL_SHIFT 16U +#define MGBE_MAC_TCR_TSENMACADDR OSI_BIT(18) +#define MGBE_MAC_TMCR_IPG_MASK 0x700U #define MGBE_MAC_RQC1R_PTPQ_SHIFT 24U #define MGBE_MAC_RQC1R_PTPQ (OSI_BIT(27) | OSI_BIT(26) | \ OSI_BIT(25) | OSI_BIT(24)) @@ -224,7 +105,7 @@ #define MGBE_MAC_RSS_ADDR_RSSIA_SHIFT 8U #define MGBE_MAC_RSS_ADDR_OB OSI_BIT(0) #define MGBE_MAC_RSS_ADDR_CT OSI_BIT(1) - +#define MGBE_MAC_TX_PCE OSI_BIT(13) /** * @addtogroup - MGBE-LPI LPI configuration macros * @@ -264,6 +145,95 @@ OSI_BIT(11) | OSI_BIT(10) | \ OSI_BIT(9) | OSI_BIT(8)) #define MGBE_MAC_PTO_CR_DN_SHIFT 8U +#define MGBE_DMA_CHX_STATUS_RPS OSI_BIT(8) +#define MGBE_DMA_CHX_STATUS_TPS OSI_BIT(1) +#define MGBE_DMA_CHX_STATUS_TBU OSI_BIT(2) +#define MGBE_DMA_CHX_STATUS_RBU OSI_BIT(7) +#define MGBE_DMA_CHX_STATUS_FBE OSI_BIT(12) + +#define MGBE_MAC_L4_ADDR 0x1 +#define MGBE_MAC_L4_ADDR_SP_MASK 0x0000FFFFU +#define MGBE_MAC_L4_ADDR_DP_MASK 0xFFFF0000U +#define MGBE_MAC_L4_ADDR_DP_SHIFT 16 +#define MGBE_MAC_LPI_CSR_LPITE OSI_BIT(20) +#define MGBE_MAC_LPI_CSR_LPITXA OSI_BIT(19) +#define MGBE_MAC_LPI_CSR_PLS OSI_BIT(17) +#define MGBE_MAC_LPI_CSR_LPIEN OSI_BIT(16) +#define MGBE_MAC_PFR_VTFE_SHIFT 16 +#define MGBE_MAC_PIDR_PID_MASK 0XFFFFU + +#endif /* !OSI_STRIPPED_LIB */ + +#define MGBE_MTL_EST_CONTROL 0x1050 +#define MGBE_MTL_EST_OVERHEAD 0x1054 +#define MGBE_MTL_EST_STATUS 0x1058 +#define MGBE_MTL_EST_SCH_ERR 0x1060 +#define MGBE_MTL_EST_FRMS_ERR 0x1064 +#define MGBE_MTL_EST_ITRE 0x1070 +#define MGBE_MTL_EST_GCL_CONTROL 0x1080 +#define MGBE_MTL_EST_DATA 0x1084 +#define MGBE_MAC_RQC4R 0x0094 +#define MGBE_MAC_FPE_CTS 0x0280 +#define MGBE_MTL_RXP_CS 0x10A0 +#define MGBE_MTL_RXP_INTR_CS 0x10A4 +#define MGBE_MTL_RXP_IND_CS 0x10B0 +#define MGBE_MTL_RXP_IND_DATA 0x10B4 + +#define MGBE_MTL_TCQ_ETS_HCR(x) ((0x0080U * (x)) + 0x1120U) +#define MGBE_MTL_TCQ_ETS_LCR(x) ((0x0080U * (x)) + 0x1124U) +#define MGBE_MTL_TCQ_ETS_SSCR(x) ((0x0080U * (x)) + 0x111CU) +#define MGBE_MTL_OP_MODE 0x1000 +#define MGBE_MTL_INTR_STATUS 0x1020 +#define MGBE_MTL_FPE_CTS 0x1090 +#define MGBE_MTL_FPE_ADV 0x1094 + +#define MGBE_MTL_QINT_STATUS(x) ((0x0080U * (x)) + 0x1174U) +#define MGBE_MTL_TCQ_ETS_CR_AVALG_SHIFT 0U +#define MGBE_MTL_QINT_TXUNIFS OSI_BIT(0) +#define MGBE_MTL_TX_OP_MODE_Q2TCMAP (OSI_BIT(10) | OSI_BIT(9) |\ + OSI_BIT(8)) +#define MGBE_MTL_TX_OP_MODE_Q2TCMAP_SHIFT 8U +#define MGBE_MTL_TX_OP_MODE_TXQEN (OSI_BIT(3) | OSI_BIT(2)) +#define MGBE_MTL_TX_OP_MODE_TXQEN_SHIFT 2U +#define MGBE_MTL_TCQ_ETS_CR_CC OSI_BIT(3) +#define MGBE_MTL_TCQ_ETS_CR_CC_SHIFT 3U +#define MGBE_MTL_TCQ_ETS_QW_ISCQW_MASK 0x001FFFFFU +#define MGBE_MTL_TCQ_ETS_SSCR_SSC_MASK 0x0000FFFFU +#define MGBE_MTL_TCQ_ETS_HCR_HC_MASK 0x1FFFFFFFU +#define MGBE_MTL_TCQ_ETS_LCR_LC_MASK 0x1FFFFFFFU + +#define MGBE_8PTP_CYCLE 26U +#define MGBE_DMA_ISR_MTLIS OSI_BIT(16) +#define MGBE_IMR_FPEIE OSI_BIT(15) +#ifndef OSI_STRIPPED_LIB +#define MGBE_MAC_EXT_CNF_EIPG 0x1U +#define MGBE_MAC_EXT_CNF_EIPG_MASK 0x7FU +#endif /* !OSI_STRIPPED_LIB */ +#define MGBE_MAC_RQC4R_PMCBCQ (OSI_BIT(27) | OSI_BIT(26) | \ + OSI_BIT(25) | OSI_BIT(24)) +#define MGBE_MAC_RQC4R_PMCBCQ_SHIFT 24U +#define MGBE_MAC_RQC1R_RQ_SHIFT 4U +#define MGBE_MTL_EST_EEST OSI_BIT(0) +/* EST GCL controlOSI_BITmap */ +#define MGBE_MTL_EST_ADDR_SHIFT 8 +/*EST MTL interrupt STATUS and ERR*/ +#define MGBE_MTL_IS_ESTIS OSI_BIT(18) +/* MTL_EST_STATUS*/ +#define MGBE_MTL_EST_STATUS_CGCE OSI_BIT(4) +#define MGBE_MTL_EST_STATUS_HLBS OSI_BIT(3) +#define MGBE_MTL_EST_STATUS_HLBF OSI_BIT(2) +#define MGBE_MTL_EST_STATUS_BTRE OSI_BIT(1) +#define MGBE_MTL_EST_STATUS_SWLC OSI_BIT(0) +/* MAC FPE control/statusOSI_BITmap */ +#define MGBE_MAC_FPE_CTS_EFPE OSI_BIT(0) +#define MGBE_MAC_FPE_CTS_TRSP OSI_BIT(19) +#define MGBE_MAC_FPE_CTS_TVER OSI_BIT(18) +#define MGBE_MAC_FPE_CTS_RVER OSI_BIT(16) +#define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1) +#define MGBE_MAC_FPE_CTS_SRSP OSI_BIT(2) +/* MTL FPE adv registers */ +#define MGBE_MAC_IMR_FPEIS OSI_BIT(16) +#define MGBE_MAC_FPE_CTS_RRSP OSI_BIT(17) /* MTL_EST_CONTROL */ #define MGBE_MTL_EST_CONTROL_PTOV (OSI_BIT(23) | OSI_BIT(24) | \ OSI_BIT(25) | OSI_BIT(26) | \ @@ -280,6 +250,8 @@ OSI_BIT(21) | OSI_BIT(22)) #define MGBE_MTL_EST_CONTROL_CTOV_SHIFT 11U #define MGBE_MTL_EST_CTOV_RECOMMEND 42U +#define MGBE_MAC_RQC1R_RQ (OSI_BIT(7) | OSI_BIT(6) | \ + OSI_BIT(5) | OSI_BIT(4)) /** * @addtogroup MGBE-MTL FRP Indirect Access register defines @@ -346,27 +318,6 @@ OSI_BIT(3) | OSI_BIT(2) | \ OSI_BIT(1) | OSI_BIT(0)) /** @} */ -#define MGBE_DMA_CHX_STATUS_RPS OSI_BIT(8) -#define MGBE_DMA_CHX_STATUS_TPS OSI_BIT(1) -#define MGBE_DMA_CHX_STATUS_TBU OSI_BIT(2) -#define MGBE_DMA_CHX_STATUS_RBU OSI_BIT(7) -#define MGBE_DMA_CHX_STATUS_FBE OSI_BIT(12) - -#define MGBE_MAC_L4_ADDR 0x1 -#define MGBE_MAC_L4_ADDR_SP_MASK 0x0000FFFFU -#define MGBE_MAC_L4_ADDR_DP_MASK 0xFFFF0000U -#define MGBE_MAC_L4_ADDR_DP_SHIFT 16 -#define MGBE_MAC_LPI_CSR_LPITE OSI_BIT(20) -#define MGBE_MAC_LPI_CSR_LPITXA OSI_BIT(19) -#define MGBE_MAC_LPI_CSR_PLS OSI_BIT(17) -#define MGBE_MAC_LPI_CSR_LPIEN OSI_BIT(16) -#define MGBE_MAC_RQC1R_RQ (OSI_BIT(7) | OSI_BIT(6) | \ - OSI_BIT(5) | OSI_BIT(4)) -#define MGBE_MAC_PFR_VTFE_SHIFT 16 -#define MGBE_MAC_PIDR_PID_MASK 0XFFFFU - - -#endif /* !OSI_STRIPPED_LIB */ /** * @addtogroup MGBE MTL queue ETS algorithm mode @@ -667,6 +618,31 @@ */ #define MGBE_MTL_EST_CTOV_MACSEC_RECOMMEND 295U #endif /* MACSEC_SUPPORT */ +#define MGBE_MTL_EST_CONTROL_LCSE (OSI_BIT(7) | OSI_BIT(6)) +#define MGBE_MTL_EST_CONTROL_LCSE_VAL 0U +#define MGBE_MTL_EST_CONTROL_DDBF OSI_BIT(4) +#define MGBE_MTL_EST_OVERHEAD_OVHD (OSI_BIT(0) | OSI_BIT(1) | \ + OSI_BIT(2) | OSI_BIT(3) | \ + OSI_BIT(4) | OSI_BIT(5)) +#define MGBE_MTL_EST_OVERHEAD_RECOMMEND 56U +/* EST GCL controlOSI_BITmap */ +#define MGBE_MTL_EST_ADDR_SHIFT 8 +/* EST GCRA addresses */ +#define MGBE_MTL_EST_BTR_LOW ((nveu32_t)0x0 << \ + MGBE_MTL_EST_ADDR_SHIFT) +#define MGBE_MTL_EST_BTR_HIGH ((nveu32_t)0x1 << \ + MGBE_MTL_EST_ADDR_SHIFT) +#define MGBE_MTL_EST_CTR_LOW ((nveu32_t)0x2 << \ + MGBE_MTL_EST_ADDR_SHIFT) +#define MGBE_MTL_EST_CTR_HIGH ((nveu32_t)0x3 << \ + MGBE_MTL_EST_ADDR_SHIFT) +#define MGBE_MTL_EST_TER ((nveu32_t)0x4 << \ + MGBE_MTL_EST_ADDR_SHIFT) +#define MGBE_MTL_EST_LLR ((nveu32_t)0x5 << \ + MGBE_MTL_EST_ADDR_SHIFT) +/*EST MTL interrupt STATUS and ERR*/ +#define MGBE_MTL_IS_ESTIS OSI_BIT(18) + #define MGBE_MAC_EXT_CNF_DDS OSI_BIT(7) /* TX timestamp */ #define MGBE_MAC_TSS_TXTSC OSI_BIT(15) diff --git a/osi/core/osi_hal.c b/osi/core/osi_hal.c index c8592fc..e2f657d 100644 --- a/osi/core/osi_hal.c +++ b/osi/core/osi_hal.c @@ -1036,57 +1036,6 @@ static nve32_t conf_eee(struct osi_core_priv_data *const osi_core, return 0; } -/** - * @brief configure_frp - Configure the FRP offload entry in the - * Instruction Table. - * - * @param[in] osi_core: OSI core private data structure. - * @param[in] cmd: FRP command data structure. - * - * @pre - * - MAC and PHY should be init and started. see osi_start_mac() - * - * @note - * Traceability Details: - * - * @note - * Classification: - * - Interrupt: No - * - Signal handler: No - * - Thread safe: No - * - Required Privileges: None - * - * @note - * API Group: - * - Initialization: No - * - Run time: Yes - * - De-initialization: No - * - * @retval 0 on success - * @retval -1 on failure. - */ -static nve32_t configure_frp(struct osi_core_priv_data *const osi_core, - struct osi_core_frp_cmd *const cmd) -{ - struct core_local *l_core = (struct core_local *)(void *)osi_core; - - if (cmd == OSI_NULL) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, - "Invalid argment\n", OSI_NONE); - return -1; - } - - /* Check for supported MAC version */ - if ((osi_core->mac == OSI_MAC_HW_EQOS) && - (osi_core->mac_ver < OSI_EQOS_MAC_5_10)) { - OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, - "MAC doesn't support FRP\n", OSI_NONE); - return -1; - } - - return setup_frp(osi_core, l_core->ops_p, cmd); -} - /** * @brief config_arp_offload - Configure ARP offload in MAC. * @@ -1187,6 +1136,63 @@ static nve32_t conf_mac_loopback(struct osi_core_priv_data *const osi_core, return l_core->ops_p->config_mac_loopback(osi_core, lb_mode); } +#endif /* !OSI_STRIPPED_LIB */ + +/** + * @brief configure_frp - Configure the FRP offload entry in the + * Instruction Table. + * + * @param[in] osi_core: OSI core private data structure. + * @param[in] cmd: FRP command data structure. + * + * @pre + * - MAC and PHY should be init and started. see osi_start_mac() + * + * @note + * Traceability Details: + * + * @note + * Classification: + * - Interrupt: No + * - Signal handler: No + * - Thread safe: No + * - Required Privileges: None + * + * @note + * API Group: + * - Initialization: No + * - Run time: Yes + * - De-initialization: No + * + * @retval 0 on success + * @retval -1 on failure. + */ +static nve32_t configure_frp(struct osi_core_priv_data *const osi_core, + struct osi_core_frp_cmd *const cmd) +{ + struct core_local *l_core = (struct core_local *)(void *)osi_core; + nve32_t ret; + + if (cmd == OSI_NULL) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, + "FRP command invalid\n", 0ULL); + ret = -1; + goto done; + } + + /* Check for supported MAC version */ + if ((osi_core->mac == OSI_MAC_HW_EQOS) && + (osi_core->mac_ver < OSI_EQOS_MAC_5_30)) { + OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL, + "MAC doesn't support FRP\n", OSI_NONE); + ret = -1; + goto done; + } + + ret = setup_frp(osi_core, l_core->ops_p, cmd); +done: + return ret; +} /** * @brief config_est - Read Setting for GCL from input and update @@ -1231,12 +1237,13 @@ static nve32_t conf_mac_loopback(struct osi_core_priv_data *const osi_core, static nve32_t config_est(struct osi_core_priv_data *osi_core, struct osi_est_config *est) { - struct core_local *l_core = (struct core_local *)(void *)osi_core; + nve32_t ret; if (est == OSI_NULL) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "EST data is NULL", 0ULL); - return -1; + ret = -1; + goto done; } if ((osi_core->flow_ctrl & OSI_FLOW_CTRL_TX) == @@ -1244,10 +1251,14 @@ static nve32_t config_est(struct osi_core_priv_data *osi_core, OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "TX Flow control enabled, please disable it", 0ULL); - return -1; + ret = -1; + goto done; } - return l_core->ops_p->hw_config_est(osi_core, est); + ret = hw_config_est(osi_core, est); + +done: + return ret; } /** @@ -1286,17 +1297,20 @@ static nve32_t config_est(struct osi_core_priv_data *osi_core, static nve32_t config_fpe(struct osi_core_priv_data *osi_core, struct osi_fpe_config *fpe) { - struct core_local *l_core = (struct core_local *)(void *)osi_core; + nve32_t ret; if (fpe == OSI_NULL) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "FPE data is NULL", 0ULL); - return -1; + ret = -1; + goto done; } - return l_core->ops_p->hw_config_fpe(osi_core, fpe); + ret = hw_config_fpe(osi_core, fpe); + +done: + return ret; } -#endif /* !OSI_STRIPPED_LIB */ /** * @brief Free stale timestamps for channel @@ -1645,6 +1659,14 @@ static void cfg_fc(struct core_local *l_core) l_core->cfg.flow_ctrl); } +static void cfg_eee(struct core_local *l_core) +{ + (void)conf_eee((struct osi_core_priv_data *)(void *)l_core, + l_core->cfg.tx_lpi_enabled, + l_core->cfg.tx_lpi_timer); +} +#endif /* !OSI_STRIPPED_LIB */ + static void cfg_avb(struct core_local *l_core) { nveu32_t i; @@ -1659,13 +1681,6 @@ static void cfg_avb(struct core_local *l_core) } } -static void cfg_eee(struct core_local *l_core) -{ - (void)conf_eee((struct osi_core_priv_data *)(void *)l_core, - l_core->cfg.tx_lpi_enabled, - l_core->cfg.tx_lpi_timer); -} - static void cfg_est(struct core_local *l_core) { (void)config_est((struct osi_core_priv_data *)(void *)l_core, @@ -1677,7 +1692,6 @@ static void cfg_fpe(struct core_local *l_core) (void)config_fpe((struct osi_core_priv_data *)(void *)l_core, &l_core->cfg.fpe); } -#endif /* !OSI_STRIPPED_LIB */ static void cfg_ptp(struct core_local *l_core) { @@ -1701,11 +1715,11 @@ static void apply_dynamic_cfg(struct osi_core_priv_data *osi_core) #ifndef OSI_STRIPPED_LIB [DYNAMIC_CFG_VLAN_IDX] = cfg_vlan, [DYNAMIC_CFG_FC_IDX] = cfg_fc, - [DYNAMIC_CFG_AVB_IDX] = cfg_avb, [DYNAMIC_CFG_EEE_IDX] = cfg_eee, +#endif /* !OSI_STRIPPED_LIB */ + [DYNAMIC_CFG_AVB_IDX] = cfg_avb, [DYNAMIC_CFG_EST_IDX] = cfg_est, [DYNAMIC_CFG_FPE_IDX] = cfg_fpe, -#endif /* !OSI_STRIPPED_LIB */ [DYNAMIC_CFG_PTP_IDX] = cfg_ptp }; nveu32_t flags = l_core->cfg.flags; @@ -1778,7 +1792,8 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core, #endif if (validate_args(osi_core, l_core) < 0) { - return ret; + ret = -1; + goto done; } ops_p = l_core->ops_p; @@ -1786,7 +1801,8 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core, if (data == OSI_NULL) { OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID, "CORE: Invalid argument\n", 0ULL); - return -1; + ret = -1; + goto done; } switch (data->cmd) { @@ -1839,21 +1855,6 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core, break; - case OSI_CMD_GET_AVB: - ret = ops_p->get_avb_algorithm(osi_core, &data->avb); - break; - - case OSI_CMD_SET_AVB: - ret = ops_p->set_avb_algorithm(osi_core, &data->avb); - if (ret == 0) { - (void)osi_memcpy(&l_core->cfg.avb[data->avb.qindex].avb_info, - &data->avb, sizeof(struct osi_core_avb_algorithm)); - l_core->cfg.avb[data->avb.qindex].used = OSI_ENABLE; - l_core->cfg.flags |= DYNAMIC_CFG_AVB; - } - - break; - case OSI_CMD_CONFIG_RX_CRC_CHECK: ret = ops_p->config_rx_crc_check(osi_core, data->arg1_u32); break; @@ -1900,8 +1901,21 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core, } break; - #endif /* !OSI_STRIPPED_LIB */ + case OSI_CMD_GET_AVB: + ret = ops_p->get_avb_algorithm(osi_core, &data->avb); + break; + + case OSI_CMD_SET_AVB: + ret = ops_p->set_avb_algorithm(osi_core, &data->avb); + if (ret == 0) { + (void)osi_memcpy(&l_core->cfg.avb[data->avb.qindex].avb_info, + &data->avb, sizeof(struct osi_core_avb_algorithm)); + l_core->cfg.avb[data->avb.qindex].used = OSI_ENABLE; + l_core->cfg.flags |= DYNAMIC_CFG_AVB; + } + break; + case OSI_CMD_CONFIG_FW_ERR: ret = hw_config_fw_err_pkts(osi_core, data->arg1_u32, data->arg2_u32); break; @@ -2161,14 +2175,15 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core, ret = rxq_route_config(osi_core, &data->rxq_route); break; - case OSI_CMD_CONFIG_FRP: - ret = configure_frp(osi_core, &data->frp_cmd); - break; - case OSI_CMD_CONFIG_RSS: ret = ops_p->config_rss(osi_core); break; +#endif /* !OSI_STRIPPED_LIB */ + case OSI_CMD_CONFIG_FRP: + ret = configure_frp(osi_core, &data->frp_cmd); + break; + case OSI_CMD_CONFIG_EST: ret = config_est(osi_core, &data->est); if (ret == 0) { @@ -2188,7 +2203,7 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core, } break; -#endif /* !OSI_STRIPPED_LIB */ + case OSI_CMD_READ_REG: ret = (nve32_t) ops_p->read_reg(osi_core, (nve32_t) data->arg1_u32); break; @@ -2278,6 +2293,7 @@ nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core, break; } +done: return ret; }