nv-tegra-mirror/nvethernetrm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/kernel/nvethernetrm.git synced 2025-12-22 17:34:29 +03:00
Code Issues Packages Projects Releases Wiki Activity

osi: eqos: Fix FRP entry update fail

Browse Source 
Issue:
FRP entry update command is getting
failed due to an invalid RXPI check
on EQOS IP.

Fix:
Fix the RXPI check on the FRP
update as per the databook.

Bug 200766666

Change-Id: I4631623ec06bf815c88c5364f5ae599d0e7702dc
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587257
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mohan Thadikamalla
2021-08-16 14:09:06 +05:30
committed by mobile promotions
parent 6c53499842
commit c21e65e2a7
1 changed files with 10 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
osi/core/eqos_core.c
View File

@@ -1277,6 +1277,16 @@ static int eqos_config_frp(struct osi_core_priv_data *const osi_core,
val &= ~EQOS_MCR_RE; val &= ~EQOS_MCR_RE;
osi_writel(val, base + EQOS_MAC_MCR); osi_writel(val, base + EQOS_MAC_MCR);
op_mode = osi_readl(base + EQOS_MTL_OP_MODE);
if (enabled == OSI_ENABLE) {
/* Set FRPE bit of MTL_Operation_Mode register */
op_mode |= EQOS_MTL_OP_MODE_FRPE;
} else {
/* Reset FRPE bit of MTL_Operation_Mode register */
op_mode &= ~EQOS_MTL_OP_MODE_FRPE;
}
osi_writel(op_mode, base + EQOS_MTL_OP_MODE);
/* Verify RXPI bit set in MTL_RXP_Control_Status */ /* Verify RXPI bit set in MTL_RXP_Control_Status */
ret = osi_readl_poll_timeout((base + EQOS_MTL_RXP_CS), ret = osi_readl_poll_timeout((base + EQOS_MTL_RXP_CS),
(osi_core->osd_ops.udelay), (osi_core->osd_ops.udelay),
@@ -1292,29 +1302,20 @@ static int eqos_config_frp(struct osi_core_priv_data *const osi_core,
goto frp_enable_re; goto frp_enable_re;
} }
op_mode = osi_readl(base + EQOS_MTL_OP_MODE);
val = osi_readl(base + EQOS_MTL_RXP_INTR_CS); val = osi_readl(base + EQOS_MTL_RXP_INTR_CS);
if (enabled == OSI_ENABLE) { if (enabled == OSI_ENABLE) {
/* Set FRPE bit of MTL_Operation_Mode register */
op_mode |= EQOS_MTL_OP_MODE_FRPE;
/* Enable FRP Interrupt MTL_RXP_Interrupt_Control_Status */ /* Enable FRP Interrupt MTL_RXP_Interrupt_Control_Status */
val |= (EQOS_MTL_RXP_INTR_CS_NVEOVIE | val |= (EQOS_MTL_RXP_INTR_CS_NVEOVIE |
EQOS_MTL_RXP_INTR_CS_NPEOVIE | EQOS_MTL_RXP_INTR_CS_NPEOVIE |
EQOS_MTL_RXP_INTR_CS_FOOVIE | EQOS_MTL_RXP_INTR_CS_FOOVIE |
EQOS_MTL_RXP_INTR_CS_PDRFIE); EQOS_MTL_RXP_INTR_CS_PDRFIE);
} else { } else {
/* Reset FRPE bit of MTL_Operation_Mode register */
op_mode &= ~EQOS_MTL_OP_MODE_FRPE;
/* Disable FRP Interrupt MTL_RXP_Interrupt_Control_Status */ /* Disable FRP Interrupt MTL_RXP_Interrupt_Control_Status */
val = osi_readl(base + EQOS_MTL_RXP_INTR_CS);
val &= ~(EQOS_MTL_RXP_INTR_CS_NVEOVIE | val &= ~(EQOS_MTL_RXP_INTR_CS_NVEOVIE |
EQOS_MTL_RXP_INTR_CS_NPEOVIE | EQOS_MTL_RXP_INTR_CS_NPEOVIE |
EQOS_MTL_RXP_INTR_CS_FOOVIE | EQOS_MTL_RXP_INTR_CS_FOOVIE |
EQOS_MTL_RXP_INTR_CS_PDRFIE); EQOS_MTL_RXP_INTR_CS_PDRFIE);
} }
osi_writel(op_mode, base + EQOS_MTL_OP_MODE);
osi_writel(val, base + EQOS_MTL_RXP_INTR_CS); osi_writel(val, base + EQOS_MTL_RXP_INTR_CS);
frp_enable_re: frp_enable_re: