diff --git a/include/osi_core.h b/include/osi_core.h
index 17ad599..79ac7d3 100644
--- a/include/osi_core.h
+++ b/include/osi_core.h
@@ -134,7 +134,7 @@ struct  osi_core_avb_algorithm {
  */
 struct osi_core_ops {
 	/** Called to poll for software reset bit */
-	int (*poll_for_swr)(void *ioaddr);
+	int (*poll_for_swr)(void *ioaddr, unsigned int pre_si);
 	/** Called to initialize MAC and MTL registers */
 	int (*core_init)(struct osi_core_priv_data *const osi_core,
 			 const unsigned int tx_fifo_size,
@@ -393,6 +393,8 @@ struct osi_core_priv_data {
 	 * Value stored in MHz
 	 */
 	unsigned int csr_clk_speed;
+	/** Tegra Pre-si platform info */
+	unsigned int pre_si;
 };
 
 /**
diff --git a/osi/core/eqos_core.c b/osi/core/eqos_core.c
index 15dc40c..9998480 100644
--- a/osi/core/eqos_core.c
+++ b/osi/core/eqos_core.c
@@ -634,19 +634,23 @@ static int eqos_config_mac_loopback(void *addr,
  *	  Waits for SWR reset to be cleared in DMA Mode register.
  *
  * @param[in] addr: EQOS virtual base address.
+ * @param[in] pre_si: Sets whether platform is Pre-silicon or not.
  *
  * @note MAC needs to be out of reset and proper clock configured.
  *
  * @retval 0 on success
  * @retval -1 on failure.
  */
-static int eqos_poll_for_swr(void *addr)
+static int eqos_poll_for_swr(void *addr, unsigned int pre_si)
 {
 	unsigned int retry = 1000;
 	unsigned int count;
 	unsigned int dma_bmr = 0;
 	int cond = 1;
 
+	if (pre_si == OSI_ENABLE) {
+		osi_writel(0x1U, (unsigned char *)addr + EQOS_DMA_BMR);
+	}
 	/* add delay of 10 usec */
 	osd_usleep_range(9, 11);
 
diff --git a/osi/core/osi_core.c b/osi/core/osi_core.c
index 2429c7e..d3f020d 100644
--- a/osi/core/osi_core.c
+++ b/osi/core/osi_core.c
@@ -68,7 +68,8 @@ int osi_poll_for_mac_reset_complete(
 {
 	if ((osi_core != OSI_NULL) && (osi_core->ops != OSI_NULL) &&
 	    (osi_core->ops->poll_for_swr != OSI_NULL)) {
-		return osi_core->ops->poll_for_swr(osi_core->base);
+		return osi_core->ops->poll_for_swr(osi_core->base,
+						   osi_core->pre_si);
 	}
 	return -1;
 }